projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | * License. See the file "COPYING" in the main directory of this archive | |
| 4 | * for more details. | |
| 5 | * | |
| 6 | * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle | |
| 7 | * Copyright (C) 2000 Silicon Graphics, Inc. | |
| 8 | * Modified for further R[236]000 support by Paul M. Antoine, 1996. | |
| 9 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
| a3692020 | 10 | * Copyright (C) 2000, 07 MIPS Technologies, Inc. |
| 4194318c | 11 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
| 1da177e4 LT |
12 | */ |
| 13 | #ifndef _ASM_MIPSREGS_H | |
| 14 | #define _ASM_MIPSREGS_H | |
| 15 | ||
| 1da177e4 LT |
16 | #include <linux/linkage.h> |
| 17 | #include <asm/hazards.h> | |
| 9267a30d | 18 | #include <asm/war.h> |
| 1da177e4 LT |
19 | |
| 20 | /* | |
| 21 | * The following macros are especially useful for __asm__ | |
| 22 | * inline assembler. | |
| 23 | */ | |
| 24 | #ifndef __STR | |
| 25 | #define __STR(x) #x | |
| 26 | #endif | |
| 27 | #ifndef STR | |
| 28 | #define STR(x) __STR(x) | |
| 29 | #endif | |
| 30 | ||
| 31 | /* | |
| 32 | * Configure language | |
| 33 | */ | |
| 34 | #ifdef __ASSEMBLY__ | |
| 35 | #define _ULCAST_ | |
| 36 | #else | |
| 37 | #define _ULCAST_ (unsigned long) | |
| 38 | #endif | |
| 39 | ||
| 40 | /* | |
| 41 | * Coprocessor 0 register names | |
| 42 | */ | |
| 43 | #define CP0_INDEX $0 | |
| 44 | #define CP0_RANDOM $1 | |
| 45 | #define CP0_ENTRYLO0 $2 | |
| 46 | #define CP0_ENTRYLO1 $3 | |
| 47 | #define CP0_CONF $3 | |
| 48 | #define CP0_CONTEXT $4 | |
| 49 | #define CP0_PAGEMASK $5 | |
| 50 | #define CP0_WIRED $6 | |
| 51 | #define CP0_INFO $7 | |
| 52 | #define CP0_BADVADDR $8 | |
| 53 | #define CP0_COUNT $9 | |
| 54 | #define CP0_ENTRYHI $10 | |
| 55 | #define CP0_COMPARE $11 | |
| 56 | #define CP0_STATUS $12 | |
| 57 | #define CP0_CAUSE $13 | |
| 58 | #define CP0_EPC $14 | |
| 59 | #define CP0_PRID $15 | |
| 60 | #define CP0_CONFIG $16 | |
| 61 | #define CP0_LLADDR $17 | |
| 62 | #define CP0_WATCHLO $18 | |
| 63 | #define CP0_WATCHHI $19 | |
| 64 | #define CP0_XCONTEXT $20 | |
| 65 | #define CP0_FRAMEMASK $21 | |
| 66 | #define CP0_DIAGNOSTIC $22 | |
| 67 | #define CP0_DEBUG $23 | |
| 68 | #define CP0_DEPC $24 | |
| 69 | #define CP0_PERFORMANCE $25 | |
| 70 | #define CP0_ECC $26 | |
| 71 | #define CP0_CACHEERR $27 | |
| 72 | #define CP0_TAGLO $28 | |
| 73 | #define CP0_TAGHI $29 | |
| 74 | #define CP0_ERROREPC $30 | |
| 75 | #define CP0_DESAVE $31 | |
| 76 | ||
| 77 | /* | |
| 78 | * R4640/R4650 cp0 register names. These registers are listed | |
| 79 | * here only for completeness; without MMU these CPUs are not useable | |
| 80 | * by Linux. A future ELKS port might take make Linux run on them | |
| 81 | * though ... | |
| 82 | */ | |
| 83 | #define CP0_IBASE $0 | |
| 84 | #define CP0_IBOUND $1 | |
| 85 | #define CP0_DBASE $2 | |
| 86 | #define CP0_DBOUND $3 | |
| 87 | #define CP0_CALG $17 | |
| 88 | #define CP0_IWATCH $18 | |
| 89 | #define CP0_DWATCH $19 | |
| 90 | ||
| 91 | /* | |
| 92 | * Coprocessor 0 Set 1 register names | |
| 93 | */ | |
| 94 | #define CP0_S1_DERRADDR0 $26 | |
| 95 | #define CP0_S1_DERRADDR1 $27 | |
| 96 | #define CP0_S1_INTCONTROL $20 | |
| 97 | ||
| 7a0fc58c RB |
98 | /* |
| 99 | * Coprocessor 0 Set 2 register names | |
| 100 | */ | |
| 101 | #define CP0_S2_SRSCTL $12 /* MIPSR2 */ | |
| 102 | ||
| 103 | /* | |
| 104 | * Coprocessor 0 Set 3 register names | |
| 105 | */ | |
| 106 | #define CP0_S3_SRSMAP $12 /* MIPSR2 */ | |
| 107 | ||
| 1da177e4 LT |
108 | /* |
| 109 | * TX39 Series | |
| 110 | */ | |
| 111 | #define CP0_TX39_CACHE $7 | |
| 112 | ||
| 113 | /* | |
| 114 | * Coprocessor 1 (FPU) register names | |
| 115 | */ | |
| 116 | #define CP1_REVISION $0 | |
| 117 | #define CP1_STATUS $31 | |
| 118 | ||
| 119 | /* | |
| 120 | * FPU Status Register Values | |
| 121 | */ | |
| 122 | /* | |
| 123 | * Status Register Values | |
| 124 | */ | |
| 125 | ||
| 126 | #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ | |
| 127 | #define FPU_CSR_COND 0x00800000 /* $fcc0 */ | |
| 128 | #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ | |
| 129 | #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ | |
| 130 | #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ | |
| 131 | #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ | |
| 132 | #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ | |
| 133 | #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ | |
| 134 | #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ | |
| 135 | #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ | |
| 136 | ||
| 137 | /* | |
| 138 | * X the exception cause indicator | |
| 139 | * E the exception enable | |
| 140 | * S the sticky/flag bit | |
| 141 | */ | |
| 142 | #define FPU_CSR_ALL_X 0x0003f000 | |
| 143 | #define FPU_CSR_UNI_X 0x00020000 | |
| 144 | #define FPU_CSR_INV_X 0x00010000 | |
| 145 | #define FPU_CSR_DIV_X 0x00008000 | |
| 146 | #define FPU_CSR_OVF_X 0x00004000 | |
| 147 | #define FPU_CSR_UDF_X 0x00002000 | |
| 148 | #define FPU_CSR_INE_X 0x00001000 | |
| 149 | ||
| 150 | #define FPU_CSR_ALL_E 0x00000f80 | |
| 151 | #define FPU_CSR_INV_E 0x00000800 | |
| 152 | #define FPU_CSR_DIV_E 0x00000400 | |
| 153 | #define FPU_CSR_OVF_E 0x00000200 | |
| 154 | #define FPU_CSR_UDF_E 0x00000100 | |
| 155 | #define FPU_CSR_INE_E 0x00000080 | |
| 156 | ||
| 157 | #define FPU_CSR_ALL_S 0x0000007c | |
| 158 | #define FPU_CSR_INV_S 0x00000040 | |
| 159 | #define FPU_CSR_DIV_S 0x00000020 | |
| 160 | #define FPU_CSR_OVF_S 0x00000010 | |
| 161 | #define FPU_CSR_UDF_S 0x00000008 | |
| 162 | #define FPU_CSR_INE_S 0x00000004 | |
| 163 | ||
| 164 | /* rounding mode */ | |
| 165 | #define FPU_CSR_RN 0x0 /* nearest */ | |
| 166 | #define FPU_CSR_RZ 0x1 /* towards zero */ | |
| 167 | #define FPU_CSR_RU 0x2 /* towards +Infinity */ | |
| 168 | #define FPU_CSR_RD 0x3 /* towards -Infinity */ | |
| 169 | ||
| 170 | ||
| 171 | /* | |
| 172 | * Values for PageMask register | |
| 173 | */ | |
| 174 | #ifdef CONFIG_CPU_VR41XX | |
| 175 | ||
| 176 | /* Why doesn't stupidity hurt ... */ | |
| 177 | ||
| 178 | #define PM_1K 0x00000000 | |
| 179 | #define PM_4K 0x00001800 | |
| 180 | #define PM_16K 0x00007800 | |
| 181 | #define PM_64K 0x0001f800 | |
| 182 | #define PM_256K 0x0007f800 | |
| 183 | ||
| 184 | #else | |
| 185 | ||
| 186 | #define PM_4K 0x00000000 | |
| c52399be | 187 | #define PM_8K 0x00002000 |
| 1da177e4 | 188 | #define PM_16K 0x00006000 |
| c52399be | 189 | #define PM_32K 0x0000e000 |
| 1da177e4 | 190 | #define PM_64K 0x0001e000 |
| c52399be | 191 | #define PM_128K 0x0003e000 |
| 1da177e4 | 192 | #define PM_256K 0x0007e000 |
| c52399be | 193 | #define PM_512K 0x000fe000 |
| 1da177e4 | 194 | #define PM_1M 0x001fe000 |
| c52399be | 195 | #define PM_2M 0x003fe000 |
| 1da177e4 | 196 | #define PM_4M 0x007fe000 |
| c52399be | 197 | #define PM_8M 0x00ffe000 |
| 1da177e4 | 198 | #define PM_16M 0x01ffe000 |
| c52399be | 199 | #define PM_32M 0x03ffe000 |
| 1da177e4 LT |
200 | #define PM_64M 0x07ffe000 |
| 201 | #define PM_256M 0x1fffe000 | |
| 542c1020 | 202 | #define PM_1G 0x7fffe000 |
| 1da177e4 LT |
203 | |
| 204 | #endif | |
| 205 | ||
| 206 | /* | |
| 207 | * Default page size for a given kernel configuration | |
| 208 | */ | |
| 209 | #ifdef CONFIG_PAGE_SIZE_4KB | |
| 210 | #define PM_DEFAULT_MASK PM_4K | |
| c52399be RB |
211 | #elif defined(CONFIG_PAGE_SIZE_8KB) |
| 212 | #define PM_DEFAULT_MASK PM_8K | |
| 1da177e4 LT |
213 | #elif defined(CONFIG_PAGE_SIZE_16KB) |
| 214 | #define PM_DEFAULT_MASK PM_16K | |
| c52399be RB |
215 | #elif defined(CONFIG_PAGE_SIZE_32KB) |
| 216 | #define PM_DEFAULT_MASK PM_32K | |
| 1da177e4 LT |
217 | #elif defined(CONFIG_PAGE_SIZE_64KB) |
| 218 | #define PM_DEFAULT_MASK PM_64K | |
| 219 | #else | |
| 220 | #error Bad page size configuration! | |
| 221 | #endif | |
| 222 | ||
| dd794392 DD |
223 | /* |
| 224 | * Default huge tlb size for a given kernel configuration | |
| 225 | */ | |
| 226 | #ifdef CONFIG_PAGE_SIZE_4KB | |
| 227 | #define PM_HUGE_MASK PM_1M | |
| 228 | #elif defined(CONFIG_PAGE_SIZE_8KB) | |
| 229 | #define PM_HUGE_MASK PM_4M | |
| 230 | #elif defined(CONFIG_PAGE_SIZE_16KB) | |
| 231 | #define PM_HUGE_MASK PM_16M | |
| 232 | #elif defined(CONFIG_PAGE_SIZE_32KB) | |
| 233 | #define PM_HUGE_MASK PM_64M | |
| 234 | #elif defined(CONFIG_PAGE_SIZE_64KB) | |
| 235 | #define PM_HUGE_MASK PM_256M | |
| 236 | #elif defined(CONFIG_HUGETLB_PAGE) | |
| 237 | #error Bad page size configuration for hugetlbfs! | |
| 238 | #endif | |
| 1da177e4 LT |
239 | |
| 240 | /* | |
| 241 | * Values used for computation of new tlb entries | |
| 242 | */ | |
| 243 | #define PL_4K 12 | |
| 244 | #define PL_16K 14 | |
| 245 | #define PL_64K 16 | |
| 246 | #define PL_256K 18 | |
| 247 | #define PL_1M 20 | |
| 248 | #define PL_4M 22 | |
| 249 | #define PL_16M 24 | |
| 250 | #define PL_64M 26 | |
| 251 | #define PL_256M 28 | |
| 252 | ||
| 253 | /* | |
| 254 | * R4x00 interrupt enable / cause bits | |
| 255 | */ | |
| 256 | #define IE_SW0 (_ULCAST_(1) << 8) | |
| 257 | #define IE_SW1 (_ULCAST_(1) << 9) | |
| 258 | #define IE_IRQ0 (_ULCAST_(1) << 10) | |
| 259 | #define IE_IRQ1 (_ULCAST_(1) << 11) | |
| 260 | #define IE_IRQ2 (_ULCAST_(1) << 12) | |
| 261 | #define IE_IRQ3 (_ULCAST_(1) << 13) | |
| 262 | #define IE_IRQ4 (_ULCAST_(1) << 14) | |
| 263 | #define IE_IRQ5 (_ULCAST_(1) << 15) | |
| 264 | ||
| 265 | /* | |
| 266 | * R4x00 interrupt cause bits | |
| 267 | */ | |
| 268 | #define C_SW0 (_ULCAST_(1) << 8) | |
| 269 | #define C_SW1 (_ULCAST_(1) << 9) | |
| 270 | #define C_IRQ0 (_ULCAST_(1) << 10) | |
| 271 | #define C_IRQ1 (_ULCAST_(1) << 11) | |
| 272 | #define C_IRQ2 (_ULCAST_(1) << 12) | |
| 273 | #define C_IRQ3 (_ULCAST_(1) << 13) | |
| 274 | #define C_IRQ4 (_ULCAST_(1) << 14) | |
| 275 | #define C_IRQ5 (_ULCAST_(1) << 15) | |
| 276 | ||
| 277 | /* | |
| 278 | * Bitfields in the R4xx0 cp0 status register | |
| 279 | */ | |
| 280 | #define ST0_IE 0x00000001 | |
| 281 | #define ST0_EXL 0x00000002 | |
| 282 | #define ST0_ERL 0x00000004 | |
| 283 | #define ST0_KSU 0x00000018 | |
| 284 | # define KSU_USER 0x00000010 | |
| 285 | # define KSU_SUPERVISOR 0x00000008 | |
| 286 | # define KSU_KERNEL 0x00000000 | |
| 287 | #define ST0_UX 0x00000020 | |
| 288 | #define ST0_SX 0x00000040 | |
| 289 | #define ST0_KX 0x00000080 | |
| 290 | #define ST0_DE 0x00010000 | |
| 291 | #define ST0_CE 0x00020000 | |
| 292 | ||
| 293 | /* | |
| 294 | * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate | |
| 295 | * cacheops in userspace. This bit exists only on RM7000 and RM9000 | |
| 296 | * processors. | |
| 297 | */ | |
| 298 | #define ST0_CO 0x08000000 | |
| 299 | ||
| 300 | /* | |
| 301 | * Bitfields in the R[23]000 cp0 status register. | |
| 302 | */ | |
| 303 | #define ST0_IEC 0x00000001 | |
| 304 | #define ST0_KUC 0x00000002 | |
| 305 | #define ST0_IEP 0x00000004 | |
| 306 | #define ST0_KUP 0x00000008 | |
| 307 | #define ST0_IEO 0x00000010 | |
| 308 | #define ST0_KUO 0x00000020 | |
| 309 | /* bits 6 & 7 are reserved on R[23]000 */ | |
| 310 | #define ST0_ISC 0x00010000 | |
| 311 | #define ST0_SWC 0x00020000 | |
| 312 | #define ST0_CM 0x00080000 | |
| 313 | ||
| 314 | /* | |
| 315 | * Bits specific to the R4640/R4650 | |
| 316 | */ | |
| 317 | #define ST0_UM (_ULCAST_(1) << 4) | |
| 318 | #define ST0_IL (_ULCAST_(1) << 23) | |
| 319 | #define ST0_DL (_ULCAST_(1) << 24) | |
| 320 | ||
| e50c0a8f | 321 | /* |
| 3301edcb | 322 | * Enable the MIPS MDMX and DSP ASEs |
| e50c0a8f RB |
323 | */ |
| 324 | #define ST0_MX 0x01000000 | |
| 325 | ||
| 1da177e4 LT |
326 | /* |
| 327 | * Bitfields in the TX39 family CP0 Configuration Register 3 | |
| 328 | */ | |
| 329 | #define TX39_CONF_ICS_SHIFT 19 | |
| 330 | #define TX39_CONF_ICS_MASK 0x00380000 | |
| 331 | #define TX39_CONF_ICS_1KB 0x00000000 | |
| 332 | #define TX39_CONF_ICS_2KB 0x00080000 | |
| 333 | #define TX39_CONF_ICS_4KB 0x00100000 | |
| 334 | #define TX39_CONF_ICS_8KB 0x00180000 | |
| 335 | #define TX39_CONF_ICS_16KB 0x00200000 | |
| 336 | ||
| 337 | #define TX39_CONF_DCS_SHIFT 16 | |
| 338 | #define TX39_CONF_DCS_MASK 0x00070000 | |
| 339 | #define TX39_CONF_DCS_1KB 0x00000000 | |
| 340 | #define TX39_CONF_DCS_2KB 0x00010000 | |
| 341 | #define TX39_CONF_DCS_4KB 0x00020000 | |
| 342 | #define TX39_CONF_DCS_8KB 0x00030000 | |
| 343 | #define TX39_CONF_DCS_16KB 0x00040000 | |
| 344 | ||
| 345 | #define TX39_CONF_CWFON 0x00004000 | |
| 346 | #define TX39_CONF_WBON 0x00002000 | |
| 347 | #define TX39_CONF_RF_SHIFT 10 | |
| 348 | #define TX39_CONF_RF_MASK 0x00000c00 | |
| 349 | #define TX39_CONF_DOZE 0x00000200 | |
| 350 | #define TX39_CONF_HALT 0x00000100 | |
| 351 | #define TX39_CONF_LOCK 0x00000080 | |
| 352 | #define TX39_CONF_ICE 0x00000020 | |
| 353 | #define TX39_CONF_DCE 0x00000010 | |
| 354 | #define TX39_CONF_IRSIZE_SHIFT 2 | |
| 355 | #define TX39_CONF_IRSIZE_MASK 0x0000000c | |
| 356 | #define TX39_CONF_DRSIZE_SHIFT 0 | |
| 357 | #define TX39_CONF_DRSIZE_MASK 0x00000003 | |
| 358 | ||
| 359 | /* | |
| 360 | * Status register bits available in all MIPS CPUs. | |
| 361 | */ | |
| 362 | #define ST0_IM 0x0000ff00 | |
| 363 | #define STATUSB_IP0 8 | |
| 364 | #define STATUSF_IP0 (_ULCAST_(1) << 8) | |
| 365 | #define STATUSB_IP1 9 | |
| 366 | #define STATUSF_IP1 (_ULCAST_(1) << 9) | |
| 367 | #define STATUSB_IP2 10 | |
| 368 | #define STATUSF_IP2 (_ULCAST_(1) << 10) | |
| 369 | #define STATUSB_IP3 11 | |
| 370 | #define STATUSF_IP3 (_ULCAST_(1) << 11) | |
| 371 | #define STATUSB_IP4 12 | |
| 372 | #define STATUSF_IP4 (_ULCAST_(1) << 12) | |
| 373 | #define STATUSB_IP5 13 | |
| 374 | #define STATUSF_IP5 (_ULCAST_(1) << 13) | |
| 375 | #define STATUSB_IP6 14 | |
| 376 | #define STATUSF_IP6 (_ULCAST_(1) << 14) | |
| 377 | #define STATUSB_IP7 15 | |
| 378 | #define STATUSF_IP7 (_ULCAST_(1) << 15) | |
| 379 | #define STATUSB_IP8 0 | |
| 380 | #define STATUSF_IP8 (_ULCAST_(1) << 0) | |
| 381 | #define STATUSB_IP9 1 | |
| 382 | #define STATUSF_IP9 (_ULCAST_(1) << 1) | |
| 383 | #define STATUSB_IP10 2 | |
| 384 | #define STATUSF_IP10 (_ULCAST_(1) << 2) | |
| 385 | #define STATUSB_IP11 3 | |
| 386 | #define STATUSF_IP11 (_ULCAST_(1) << 3) | |
| 387 | #define STATUSB_IP12 4 | |
| 388 | #define STATUSF_IP12 (_ULCAST_(1) << 4) | |
| 389 | #define STATUSB_IP13 5 | |
| 390 | #define STATUSF_IP13 (_ULCAST_(1) << 5) | |
| 391 | #define STATUSB_IP14 6 | |
| 392 | #define STATUSF_IP14 (_ULCAST_(1) << 6) | |
| 393 | #define STATUSB_IP15 7 | |
| 394 | #define STATUSF_IP15 (_ULCAST_(1) << 7) | |
| 395 | #define ST0_CH 0x00040000 | |
| 396 | #define ST0_SR 0x00100000 | |
| 397 | #define ST0_TS 0x00200000 | |
| 398 | #define ST0_BEV 0x00400000 | |
| 399 | #define ST0_RE 0x02000000 | |
| 400 | #define ST0_FR 0x04000000 | |
| 401 | #define ST0_CU 0xf0000000 | |
| 402 | #define ST0_CU0 0x10000000 | |
| 403 | #define ST0_CU1 0x20000000 | |
| 404 | #define ST0_CU2 0x40000000 | |
| 405 | #define ST0_CU3 0x80000000 | |
| 406 | #define ST0_XX 0x80000000 /* MIPS IV naming */ | |
| 407 | ||
| 010c108d DV |
408 | /* |
| 409 | * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) | |
| 410 | * | |
| 411 | * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. | |
| 412 | */ | |
| 413 | #define INTCTLB_IPPCI 26 | |
| 414 | #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) | |
| 415 | #define INTCTLB_IPTI 29 | |
| 416 | #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) | |
| 417 | ||
| 1da177e4 LT |
418 | /* |
| 419 | * Bitfields and bit numbers in the coprocessor 0 cause register. | |
| 420 | * | |
| 421 | * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. | |
| 422 | */ | |
| 423 | #define CAUSEB_EXCCODE 2 | |
| 424 | #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) | |
| 425 | #define CAUSEB_IP 8 | |
| 426 | #define CAUSEF_IP (_ULCAST_(255) << 8) | |
| 427 | #define CAUSEB_IP0 8 | |
| 428 | #define CAUSEF_IP0 (_ULCAST_(1) << 8) | |
| 429 | #define CAUSEB_IP1 9 | |
| 430 | #define CAUSEF_IP1 (_ULCAST_(1) << 9) | |
| 431 | #define CAUSEB_IP2 10 | |
| 432 | #define CAUSEF_IP2 (_ULCAST_(1) << 10) | |
| 433 | #define CAUSEB_IP3 11 | |
| 434 | #define CAUSEF_IP3 (_ULCAST_(1) << 11) | |
| 435 | #define CAUSEB_IP4 12 | |
| 436 | #define CAUSEF_IP4 (_ULCAST_(1) << 12) | |
| 437 | #define CAUSEB_IP5 13 | |
| 438 | #define CAUSEF_IP5 (_ULCAST_(1) << 13) | |
| 439 | #define CAUSEB_IP6 14 | |
| 440 | #define CAUSEF_IP6 (_ULCAST_(1) << 14) | |
| 441 | #define CAUSEB_IP7 15 | |
| 442 | #define CAUSEF_IP7 (_ULCAST_(1) << 15) | |
| 443 | #define CAUSEB_IV 23 | |
| 444 | #define CAUSEF_IV (_ULCAST_(1) << 23) | |
| 445 | #define CAUSEB_CE 28 | |
| 446 | #define CAUSEF_CE (_ULCAST_(3) << 28) | |
| 010c108d DV |
447 | #define CAUSEB_TI 30 |
| 448 | #define CAUSEF_TI (_ULCAST_(1) << 30) | |
| 1da177e4 LT |
449 | #define CAUSEB_BD 31 |
| 450 | #define CAUSEF_BD (_ULCAST_(1) << 31) | |
| 451 | ||
| 452 | /* | |
| 453 | * Bits in the coprocessor 0 config register. | |
| 454 | */ | |
| 455 | /* Generic bits. */ | |
| 456 | #define CONF_CM_CACHABLE_NO_WA 0 | |
| 457 | #define CONF_CM_CACHABLE_WA 1 | |
| 458 | #define CONF_CM_UNCACHED 2 | |
| 459 | #define CONF_CM_CACHABLE_NONCOHERENT 3 | |
| 460 | #define CONF_CM_CACHABLE_CE 4 | |
| 461 | #define CONF_CM_CACHABLE_COW 5 | |
| 462 | #define CONF_CM_CACHABLE_CUW 6 | |
| 463 | #define CONF_CM_CACHABLE_ACCELERATED 7 | |
| 464 | #define CONF_CM_CMASK 7 | |
| 465 | #define CONF_BE (_ULCAST_(1) << 15) | |
| 466 | ||
| 467 | /* Bits common to various processors. */ | |
| 468 | #define CONF_CU (_ULCAST_(1) << 3) | |
| 469 | #define CONF_DB (_ULCAST_(1) << 4) | |
| 470 | #define CONF_IB (_ULCAST_(1) << 5) | |
| 471 | #define CONF_DC (_ULCAST_(7) << 6) | |
| 472 | #define CONF_IC (_ULCAST_(7) << 9) | |
| 473 | #define CONF_EB (_ULCAST_(1) << 13) | |
| 474 | #define CONF_EM (_ULCAST_(1) << 14) | |
| 475 | #define CONF_SM (_ULCAST_(1) << 16) | |
| 476 | #define CONF_SC (_ULCAST_(1) << 17) | |
| 477 | #define CONF_EW (_ULCAST_(3) << 18) | |
| 478 | #define CONF_EP (_ULCAST_(15)<< 24) | |
| 479 | #define CONF_EC (_ULCAST_(7) << 28) | |
| 480 | #define CONF_CM (_ULCAST_(1) << 31) | |
| 481 | ||
| 482 | /* Bits specific to the R4xx0. */ | |
| 483 | #define R4K_CONF_SW (_ULCAST_(1) << 20) | |
| 484 | #define R4K_CONF_SS (_ULCAST_(1) << 21) | |
| e20368d5 | 485 | #define R4K_CONF_SB (_ULCAST_(3) << 22) |
| 1da177e4 LT |
486 | |
| 487 | /* Bits specific to the R5000. */ | |
| 488 | #define R5K_CONF_SE (_ULCAST_(1) << 12) | |
| 489 | #define R5K_CONF_SS (_ULCAST_(3) << 20) | |
| 490 | ||
| ba5187db | 491 | /* Bits specific to the RM7000. */ |
| c6ad7b7d MR |
492 | #define RM7K_CONF_SE (_ULCAST_(1) << 3) |
| 493 | #define RM7K_CONF_TE (_ULCAST_(1) << 12) | |
| 494 | #define RM7K_CONF_CLK (_ULCAST_(1) << 16) | |
| 495 | #define RM7K_CONF_TC (_ULCAST_(1) << 17) | |
| 496 | #define RM7K_CONF_SI (_ULCAST_(3) << 20) | |
| 497 | #define RM7K_CONF_SC (_ULCAST_(1) << 31) | |
| ba5187db | 498 | |
| 1da177e4 LT |
499 | /* Bits specific to the R10000. */ |
| 500 | #define R10K_CONF_DN (_ULCAST_(3) << 3) | |
| 501 | #define R10K_CONF_CT (_ULCAST_(1) << 5) | |
| 502 | #define R10K_CONF_PE (_ULCAST_(1) << 6) | |
| 503 | #define R10K_CONF_PM (_ULCAST_(3) << 7) | |
| 504 | #define R10K_CONF_EC (_ULCAST_(15)<< 9) | |
| 505 | #define R10K_CONF_SB (_ULCAST_(1) << 13) | |
| 506 | #define R10K_CONF_SK (_ULCAST_(1) << 14) | |
| 507 | #define R10K_CONF_SS (_ULCAST_(7) << 16) | |
| 508 | #define R10K_CONF_SC (_ULCAST_(7) << 19) | |
| 509 | #define R10K_CONF_DC (_ULCAST_(7) << 26) | |
| 510 | #define R10K_CONF_IC (_ULCAST_(7) << 29) | |
| 511 | ||
| 512 | /* Bits specific to the VR41xx. */ | |
| 513 | #define VR41_CONF_CS (_ULCAST_(1) << 12) | |
| 2874fe55 | 514 | #define VR41_CONF_P4K (_ULCAST_(1) << 13) |
| 4e8ab361 | 515 | #define VR41_CONF_BP (_ULCAST_(1) << 16) |
| 1da177e4 LT |
516 | #define VR41_CONF_M16 (_ULCAST_(1) << 20) |
| 517 | #define VR41_CONF_AD (_ULCAST_(1) << 23) | |
| 518 | ||
| 519 | /* Bits specific to the R30xx. */ | |
| 520 | #define R30XX_CONF_FDM (_ULCAST_(1) << 19) | |
| 521 | #define R30XX_CONF_REV (_ULCAST_(1) << 22) | |
| 522 | #define R30XX_CONF_AC (_ULCAST_(1) << 23) | |
| 523 | #define R30XX_CONF_RF (_ULCAST_(1) << 24) | |
| 524 | #define R30XX_CONF_HALT (_ULCAST_(1) << 25) | |
| 525 | #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) | |
| 526 | #define R30XX_CONF_DBR (_ULCAST_(1) << 29) | |
| 527 | #define R30XX_CONF_SB (_ULCAST_(1) << 30) | |
| 528 | #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) | |
| 529 | ||
| 530 | /* Bits specific to the TX49. */ | |
| 531 | #define TX49_CONF_DC (_ULCAST_(1) << 16) | |
| 532 | #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ | |
| 533 | #define TX49_CONF_HALT (_ULCAST_(1) << 18) | |
| 534 | #define TX49_CONF_CWFON (_ULCAST_(1) << 27) | |
| 535 | ||
| 536 | /* Bits specific to the MIPS32/64 PRA. */ | |
| 537 | #define MIPS_CONF_MT (_ULCAST_(7) << 7) | |
| 538 | #define MIPS_CONF_AR (_ULCAST_(7) << 10) | |
| 539 | #define MIPS_CONF_AT (_ULCAST_(3) << 13) | |
| 540 | #define MIPS_CONF_M (_ULCAST_(1) << 31) | |
| 541 | ||
| 4194318c RB |
542 | /* |
| 543 | * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. | |
| 544 | */ | |
| 545 | #define MIPS_CONF1_FP (_ULCAST_(1) << 0) | |
| 546 | #define MIPS_CONF1_EP (_ULCAST_(1) << 1) | |
| 547 | #define MIPS_CONF1_CA (_ULCAST_(1) << 2) | |
| 548 | #define MIPS_CONF1_WR (_ULCAST_(1) << 3) | |
| 549 | #define MIPS_CONF1_PC (_ULCAST_(1) << 4) | |
| 550 | #define MIPS_CONF1_MD (_ULCAST_(1) << 5) | |
| 551 | #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) | |
| 552 | #define MIPS_CONF1_DA (_ULCAST_(7) << 7) | |
| 553 | #define MIPS_CONF1_DL (_ULCAST_(7) << 10) | |
| 554 | #define MIPS_CONF1_DS (_ULCAST_(7) << 13) | |
| 555 | #define MIPS_CONF1_IA (_ULCAST_(7) << 16) | |
| 556 | #define MIPS_CONF1_IL (_ULCAST_(7) << 19) | |
| 557 | #define MIPS_CONF1_IS (_ULCAST_(7) << 22) | |
| 558 | #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) | |
| 559 | ||
| 560 | #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) | |
| 561 | #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) | |
| 562 | #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) | |
| 563 | #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) | |
| 564 | #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) | |
| 565 | #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) | |
| 566 | #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) | |
| 567 | #define MIPS_CONF2_TU (_ULCAST_(7) << 28) | |
| 568 | ||
| 569 | #define MIPS_CONF3_TL (_ULCAST_(1) << 0) | |
| 570 | #define MIPS_CONF3_SM (_ULCAST_(1) << 1) | |
| 8f40611d | 571 | #define MIPS_CONF3_MT (_ULCAST_(1) << 2) |
| 4194318c RB |
572 | #define MIPS_CONF3_SP (_ULCAST_(1) << 4) |
| 573 | #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) | |
| 574 | #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) | |
| 575 | #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) | |
| e50c0a8f | 576 | #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) |
| a3692020 | 577 | #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) |
| 4194318c | 578 | |
| 4b3e975e RB |
579 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) |
| 580 | ||
| 9267a30d MSJ |
581 | #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) |
| 582 | ||
| 583 | ||
| 4194318c RB |
584 | /* |
| 585 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. | |
| 586 | */ | |
| 587 | #define MIPS_FPIR_S (_ULCAST_(1) << 16) | |
| 588 | #define MIPS_FPIR_D (_ULCAST_(1) << 17) | |
| 589 | #define MIPS_FPIR_PS (_ULCAST_(1) << 18) | |
| 590 | #define MIPS_FPIR_3D (_ULCAST_(1) << 19) | |
| 591 | #define MIPS_FPIR_W (_ULCAST_(1) << 20) | |
| 592 | #define MIPS_FPIR_L (_ULCAST_(1) << 21) | |
| 593 | #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) | |
| 594 | ||
| 1da177e4 LT |
595 | #ifndef __ASSEMBLY__ |
| 596 | ||
| 597 | /* | |
| 598 | * Functions to access the R10000 performance counters. These are basically | |
| 599 | * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit | |
| 600 | * performance counter number encoded into bits 1 ... 5 of the instruction. | |
| 601 | * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware | |
| 602 | * disassembler these will look like an access to sel 0 or 1. | |
| 603 | */ | |
| 604 | #define read_r10k_perf_cntr(counter) \ | |
| 605 | ({ \ | |
| 606 | unsigned int __res; \ | |
| 607 | __asm__ __volatile__( \ | |
| 608 | "mfpc\t%0, %1" \ | |
| 609 | : "=r" (__res) \ | |
| 610 | : "i" (counter)); \ | |
| 611 | \ | |
| 612 | __res; \ | |
| 613 | }) | |
| 614 | ||
| 615 | #define write_r10k_perf_cntr(counter,val) \ | |
| 616 | do { \ | |
| 617 | __asm__ __volatile__( \ | |
| 618 | "mtpc\t%0, %1" \ | |
| 619 | : \ | |
| 620 | : "r" (val), "i" (counter)); \ | |
| 621 | } while (0) | |
| 622 | ||
| 623 | #define read_r10k_perf_event(counter) \ | |
| 624 | ({ \ | |
| 625 | unsigned int __res; \ | |
| 626 | __asm__ __volatile__( \ | |
| 627 | "mfps\t%0, %1" \ | |
| 628 | : "=r" (__res) \ | |
| 629 | : "i" (counter)); \ | |
| 630 | \ | |
| 631 | __res; \ | |
| 632 | }) | |
| 633 | ||
| 634 | #define write_r10k_perf_cntl(counter,val) \ | |
| 635 | do { \ | |
| 636 | __asm__ __volatile__( \ | |
| 637 | "mtps\t%0, %1" \ | |
| 638 | : \ | |
| 639 | : "r" (val), "i" (counter)); \ | |
| 640 | } while (0) | |
| 641 | ||
| 642 | ||
| 643 | /* | |
| 644 | * Macros to access the system control coprocessor | |
| 645 | */ | |
| 646 | ||
| 647 | #define __read_32bit_c0_register(source, sel) \ | |
| 648 | ({ int __res; \ | |
| 649 | if (sel == 0) \ | |
| 650 | __asm__ __volatile__( \ | |
| 651 | "mfc0\t%0, " #source "\n\t" \ | |
| 652 | : "=r" (__res)); \ | |
| 653 | else \ | |
| 654 | __asm__ __volatile__( \ | |
| 655 | ".set\tmips32\n\t" \ | |
| 656 | "mfc0\t%0, " #source ", " #sel "\n\t" \ | |
| 657 | ".set\tmips0\n\t" \ | |
| 658 | : "=r" (__res)); \ | |
| 659 | __res; \ | |
| 660 | }) | |
| 661 | ||
| 662 | #define __read_64bit_c0_register(source, sel) \ | |
| 663 | ({ unsigned long long __res; \ | |
| 664 | if (sizeof(unsigned long) == 4) \ | |
| 665 | __res = __read_64bit_c0_split(source, sel); \ | |
| 666 | else if (sel == 0) \ | |
| 667 | __asm__ __volatile__( \ | |
| 668 | ".set\tmips3\n\t" \ | |
| 669 | "dmfc0\t%0, " #source "\n\t" \ | |
| 670 | ".set\tmips0" \ | |
| 671 | : "=r" (__res)); \ | |
| 672 | else \ | |
| 673 | __asm__ __volatile__( \ | |
| 674 | ".set\tmips64\n\t" \ | |
| 675 | "dmfc0\t%0, " #source ", " #sel "\n\t" \ | |
| 676 | ".set\tmips0" \ | |
| 677 | : "=r" (__res)); \ | |
| 678 | __res; \ | |
| 679 | }) | |
| 680 | ||
| 681 | #define __write_32bit_c0_register(register, sel, value) \ | |
| 682 | do { \ | |
| 683 | if (sel == 0) \ | |
| 684 | __asm__ __volatile__( \ | |
| 685 | "mtc0\t%z0, " #register "\n\t" \ | |
| 0952e290 | 686 | : : "Jr" ((unsigned int)(value))); \ |
| 1da177e4 LT |
687 | else \ |
| 688 | __asm__ __volatile__( \ | |
| 689 | ".set\tmips32\n\t" \ | |
| 690 | "mtc0\t%z0, " #register ", " #sel "\n\t" \ | |
| 691 | ".set\tmips0" \ | |
| 0952e290 | 692 | : : "Jr" ((unsigned int)(value))); \ |
| 1da177e4 LT |
693 | } while (0) |
| 694 | ||
| 695 | #define __write_64bit_c0_register(register, sel, value) \ | |
| 696 | do { \ | |
| 697 | if (sizeof(unsigned long) == 4) \ | |
| 698 | __write_64bit_c0_split(register, sel, value); \ | |
| 699 | else if (sel == 0) \ | |
| 700 | __asm__ __volatile__( \ | |
| 701 | ".set\tmips3\n\t" \ | |
| 702 | "dmtc0\t%z0, " #register "\n\t" \ | |
| 703 | ".set\tmips0" \ | |
| 704 | : : "Jr" (value)); \ | |
| 705 | else \ | |
| 706 | __asm__ __volatile__( \ | |
| 707 | ".set\tmips64\n\t" \ | |
| 708 | "dmtc0\t%z0, " #register ", " #sel "\n\t" \ | |
| 709 | ".set\tmips0" \ | |
| 710 | : : "Jr" (value)); \ | |
| 711 | } while (0) | |
| 712 | ||
| 713 | #define __read_ulong_c0_register(reg, sel) \ | |
| 714 | ((sizeof(unsigned long) == 4) ? \ | |
| 715 | (unsigned long) __read_32bit_c0_register(reg, sel) : \ | |
| 716 | (unsigned long) __read_64bit_c0_register(reg, sel)) | |
| 717 | ||
| 718 | #define __write_ulong_c0_register(reg, sel, val) \ | |
| 719 | do { \ | |
| 720 | if (sizeof(unsigned long) == 4) \ | |
| 721 | __write_32bit_c0_register(reg, sel, val); \ | |
| 722 | else \ | |
| 723 | __write_64bit_c0_register(reg, sel, val); \ | |
| 724 | } while (0) | |
| 725 | ||
| 726 | /* | |
| 727 | * On RM7000/RM9000 these are uses to access cop0 set 1 registers | |
| 728 | */ | |
| 729 | #define __read_32bit_c0_ctrl_register(source) \ | |
| 730 | ({ int __res; \ | |
| 731 | __asm__ __volatile__( \ | |
| 732 | "cfc0\t%0, " #source "\n\t" \ | |
| 733 | : "=r" (__res)); \ | |
| 734 | __res; \ | |
| 735 | }) | |
| 736 | ||
| 737 | #define __write_32bit_c0_ctrl_register(register, value) \ | |
| 738 | do { \ | |
| 739 | __asm__ __volatile__( \ | |
| 740 | "ctc0\t%z0, " #register "\n\t" \ | |
| 0952e290 | 741 | : : "Jr" ((unsigned int)(value))); \ |
| 1da177e4 LT |
742 | } while (0) |
| 743 | ||
| 744 | /* | |
| 745 | * These versions are only needed for systems with more than 38 bits of | |
| 746 | * physical address space running the 32-bit kernel. That's none atm :-) | |
| 747 | */ | |
| 748 | #define __read_64bit_c0_split(source, sel) \ | |
| 749 | ({ \ | |
| 87d43dd4 AN |
750 | unsigned long long __val; \ |
| 751 | unsigned long __flags; \ | |
| 1da177e4 | 752 | \ |
| 87d43dd4 | 753 | local_irq_save(__flags); \ |
| 1da177e4 LT |
754 | if (sel == 0) \ |
| 755 | __asm__ __volatile__( \ | |
| 756 | ".set\tmips64\n\t" \ | |
| 757 | "dmfc0\t%M0, " #source "\n\t" \ | |
| 758 | "dsll\t%L0, %M0, 32\n\t" \ | |
| 0b543526 RB |
759 | "dsra\t%M0, %M0, 32\n\t" \ |
| 760 | "dsra\t%L0, %L0, 32\n\t" \ | |
| 1da177e4 | 761 | ".set\tmips0" \ |
| 87d43dd4 | 762 | : "=r" (__val)); \ |
| 1da177e4 LT |
763 | else \ |
| 764 | __asm__ __volatile__( \ | |
| 765 | ".set\tmips64\n\t" \ | |
| 766 | "dmfc0\t%M0, " #source ", " #sel "\n\t" \ | |
| 767 | "dsll\t%L0, %M0, 32\n\t" \ | |
| 0b543526 RB |
768 | "dsra\t%M0, %M0, 32\n\t" \ |
| 769 | "dsra\t%L0, %L0, 32\n\t" \ | |
| 1da177e4 | 770 | ".set\tmips0" \ |
| 87d43dd4 AN |
771 | : "=r" (__val)); \ |
| 772 | local_irq_restore(__flags); \ | |
| 1da177e4 | 773 | \ |
| 87d43dd4 | 774 | __val; \ |
| 1da177e4 LT |
775 | }) |
| 776 | ||
| 777 | #define __write_64bit_c0_split(source, sel, val) \ | |
| 778 | do { \ | |
| 87d43dd4 | 779 | unsigned long __flags; \ |
| 1da177e4 | 780 | \ |
| 87d43dd4 | 781 | local_irq_save(__flags); \ |
| 1da177e4 LT |
782 | if (sel == 0) \ |
| 783 | __asm__ __volatile__( \ | |
| 784 | ".set\tmips64\n\t" \ | |
| 785 | "dsll\t%L0, %L0, 32\n\t" \ | |
| 786 | "dsrl\t%L0, %L0, 32\n\t" \ | |
| 787 | "dsll\t%M0, %M0, 32\n\t" \ | |
| 788 | "or\t%L0, %L0, %M0\n\t" \ | |
| 789 | "dmtc0\t%L0, " #source "\n\t" \ | |
| 790 | ".set\tmips0" \ | |
| 791 | : : "r" (val)); \ | |
| 792 | else \ | |
| 793 | __asm__ __volatile__( \ | |
| 794 | ".set\tmips64\n\t" \ | |
| 795 | "dsll\t%L0, %L0, 32\n\t" \ | |
| 796 | "dsrl\t%L0, %L0, 32\n\t" \ | |
| 797 | "dsll\t%M0, %M0, 32\n\t" \ | |
| 798 | "or\t%L0, %L0, %M0\n\t" \ | |
| 799 | "dmtc0\t%L0, " #source ", " #sel "\n\t" \ | |
| 800 | ".set\tmips0" \ | |
| 801 | : : "r" (val)); \ | |
| 87d43dd4 | 802 | local_irq_restore(__flags); \ |
| 1da177e4 LT |
803 | } while (0) |
| 804 | ||
| 805 | #define read_c0_index() __read_32bit_c0_register($0, 0) | |
| 806 | #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) | |
| 807 | ||
| 272bace7 RB |
808 | #define read_c0_random() __read_32bit_c0_register($1, 0) |
| 809 | #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) | |
| 810 | ||
| 1da177e4 LT |
811 | #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) |
| 812 | #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) | |
| 813 | ||
| 814 | #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) | |
| 815 | #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) | |
| 816 | ||
| 817 | #define read_c0_conf() __read_32bit_c0_register($3, 0) | |
| 818 | #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) | |
| 819 | ||
| 820 | #define read_c0_context() __read_ulong_c0_register($4, 0) | |
| 821 | #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) | |
| 822 | ||
| a3692020 RB |
823 | #define read_c0_userlocal() __read_ulong_c0_register($4, 2) |
| 824 | #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) | |
| 825 | ||
| 1da177e4 LT |
826 | #define read_c0_pagemask() __read_32bit_c0_register($5, 0) |
| 827 | #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) | |
| 828 | ||
| 829 | #define read_c0_wired() __read_32bit_c0_register($6, 0) | |
| 830 | #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) | |
| 831 | ||
| 832 | #define read_c0_info() __read_32bit_c0_register($7, 0) | |
| 833 | ||
| 834 | #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ | |
| 835 | #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) | |
| 836 | ||
| 15c4f67a RB |
837 | #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) |
| 838 | #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) | |
| 839 | ||
| 1da177e4 LT |
840 | #define read_c0_count() __read_32bit_c0_register($9, 0) |
| 841 | #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) | |
| 842 | ||
| bdf21b18 PP |
843 | #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ |
| 844 | #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) | |
| 845 | ||
| 846 | #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ | |
| 847 | #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) | |
| 848 | ||
| 1da177e4 LT |
849 | #define read_c0_entryhi() __read_ulong_c0_register($10, 0) |
| 850 | #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) | |
| 851 | ||
| 852 | #define read_c0_compare() __read_32bit_c0_register($11, 0) | |
| 853 | #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) | |
| 854 | ||
| bdf21b18 PP |
855 | #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ |
| 856 | #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) | |
| 857 | ||
| 858 | #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ | |
| 859 | #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) | |
| 860 | ||
| 1da177e4 | 861 | #define read_c0_status() __read_32bit_c0_register($12, 0) |
| 41c594ab RB |
862 | #ifdef CONFIG_MIPS_MT_SMTC |
| 863 | #define write_c0_status(val) \ | |
| 864 | do { \ | |
| 865 | __write_32bit_c0_register($12, 0, val); \ | |
| 866 | __ehb(); \ | |
| 867 | } while (0) | |
| 868 | #else | |
| 869 | /* | |
| 870 | * Legacy non-SMTC code, which may be hazardous | |
| 871 | * but which might not support EHB | |
| 872 | */ | |
| 1da177e4 | 873 | #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) |
| 41c594ab | 874 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 1da177e4 LT |
875 | |
| 876 | #define read_c0_cause() __read_32bit_c0_register($13, 0) | |
| 877 | #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) | |
| 878 | ||
| 879 | #define read_c0_epc() __read_ulong_c0_register($14, 0) | |
| 880 | #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) | |
| 881 | ||
| 882 | #define read_c0_prid() __read_32bit_c0_register($15, 0) | |
| 883 | ||
| 884 | #define read_c0_config() __read_32bit_c0_register($16, 0) | |
| 885 | #define read_c0_config1() __read_32bit_c0_register($16, 1) | |
| 886 | #define read_c0_config2() __read_32bit_c0_register($16, 2) | |
| 887 | #define read_c0_config3() __read_32bit_c0_register($16, 3) | |
| 0efe2761 RB |
888 | #define read_c0_config4() __read_32bit_c0_register($16, 4) |
| 889 | #define read_c0_config5() __read_32bit_c0_register($16, 5) | |
| 890 | #define read_c0_config6() __read_32bit_c0_register($16, 6) | |
| 891 | #define read_c0_config7() __read_32bit_c0_register($16, 7) | |
| 1da177e4 LT |
892 | #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) |
| 893 | #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) | |
| 894 | #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) | |
| 895 | #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) | |
| 0efe2761 RB |
896 | #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) |
| 897 | #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) | |
| 898 | #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) | |
| 899 | #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) | |
| 1da177e4 LT |
900 | |
| 901 | /* | |
| 902 | * The WatchLo register. There may be upto 8 of them. | |
| 903 | */ | |
| 904 | #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) | |
| 905 | #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) | |
| 906 | #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) | |
| 907 | #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) | |
| 908 | #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) | |
| 909 | #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) | |
| 910 | #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) | |
| 911 | #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) | |
| 912 | #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) | |
| 913 | #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) | |
| 914 | #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) | |
| 915 | #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) | |
| 916 | #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) | |
| 917 | #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) | |
| 918 | #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) | |
| 919 | #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) | |
| 920 | ||
| 921 | /* | |
| 922 | * The WatchHi register. There may be upto 8 of them. | |
| 923 | */ | |
| 924 | #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) | |
| 925 | #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) | |
| 926 | #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) | |
| 927 | #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) | |
| 928 | #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) | |
| 929 | #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) | |
| 930 | #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) | |
| 931 | #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) | |
| 932 | ||
| 933 | #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) | |
| 934 | #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) | |
| 935 | #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) | |
| 936 | #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) | |
| 937 | #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) | |
| 938 | #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) | |
| 939 | #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) | |
| 940 | #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) | |
| 941 | ||
| 942 | #define read_c0_xcontext() __read_ulong_c0_register($20, 0) | |
| 943 | #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) | |
| 944 | ||
| 945 | #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) | |
| 946 | #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) | |
| 947 | ||
| 948 | #define read_c0_framemask() __read_32bit_c0_register($21, 0) | |
| 949 | #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) | |
| 950 | ||
| 951 | /* RM9000 PerfControl performance counter control register */ | |
| 952 | #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) | |
| 953 | #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) | |
| 954 | ||
| 955 | #define read_c0_diag() __read_32bit_c0_register($22, 0) | |
| 956 | #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) | |
| 957 | ||
| 958 | #define read_c0_diag1() __read_32bit_c0_register($22, 1) | |
| 959 | #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) | |
| 960 | ||
| 961 | #define read_c0_diag2() __read_32bit_c0_register($22, 2) | |
| 962 | #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) | |
| 963 | ||
| 964 | #define read_c0_diag3() __read_32bit_c0_register($22, 3) | |
| 965 | #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) | |
| 966 | ||
| 967 | #define read_c0_diag4() __read_32bit_c0_register($22, 4) | |
| 968 | #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) | |
| 969 | ||
| 970 | #define read_c0_diag5() __read_32bit_c0_register($22, 5) | |
| 971 | #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) | |
| 972 | ||
| 973 | #define read_c0_debug() __read_32bit_c0_register($23, 0) | |
| 974 | #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) | |
| 975 | ||
| 976 | #define read_c0_depc() __read_ulong_c0_register($24, 0) | |
| 977 | #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) | |
| 978 | ||
| 979 | /* | |
| 980 | * MIPS32 / MIPS64 performance counters | |
| 981 | */ | |
| 982 | #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) | |
| 983 | #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) | |
| 984 | #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) | |
| 985 | #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) | |
| 986 | #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) | |
| 987 | #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) | |
| 988 | #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) | |
| 989 | #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) | |
| 990 | #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) | |
| 991 | #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) | |
| 992 | #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) | |
| 993 | #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) | |
| 994 | #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) | |
| 995 | #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) | |
| 996 | #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) | |
| 997 | #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) | |
| 998 | ||
| 999 | /* RM9000 PerfCount performance counter register */ | |
| 1000 | #define read_c0_perfcount() __read_64bit_c0_register($25, 0) | |
| 1001 | #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) | |
| 1002 | ||
| 1003 | #define read_c0_ecc() __read_32bit_c0_register($26, 0) | |
| 1004 | #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) | |
| 1005 | ||
| 1006 | #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) | |
| 1007 | #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) | |
| 1008 | ||
| 1009 | #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) | |
| 1010 | ||
| 1011 | #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) | |
| 1012 | #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) | |
| 1013 | ||
| 1014 | #define read_c0_taglo() __read_32bit_c0_register($28, 0) | |
| 1015 | #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) | |
| 1016 | ||
| 41c594ab RB |
1017 | #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) |
| 1018 | #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) | |
| 1019 | ||
| 1da177e4 LT |
1020 | #define read_c0_taghi() __read_32bit_c0_register($29, 0) |
| 1021 | #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) | |
| 1022 | ||
| 1023 | #define read_c0_errorepc() __read_ulong_c0_register($30, 0) | |
| 1024 | #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) | |
| 1025 | ||
| 7a0fc58c | 1026 | /* MIPSR2 */ |
| 21a151d8 | 1027 | #define read_c0_hwrena() __read_32bit_c0_register($7, 0) |
| 7a0fc58c RB |
1028 | #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) |
| 1029 | ||
| 1030 | #define read_c0_intctl() __read_32bit_c0_register($12, 1) | |
| 1031 | #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) | |
| 1032 | ||
| 1033 | #define read_c0_srsctl() __read_32bit_c0_register($12, 2) | |
| 1034 | #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) | |
| 1035 | ||
| 1036 | #define read_c0_srsmap() __read_32bit_c0_register($12, 3) | |
| 1037 | #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) | |
| 1038 | ||
| 21a151d8 | 1039 | #define read_c0_ebase() __read_32bit_c0_register($15, 1) |
| 7a0fc58c RB |
1040 | #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) |
| 1041 | ||
| ed918c2d DD |
1042 | |
| 1043 | /* Cavium OCTEON (cnMIPS) */ | |
| 1044 | #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) | |
| 1045 | #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) | |
| 1046 | ||
| 1047 | #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) | |
| 1048 | #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) | |
| 1049 | ||
| 1050 | #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) | |
| 1051 | #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) | |
| 1052 | /* | |
| 1053 | * The cacheerr registers are not standardized. On OCTEON, they are | |
| 1054 | * 64 bits wide. | |
| 1055 | */ | |
| 1056 | #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) | |
| 1057 | #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) | |
| 1058 | ||
| 1059 | #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) | |
| 1060 | #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) | |
| 1061 | ||
| 1da177e4 LT |
1062 | /* |
| 1063 | * Macros to access the floating point coprocessor control registers | |
| 1064 | */ | |
| 1065 | #define read_32bit_cp1_register(source) \ | |
| 1066 | ({ int __res; \ | |
| 1067 | __asm__ __volatile__( \ | |
| 1068 | ".set\tpush\n\t" \ | |
| 1069 | ".set\treorder\n\t" \ | |
| 25c30003 DD |
1070 | /* gas fails to assemble cfc1 for some archs (octeon).*/ \ |
| 1071 | ".set\tmips1\n\t" \ | |
| 1da177e4 LT |
1072 | "cfc1\t%0,"STR(source)"\n\t" \ |
| 1073 | ".set\tpop" \ | |
| 1074 | : "=r" (__res)); \ | |
| 1075 | __res;}) | |
| 1076 | ||
| e50c0a8f RB |
1077 | #define rddsp(mask) \ |
| 1078 | ({ \ | |
| 1079 | unsigned int __res; \ | |
| 1080 | \ | |
| 1081 | __asm__ __volatile__( \ | |
| 1082 | " .set push \n" \ | |
| 1083 | " .set noat \n" \ | |
| 1084 | " # rddsp $1, %x1 \n" \ | |
| 1085 | " .word 0x7c000cb8 | (%x1 << 16) \n" \ | |
| 1086 | " move %0, $1 \n" \ | |
| 1087 | " .set pop \n" \ | |
| 1088 | : "=r" (__res) \ | |
| 1089 | : "i" (mask)); \ | |
| 1090 | __res; \ | |
| 1091 | }) | |
| 1092 | ||
| 1093 | #define wrdsp(val, mask) \ | |
| 1094 | do { \ | |
| e50c0a8f RB |
1095 | __asm__ __volatile__( \ |
| 1096 | " .set push \n" \ | |
| 1097 | " .set noat \n" \ | |
| 1098 | " move $1, %0 \n" \ | |
| 1099 | " # wrdsp $1, %x1 \n" \ | |
| 26487957 | 1100 | " .word 0x7c2004f8 | (%x1 << 11) \n" \ |
| e50c0a8f RB |
1101 | " .set pop \n" \ |
| 1102 | : \ | |
| 1103 | : "r" (val), "i" (mask)); \ | |
| e50c0a8f RB |
1104 | } while (0) |
| 1105 | ||
| 1106 | #if 0 /* Need DSP ASE capable assembler ... */ | |
| 1107 | #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) | |
| 1108 | #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) | |
| 1109 | #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) | |
| 1110 | #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) | |
| 1111 | ||
| 1112 | #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) | |
| 1113 | #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) | |
| 1114 | #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) | |
| 1115 | #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) | |
| 1116 | ||
| 1117 | #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) | |
| 1118 | #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) | |
| 1119 | #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) | |
| 1120 | #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) | |
| 1121 | ||
| 1122 | #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) | |
| 1123 | #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) | |
| 1124 | #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) | |
| 1125 | #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) | |
| 1126 | ||
| 1127 | #else | |
| 1128 | ||
| 1129 | #define mfhi0() \ | |
| 1130 | ({ \ | |
| 1131 | unsigned long __treg; \ | |
| 1132 | \ | |
| 1133 | __asm__ __volatile__( \ | |
| 1134 | " .set push \n" \ | |
| 1135 | " .set noat \n" \ | |
| 1136 | " # mfhi %0, $ac0 \n" \ | |
| 1137 | " .word 0x00000810 \n" \ | |
| 1138 | " move %0, $1 \n" \ | |
| 1139 | " .set pop \n" \ | |
| 1140 | : "=r" (__treg)); \ | |
| 1141 | __treg; \ | |
| 1142 | }) | |
| 1143 | ||
| 1144 | #define mfhi1() \ | |
| 1145 | ({ \ | |
| 1146 | unsigned long __treg; \ | |
| 1147 | \ | |
| 1148 | __asm__ __volatile__( \ | |
| 1149 | " .set push \n" \ | |
| 1150 | " .set noat \n" \ | |
| 1151 | " # mfhi %0, $ac1 \n" \ | |
| 1152 | " .word 0x00200810 \n" \ | |
| 1153 | " move %0, $1 \n" \ | |
| 1154 | " .set pop \n" \ | |
| 1155 | : "=r" (__treg)); \ | |
| 1156 | __treg; \ | |
| 1157 | }) | |
| 1158 | ||
| 1159 | #define mfhi2() \ | |
| 1160 | ({ \ | |
| 1161 | unsigned long __treg; \ | |
| 1162 | \ | |
| 1163 | __asm__ __volatile__( \ | |
| 1164 | " .set push \n" \ | |
| 1165 | " .set noat \n" \ | |
| 1166 | " # mfhi %0, $ac2 \n" \ | |
| 1167 | " .word 0x00400810 \n" \ | |
| 1168 | " move %0, $1 \n" \ | |
| 1169 | " .set pop \n" \ | |
| 1170 | : "=r" (__treg)); \ | |
| 1171 | __treg; \ | |
| 1172 | }) | |
| 1173 | ||
| 1174 | #define mfhi3() \ | |
| 1175 | ({ \ | |
| 1176 | unsigned long __treg; \ | |
| 1177 | \ | |
| 1178 | __asm__ __volatile__( \ | |
| 1179 | " .set push \n" \ | |
| 1180 | " .set noat \n" \ | |
| 1181 | " # mfhi %0, $ac3 \n" \ | |
| 1182 | " .word 0x00600810 \n" \ | |
| 1183 | " move %0, $1 \n" \ | |
| 1184 | " .set pop \n" \ | |
| 1185 | : "=r" (__treg)); \ | |
| 1186 | __treg; \ | |
| 1187 | }) | |
| 1188 | ||
| 1189 | #define mflo0() \ | |
| 1190 | ({ \ | |
| 1191 | unsigned long __treg; \ | |
| 1192 | \ | |
| 1193 | __asm__ __volatile__( \ | |
| 1194 | " .set push \n" \ | |
| 1195 | " .set noat \n" \ | |
| 1196 | " # mflo %0, $ac0 \n" \ | |
| 1197 | " .word 0x00000812 \n" \ | |
| 1198 | " move %0, $1 \n" \ | |
| 1199 | " .set pop \n" \ | |
| 1200 | : "=r" (__treg)); \ | |
| 1201 | __treg; \ | |
| 1202 | }) | |
| 1203 | ||
| 1204 | #define mflo1() \ | |
| 1205 | ({ \ | |
| 1206 | unsigned long __treg; \ | |
| 1207 | \ | |
| 1208 | __asm__ __volatile__( \ | |
| 1209 | " .set push \n" \ | |
| 1210 | " .set noat \n" \ | |
| 1211 | " # mflo %0, $ac1 \n" \ | |
| 1212 | " .word 0x00200812 \n" \ | |
| 1213 | " move %0, $1 \n" \ | |
| 1214 | " .set pop \n" \ | |
| 1215 | : "=r" (__treg)); \ | |
| 1216 | __treg; \ | |
| 1217 | }) | |
| 1218 | ||
| 1219 | #define mflo2() \ | |
| 1220 | ({ \ | |
| 1221 | unsigned long __treg; \ | |
| 1222 | \ | |
| 1223 | __asm__ __volatile__( \ | |
| 1224 | " .set push \n" \ | |
| 1225 | " .set noat \n" \ | |
| 1226 | " # mflo %0, $ac2 \n" \ | |
| 1227 | " .word 0x00400812 \n" \ | |
| 1228 | " move %0, $1 \n" \ | |
| 1229 | " .set pop \n" \ | |
| 1230 | : "=r" (__treg)); \ | |
| 1231 | __treg; \ | |
| 1232 | }) | |
| 1233 | ||
| 1234 | #define mflo3() \ | |
| 1235 | ({ \ | |
| 1236 | unsigned long __treg; \ | |
| 1237 | \ | |
| 1238 | __asm__ __volatile__( \ | |
| 1239 | " .set push \n" \ | |
| 1240 | " .set noat \n" \ | |
| 1241 | " # mflo %0, $ac3 \n" \ | |
| 1242 | " .word 0x00600812 \n" \ | |
| 1243 | " move %0, $1 \n" \ | |
| 1244 | " .set pop \n" \ | |
| 1245 | : "=r" (__treg)); \ | |
| 1246 | __treg; \ | |
| 1247 | }) | |
| 1248 | ||
| 1249 | #define mthi0(x) \ | |
| 1250 | do { \ | |
| 1251 | __asm__ __volatile__( \ | |
| 1252 | " .set push \n" \ | |
| 1253 | " .set noat \n" \ | |
| 1254 | " move $1, %0 \n" \ | |
| 1255 | " # mthi $1, $ac0 \n" \ | |
| 1256 | " .word 0x00200011 \n" \ | |
| 1257 | " .set pop \n" \ | |
| 1258 | : \ | |
| 1259 | : "r" (x)); \ | |
| 1260 | } while (0) | |
| 1261 | ||
| 1262 | #define mthi1(x) \ | |
| 1263 | do { \ | |
| 1264 | __asm__ __volatile__( \ | |
| 1265 | " .set push \n" \ | |
| 1266 | " .set noat \n" \ | |
| 1267 | " move $1, %0 \n" \ | |
| 1268 | " # mthi $1, $ac1 \n" \ | |
| 1269 | " .word 0x00200811 \n" \ | |
| 1270 | " .set pop \n" \ | |
| 1271 | : \ | |
| 1272 | : "r" (x)); \ | |
| 1273 | } while (0) | |
| 1274 | ||
| 1275 | #define mthi2(x) \ | |
| 1276 | do { \ | |
| 1277 | __asm__ __volatile__( \ | |
| 1278 | " .set push \n" \ | |
| 1279 | " .set noat \n" \ | |
| 1280 | " move $1, %0 \n" \ | |
| 1281 | " # mthi $1, $ac2 \n" \ | |
| 1282 | " .word 0x00201011 \n" \ | |
| 1283 | " .set pop \n" \ | |
| 1284 | : \ | |
| 1285 | : "r" (x)); \ | |
| 1286 | } while (0) | |
| 1287 | ||
| 1288 | #define mthi3(x) \ | |
| 1289 | do { \ | |
| 1290 | __asm__ __volatile__( \ | |
| 1291 | " .set push \n" \ | |
| 1292 | " .set noat \n" \ | |
| 1293 | " move $1, %0 \n" \ | |
| 1294 | " # mthi $1, $ac3 \n" \ | |
| 1295 | " .word 0x00201811 \n" \ | |
| 1296 | " .set pop \n" \ | |
| 1297 | : \ | |
| 1298 | : "r" (x)); \ | |
| 1299 | } while (0) | |
| 1300 | ||
| 1301 | #define mtlo0(x) \ | |
| 1302 | do { \ | |
| 1303 | __asm__ __volatile__( \ | |
| 1304 | " .set push \n" \ | |
| 1305 | " .set noat \n" \ | |
| 1306 | " move $1, %0 \n" \ | |
| 1307 | " # mtlo $1, $ac0 \n" \ | |
| 1308 | " .word 0x00200013 \n" \ | |
| 1309 | " .set pop \n" \ | |
| 1310 | : \ | |
| 1311 | : "r" (x)); \ | |
| 1312 | } while (0) | |
| 1313 | ||
| 1314 | #define mtlo1(x) \ | |
| 1315 | do { \ | |
| 1316 | __asm__ __volatile__( \ | |
| 1317 | " .set push \n" \ | |
| 1318 | " .set noat \n" \ | |
| 1319 | " move $1, %0 \n" \ | |
| 1320 | " # mtlo $1, $ac1 \n" \ | |
| 1321 | " .word 0x00200813 \n" \ | |
| 1322 | " .set pop \n" \ | |
| 1323 | : \ | |
| 1324 | : "r" (x)); \ | |
| 1325 | } while (0) | |
| 1326 | ||
| 1327 | #define mtlo2(x) \ | |
| 1328 | do { \ | |
| 1329 | __asm__ __volatile__( \ | |
| 1330 | " .set push \n" \ | |
| 1331 | " .set noat \n" \ | |
| 1332 | " move $1, %0 \n" \ | |
| 1333 | " # mtlo $1, $ac2 \n" \ | |
| 1334 | " .word 0x00201013 \n" \ | |
| 1335 | " .set pop \n" \ | |
| 1336 | : \ | |
| 1337 | : "r" (x)); \ | |
| 1338 | } while (0) | |
| 1339 | ||
| 1340 | #define mtlo3(x) \ | |
| 1341 | do { \ | |
| 1342 | __asm__ __volatile__( \ | |
| 1343 | " .set push \n" \ | |
| 1344 | " .set noat \n" \ | |
| 1345 | " move $1, %0 \n" \ | |
| 1346 | " # mtlo $1, $ac3 \n" \ | |
| 1347 | " .word 0x00201813 \n" \ | |
| 1348 | " .set pop \n" \ | |
| 1349 | : \ | |
| 1350 | : "r" (x)); \ | |
| 1351 | } while (0) | |
| 1352 | ||
| 1353 | #endif | |
| 1354 | ||
| 1da177e4 LT |
1355 | /* |
| 1356 | * TLB operations. | |
| 1357 | * | |
| 1358 | * It is responsibility of the caller to take care of any TLB hazards. | |
| 1359 | */ | |
| 1360 | static inline void tlb_probe(void) | |
| 1361 | { | |
| 1362 | __asm__ __volatile__( | |
| 1363 | ".set noreorder\n\t" | |
| 1364 | "tlbp\n\t" | |
| 1365 | ".set reorder"); | |
| 1366 | } | |
| 1367 | ||
| 1368 | static inline void tlb_read(void) | |
| 1369 | { | |
| 9267a30d MSJ |
1370 | #if MIPS34K_MISSED_ITLB_WAR |
| 1371 | int res = 0; | |
| 1372 | ||
| 1373 | __asm__ __volatile__( | |
| 1374 | " .set push \n" | |
| 1375 | " .set noreorder \n" | |
| 1376 | " .set noat \n" | |
| 1377 | " .set mips32r2 \n" | |
| 1378 | " .word 0x41610001 # dvpe $1 \n" | |
| 1379 | " move %0, $1 \n" | |
| 1380 | " ehb \n" | |
| 1381 | " .set pop \n" | |
| 1382 | : "=r" (res)); | |
| 1383 | ||
| 1384 | instruction_hazard(); | |
| 1385 | #endif | |
| 1386 | ||
| 1da177e4 LT |
1387 | __asm__ __volatile__( |
| 1388 | ".set noreorder\n\t" | |
| 1389 | "tlbr\n\t" | |
| 1390 | ".set reorder"); | |
| 9267a30d MSJ |
1391 | |
| 1392 | #if MIPS34K_MISSED_ITLB_WAR | |
| 1393 | if ((res & _ULCAST_(1))) | |
| 1394 | __asm__ __volatile__( | |
| 1395 | " .set push \n" | |
| 1396 | " .set noreorder \n" | |
| 1397 | " .set noat \n" | |
| 1398 | " .set mips32r2 \n" | |
| 1399 | " .word 0x41600021 # evpe \n" | |
| 1400 | " ehb \n" | |
| 1401 | " .set pop \n"); | |
| 1402 | #endif | |
| 1da177e4 LT |
1403 | } |
| 1404 | ||
| 1405 | static inline void tlb_write_indexed(void) | |
| 1406 | { | |
| 1407 | __asm__ __volatile__( | |
| 1408 | ".set noreorder\n\t" | |
| 1409 | "tlbwi\n\t" | |
| 1410 | ".set reorder"); | |
| 1411 | } | |
| 1412 | ||
| 1413 | static inline void tlb_write_random(void) | |
| 1414 | { | |
| 1415 | __asm__ __volatile__( | |
| 1416 | ".set noreorder\n\t" | |
| 1417 | "tlbwr\n\t" | |
| 1418 | ".set reorder"); | |
| 1419 | } | |
| 1420 | ||
| 1421 | /* | |
| 1422 | * Manipulate bits in a c0 register. | |
| 1423 | */ | |
| 41c594ab RB |
1424 | #ifndef CONFIG_MIPS_MT_SMTC |
| 1425 | /* | |
| 1426 | * SMTC Linux requires shutting-down microthread scheduling | |
| 1427 | * during CP0 register read-modify-write sequences. | |
| 1428 | */ | |
| 1da177e4 LT |
1429 | #define __BUILD_SET_C0(name) \ |
| 1430 | static inline unsigned int \ | |
| 1431 | set_c0_##name(unsigned int set) \ | |
| 1432 | { \ | |
| 89e18eb3 | 1433 | unsigned int res, new; \ |
| 1da177e4 LT |
1434 | \ |
| 1435 | res = read_c0_##name(); \ | |
| 89e18eb3 RB |
1436 | new = res | set; \ |
| 1437 | write_c0_##name(new); \ | |
| 1da177e4 LT |
1438 | \ |
| 1439 | return res; \ | |
| 1440 | } \ | |
| 1441 | \ | |
| 1442 | static inline unsigned int \ | |
| 1443 | clear_c0_##name(unsigned int clear) \ | |
| 1444 | { \ | |
| 89e18eb3 | 1445 | unsigned int res, new; \ |
| 1da177e4 LT |
1446 | \ |
| 1447 | res = read_c0_##name(); \ | |
| 89e18eb3 RB |
1448 | new = res & ~clear; \ |
| 1449 | write_c0_##name(new); \ | |
| 1da177e4 LT |
1450 | \ |
| 1451 | return res; \ | |
| 1452 | } \ | |
| 1453 | \ | |
| 1454 | static inline unsigned int \ | |
| 89e18eb3 | 1455 | change_c0_##name(unsigned int change, unsigned int val) \ |
| 1da177e4 | 1456 | { \ |
| 89e18eb3 | 1457 | unsigned int res, new; \ |
| 1da177e4 LT |
1458 | \ |
| 1459 | res = read_c0_##name(); \ | |
| 89e18eb3 RB |
1460 | new = res & ~change; \ |
| 1461 | new |= (val & change); \ | |
| 1462 | write_c0_##name(new); \ | |
| 1da177e4 LT |
1463 | \ |
| 1464 | return res; \ | |
| 1465 | } | |
| 1466 | ||
| 41c594ab RB |
1467 | #else /* SMTC versions that manage MT scheduling */ |
| 1468 | ||
| 192ef366 | 1469 | #include <linux/irqflags.h> |
| 41c594ab RB |
1470 | |
| 1471 | /* | |
| 1472 | * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with | |
| 1473 | * header file recursion. | |
| 1474 | */ | |
| 1475 | static inline unsigned int __dmt(void) | |
| 1476 | { | |
| 1477 | int res; | |
| 1478 | ||
| 1479 | __asm__ __volatile__( | |
| 1480 | " .set push \n" | |
| 1481 | " .set mips32r2 \n" | |
| 1482 | " .set noat \n" | |
| 1483 | " .word 0x41610BC1 # dmt $1 \n" | |
| 1484 | " ehb \n" | |
| 1485 | " move %0, $1 \n" | |
| 1486 | " .set pop \n" | |
| 1487 | : "=r" (res)); | |
| 1488 | ||
| 1489 | instruction_hazard(); | |
| 1490 | ||
| 1491 | return res; | |
| 1492 | } | |
| 1493 | ||
| 1494 | #define __VPECONTROL_TE_SHIFT 15 | |
| 1495 | #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) | |
| 1496 | ||
| 1497 | #define __EMT_ENABLE __VPECONTROL_TE | |
| 1498 | ||
| 1499 | static inline void __emt(unsigned int previous) | |
| 1500 | { | |
| 1501 | if ((previous & __EMT_ENABLE)) | |
| 1502 | __asm__ __volatile__( | |
| 41c594ab RB |
1503 | " .set mips32r2 \n" |
| 1504 | " .word 0x41600be1 # emt \n" | |
| 1505 | " ehb \n" | |
| 1bd5e161 | 1506 | " .set mips0 \n"); |
| 41c594ab RB |
1507 | } |
| 1508 | ||
| 1509 | static inline void __ehb(void) | |
| 1510 | { | |
| 1511 | __asm__ __volatile__( | |
| 4277ff5e RB |
1512 | " .set mips32r2 \n" |
| 1513 | " ehb \n" " .set mips0 \n"); | |
| 41c594ab RB |
1514 | } |
| 1515 | ||
| 1516 | /* | |
| 1517 | * Note that local_irq_save/restore affect TC-specific IXMT state, | |
| 1518 | * not Status.IE as in non-SMTC kernel. | |
| 1519 | */ | |
| 1520 | ||
| 1521 | #define __BUILD_SET_C0(name) \ | |
| 1522 | static inline unsigned int \ | |
| 1523 | set_c0_##name(unsigned int set) \ | |
| 1524 | { \ | |
| 1525 | unsigned int res; \ | |
| c34e6e8b | 1526 | unsigned int new; \ |
| 41c594ab | 1527 | unsigned int omt; \ |
| b7e4226e | 1528 | unsigned long flags; \ |
| 41c594ab RB |
1529 | \ |
| 1530 | local_irq_save(flags); \ | |
| 1531 | omt = __dmt(); \ | |
| 1532 | res = read_c0_##name(); \ | |
| c34e6e8b KK |
1533 | new = res | set; \ |
| 1534 | write_c0_##name(new); \ | |
| 41c594ab RB |
1535 | __emt(omt); \ |
| 1536 | local_irq_restore(flags); \ | |
| 1537 | \ | |
| 1538 | return res; \ | |
| 1539 | } \ | |
| 1540 | \ | |
| 1541 | static inline unsigned int \ | |
| 1542 | clear_c0_##name(unsigned int clear) \ | |
| 1543 | { \ | |
| 1544 | unsigned int res; \ | |
| c34e6e8b | 1545 | unsigned int new; \ |
| 41c594ab | 1546 | unsigned int omt; \ |
| b7e4226e | 1547 | unsigned long flags; \ |
| 41c594ab RB |
1548 | \ |
| 1549 | local_irq_save(flags); \ | |
| 1550 | omt = __dmt(); \ | |
| 1551 | res = read_c0_##name(); \ | |
| c34e6e8b KK |
1552 | new = res & ~clear; \ |
| 1553 | write_c0_##name(new); \ | |
| 41c594ab RB |
1554 | __emt(omt); \ |
| 1555 | local_irq_restore(flags); \ | |
| 1556 | \ | |
| 1557 | return res; \ | |
| 1558 | } \ | |
| 1559 | \ | |
| 1560 | static inline unsigned int \ | |
| c34e6e8b | 1561 | change_c0_##name(unsigned int change, unsigned int newbits) \ |
| 41c594ab RB |
1562 | { \ |
| 1563 | unsigned int res; \ | |
| c34e6e8b | 1564 | unsigned int new; \ |
| 41c594ab | 1565 | unsigned int omt; \ |
| b7e4226e | 1566 | unsigned long flags; \ |
| 41c594ab RB |
1567 | \ |
| 1568 | local_irq_save(flags); \ | |
| 1569 | \ | |
| 1570 | omt = __dmt(); \ | |
| 1571 | res = read_c0_##name(); \ | |
| c34e6e8b KK |
1572 | new = res & ~change; \ |
| 1573 | new |= (newbits & change); \ | |
| 1574 | write_c0_##name(new); \ | |
| 41c594ab RB |
1575 | __emt(omt); \ |
| 1576 | local_irq_restore(flags); \ | |
| 1577 | \ | |
| 1578 | return res; \ | |
| 1579 | } | |
| 1580 | #endif | |
| 1581 | ||
| 1da177e4 LT |
1582 | __BUILD_SET_C0(status) |
| 1583 | __BUILD_SET_C0(cause) | |
| 1584 | __BUILD_SET_C0(config) | |
| 1585 | __BUILD_SET_C0(intcontrol) | |
| 7a0fc58c RB |
1586 | __BUILD_SET_C0(intctl) |
| 1587 | __BUILD_SET_C0(srsmap) | |
| 1da177e4 LT |
1588 | |
| 1589 | #endif /* !__ASSEMBLY__ */ | |
| 1590 | ||
| 1591 | #endif /* _ASM_MIPSREGS_H */ |