Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle | |
7 | * Copyright (C) 2000 Silicon Graphics, Inc. | |
8 | * Modified for further R[236]000 support by Paul M. Antoine, 1996. | |
9 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
a3692020 | 10 | * Copyright (C) 2000, 07 MIPS Technologies, Inc. |
4194318c | 11 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
1da177e4 LT |
12 | */ |
13 | #ifndef _ASM_MIPSREGS_H | |
14 | #define _ASM_MIPSREGS_H | |
15 | ||
1da177e4 | 16 | #include <linux/linkage.h> |
87c99203 | 17 | #include <linux/types.h> |
1da177e4 | 18 | #include <asm/hazards.h> |
9267a30d | 19 | #include <asm/war.h> |
1da177e4 LT |
20 | |
21 | /* | |
22 | * The following macros are especially useful for __asm__ | |
23 | * inline assembler. | |
24 | */ | |
25 | #ifndef __STR | |
26 | #define __STR(x) #x | |
27 | #endif | |
28 | #ifndef STR | |
29 | #define STR(x) __STR(x) | |
30 | #endif | |
31 | ||
32 | /* | |
33 | * Configure language | |
34 | */ | |
35 | #ifdef __ASSEMBLY__ | |
36 | #define _ULCAST_ | |
37 | #else | |
38 | #define _ULCAST_ (unsigned long) | |
39 | #endif | |
40 | ||
41 | /* | |
42 | * Coprocessor 0 register names | |
43 | */ | |
44 | #define CP0_INDEX $0 | |
45 | #define CP0_RANDOM $1 | |
46 | #define CP0_ENTRYLO0 $2 | |
47 | #define CP0_ENTRYLO1 $3 | |
48 | #define CP0_CONF $3 | |
49 | #define CP0_CONTEXT $4 | |
50 | #define CP0_PAGEMASK $5 | |
51 | #define CP0_WIRED $6 | |
52 | #define CP0_INFO $7 | |
195cee92 | 53 | #define CP0_HWRENA $7, 0 |
1da177e4 | 54 | #define CP0_BADVADDR $8 |
609cf6f2 | 55 | #define CP0_BADINSTR $8, 1 |
1da177e4 LT |
56 | #define CP0_COUNT $9 |
57 | #define CP0_ENTRYHI $10 | |
58 | #define CP0_COMPARE $11 | |
59 | #define CP0_STATUS $12 | |
60 | #define CP0_CAUSE $13 | |
61 | #define CP0_EPC $14 | |
62 | #define CP0_PRID $15 | |
609cf6f2 PB |
63 | #define CP0_EBASE $15, 1 |
64 | #define CP0_CMGCRBASE $15, 3 | |
1da177e4 | 65 | #define CP0_CONFIG $16 |
195cee92 JH |
66 | #define CP0_CONFIG3 $16, 3 |
67 | #define CP0_CONFIG5 $16, 5 | |
1da177e4 LT |
68 | #define CP0_LLADDR $17 |
69 | #define CP0_WATCHLO $18 | |
70 | #define CP0_WATCHHI $19 | |
71 | #define CP0_XCONTEXT $20 | |
72 | #define CP0_FRAMEMASK $21 | |
73 | #define CP0_DIAGNOSTIC $22 | |
74 | #define CP0_DEBUG $23 | |
75 | #define CP0_DEPC $24 | |
76 | #define CP0_PERFORMANCE $25 | |
77 | #define CP0_ECC $26 | |
78 | #define CP0_CACHEERR $27 | |
79 | #define CP0_TAGLO $28 | |
80 | #define CP0_TAGHI $29 | |
81 | #define CP0_ERROREPC $30 | |
82 | #define CP0_DESAVE $31 | |
83 | ||
84 | /* | |
85 | * R4640/R4650 cp0 register names. These registers are listed | |
86 | * here only for completeness; without MMU these CPUs are not useable | |
87 | * by Linux. A future ELKS port might take make Linux run on them | |
88 | * though ... | |
89 | */ | |
90 | #define CP0_IBASE $0 | |
91 | #define CP0_IBOUND $1 | |
92 | #define CP0_DBASE $2 | |
93 | #define CP0_DBOUND $3 | |
94 | #define CP0_CALG $17 | |
95 | #define CP0_IWATCH $18 | |
96 | #define CP0_DWATCH $19 | |
97 | ||
98 | /* | |
99 | * Coprocessor 0 Set 1 register names | |
100 | */ | |
101 | #define CP0_S1_DERRADDR0 $26 | |
102 | #define CP0_S1_DERRADDR1 $27 | |
103 | #define CP0_S1_INTCONTROL $20 | |
104 | ||
7a0fc58c RB |
105 | /* |
106 | * Coprocessor 0 Set 2 register names | |
107 | */ | |
108 | #define CP0_S2_SRSCTL $12 /* MIPSR2 */ | |
109 | ||
110 | /* | |
111 | * Coprocessor 0 Set 3 register names | |
112 | */ | |
113 | #define CP0_S3_SRSMAP $12 /* MIPSR2 */ | |
114 | ||
1da177e4 LT |
115 | /* |
116 | * TX39 Series | |
117 | */ | |
118 | #define CP0_TX39_CACHE $7 | |
119 | ||
1da177e4 | 120 | |
bae637a2 JH |
121 | /* Generic EntryLo bit definitions */ |
122 | #define ENTRYLO_G (_ULCAST_(1) << 0) | |
123 | #define ENTRYLO_V (_ULCAST_(1) << 1) | |
124 | #define ENTRYLO_D (_ULCAST_(1) << 2) | |
125 | #define ENTRYLO_C_SHIFT 3 | |
126 | #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT) | |
127 | ||
128 | /* R3000 EntryLo bit definitions */ | |
129 | #define R3K_ENTRYLO_G (_ULCAST_(1) << 8) | |
130 | #define R3K_ENTRYLO_V (_ULCAST_(1) << 9) | |
131 | #define R3K_ENTRYLO_D (_ULCAST_(1) << 10) | |
132 | #define R3K_ENTRYLO_N (_ULCAST_(1) << 11) | |
133 | ||
134 | /* MIPS32/64 EntryLo bit definitions */ | |
135 | #ifdef CONFIG_64BIT | |
136 | /* as read by dmfc0 */ | |
137 | #define MIPS_ENTRYLO_XI (_ULCAST_(1) << 62) | |
138 | #define MIPS_ENTRYLO_RI (_ULCAST_(1) << 63) | |
139 | #else | |
140 | /* as read by mfc0 */ | |
141 | #define MIPS_ENTRYLO_XI (_ULCAST_(1) << 30) | |
142 | #define MIPS_ENTRYLO_RI (_ULCAST_(1) << 31) | |
143 | #endif | |
144 | ||
1da177e4 LT |
145 | /* |
146 | * Values for PageMask register | |
147 | */ | |
148 | #ifdef CONFIG_CPU_VR41XX | |
149 | ||
150 | /* Why doesn't stupidity hurt ... */ | |
151 | ||
152 | #define PM_1K 0x00000000 | |
153 | #define PM_4K 0x00001800 | |
154 | #define PM_16K 0x00007800 | |
155 | #define PM_64K 0x0001f800 | |
156 | #define PM_256K 0x0007f800 | |
157 | ||
158 | #else | |
159 | ||
160 | #define PM_4K 0x00000000 | |
c52399be | 161 | #define PM_8K 0x00002000 |
1da177e4 | 162 | #define PM_16K 0x00006000 |
c52399be | 163 | #define PM_32K 0x0000e000 |
1da177e4 | 164 | #define PM_64K 0x0001e000 |
c52399be | 165 | #define PM_128K 0x0003e000 |
1da177e4 | 166 | #define PM_256K 0x0007e000 |
c52399be | 167 | #define PM_512K 0x000fe000 |
1da177e4 | 168 | #define PM_1M 0x001fe000 |
c52399be | 169 | #define PM_2M 0x003fe000 |
1da177e4 | 170 | #define PM_4M 0x007fe000 |
c52399be | 171 | #define PM_8M 0x00ffe000 |
1da177e4 | 172 | #define PM_16M 0x01ffe000 |
c52399be | 173 | #define PM_32M 0x03ffe000 |
1da177e4 LT |
174 | #define PM_64M 0x07ffe000 |
175 | #define PM_256M 0x1fffe000 | |
542c1020 | 176 | #define PM_1G 0x7fffe000 |
1da177e4 LT |
177 | |
178 | #endif | |
179 | ||
180 | /* | |
181 | * Default page size for a given kernel configuration | |
182 | */ | |
183 | #ifdef CONFIG_PAGE_SIZE_4KB | |
70342287 | 184 | #define PM_DEFAULT_MASK PM_4K |
c52399be | 185 | #elif defined(CONFIG_PAGE_SIZE_8KB) |
70342287 | 186 | #define PM_DEFAULT_MASK PM_8K |
1da177e4 | 187 | #elif defined(CONFIG_PAGE_SIZE_16KB) |
70342287 | 188 | #define PM_DEFAULT_MASK PM_16K |
c52399be | 189 | #elif defined(CONFIG_PAGE_SIZE_32KB) |
70342287 | 190 | #define PM_DEFAULT_MASK PM_32K |
1da177e4 | 191 | #elif defined(CONFIG_PAGE_SIZE_64KB) |
70342287 | 192 | #define PM_DEFAULT_MASK PM_64K |
1da177e4 LT |
193 | #else |
194 | #error Bad page size configuration! | |
195 | #endif | |
196 | ||
dd794392 DD |
197 | /* |
198 | * Default huge tlb size for a given kernel configuration | |
199 | */ | |
200 | #ifdef CONFIG_PAGE_SIZE_4KB | |
201 | #define PM_HUGE_MASK PM_1M | |
202 | #elif defined(CONFIG_PAGE_SIZE_8KB) | |
203 | #define PM_HUGE_MASK PM_4M | |
204 | #elif defined(CONFIG_PAGE_SIZE_16KB) | |
205 | #define PM_HUGE_MASK PM_16M | |
206 | #elif defined(CONFIG_PAGE_SIZE_32KB) | |
207 | #define PM_HUGE_MASK PM_64M | |
208 | #elif defined(CONFIG_PAGE_SIZE_64KB) | |
209 | #define PM_HUGE_MASK PM_256M | |
aa1762f4 | 210 | #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) |
dd794392 DD |
211 | #error Bad page size configuration for hugetlbfs! |
212 | #endif | |
1da177e4 LT |
213 | |
214 | /* | |
215 | * Values used for computation of new tlb entries | |
216 | */ | |
217 | #define PL_4K 12 | |
218 | #define PL_16K 14 | |
219 | #define PL_64K 16 | |
220 | #define PL_256K 18 | |
221 | #define PL_1M 20 | |
222 | #define PL_4M 22 | |
223 | #define PL_16M 24 | |
224 | #define PL_64M 26 | |
225 | #define PL_256M 28 | |
226 | ||
9fe2e9d6 DD |
227 | /* |
228 | * PageGrain bits | |
229 | */ | |
70342287 RB |
230 | #define PG_RIE (_ULCAST_(1) << 31) |
231 | #define PG_XIE (_ULCAST_(1) << 30) | |
232 | #define PG_ELPA (_ULCAST_(1) << 29) | |
233 | #define PG_ESP (_ULCAST_(1) << 28) | |
6575b1d4 | 234 | #define PG_IEC (_ULCAST_(1) << 27) |
9fe2e9d6 | 235 | |
bae637a2 JH |
236 | /* MIPS32/64 EntryHI bit definitions */ |
237 | #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) | |
238 | ||
1da177e4 LT |
239 | /* |
240 | * R4x00 interrupt enable / cause bits | |
241 | */ | |
70342287 RB |
242 | #define IE_SW0 (_ULCAST_(1) << 8) |
243 | #define IE_SW1 (_ULCAST_(1) << 9) | |
244 | #define IE_IRQ0 (_ULCAST_(1) << 10) | |
245 | #define IE_IRQ1 (_ULCAST_(1) << 11) | |
246 | #define IE_IRQ2 (_ULCAST_(1) << 12) | |
247 | #define IE_IRQ3 (_ULCAST_(1) << 13) | |
248 | #define IE_IRQ4 (_ULCAST_(1) << 14) | |
249 | #define IE_IRQ5 (_ULCAST_(1) << 15) | |
1da177e4 LT |
250 | |
251 | /* | |
252 | * R4x00 interrupt cause bits | |
253 | */ | |
70342287 RB |
254 | #define C_SW0 (_ULCAST_(1) << 8) |
255 | #define C_SW1 (_ULCAST_(1) << 9) | |
256 | #define C_IRQ0 (_ULCAST_(1) << 10) | |
257 | #define C_IRQ1 (_ULCAST_(1) << 11) | |
258 | #define C_IRQ2 (_ULCAST_(1) << 12) | |
259 | #define C_IRQ3 (_ULCAST_(1) << 13) | |
260 | #define C_IRQ4 (_ULCAST_(1) << 14) | |
261 | #define C_IRQ5 (_ULCAST_(1) << 15) | |
1da177e4 LT |
262 | |
263 | /* | |
264 | * Bitfields in the R4xx0 cp0 status register | |
265 | */ | |
266 | #define ST0_IE 0x00000001 | |
267 | #define ST0_EXL 0x00000002 | |
268 | #define ST0_ERL 0x00000004 | |
269 | #define ST0_KSU 0x00000018 | |
270 | # define KSU_USER 0x00000010 | |
271 | # define KSU_SUPERVISOR 0x00000008 | |
272 | # define KSU_KERNEL 0x00000000 | |
273 | #define ST0_UX 0x00000020 | |
274 | #define ST0_SX 0x00000040 | |
70342287 | 275 | #define ST0_KX 0x00000080 |
1da177e4 LT |
276 | #define ST0_DE 0x00010000 |
277 | #define ST0_CE 0x00020000 | |
278 | ||
279 | /* | |
280 | * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate | |
281 | * cacheops in userspace. This bit exists only on RM7000 and RM9000 | |
282 | * processors. | |
283 | */ | |
284 | #define ST0_CO 0x08000000 | |
285 | ||
286 | /* | |
287 | * Bitfields in the R[23]000 cp0 status register. | |
288 | */ | |
70342287 | 289 | #define ST0_IEC 0x00000001 |
1da177e4 LT |
290 | #define ST0_KUC 0x00000002 |
291 | #define ST0_IEP 0x00000004 | |
292 | #define ST0_KUP 0x00000008 | |
293 | #define ST0_IEO 0x00000010 | |
294 | #define ST0_KUO 0x00000020 | |
295 | /* bits 6 & 7 are reserved on R[23]000 */ | |
296 | #define ST0_ISC 0x00010000 | |
297 | #define ST0_SWC 0x00020000 | |
298 | #define ST0_CM 0x00080000 | |
299 | ||
300 | /* | |
301 | * Bits specific to the R4640/R4650 | |
302 | */ | |
70342287 | 303 | #define ST0_UM (_ULCAST_(1) << 4) |
1da177e4 LT |
304 | #define ST0_IL (_ULCAST_(1) << 23) |
305 | #define ST0_DL (_ULCAST_(1) << 24) | |
306 | ||
e50c0a8f | 307 | /* |
3301edcb | 308 | * Enable the MIPS MDMX and DSP ASEs |
e50c0a8f RB |
309 | */ |
310 | #define ST0_MX 0x01000000 | |
311 | ||
1da177e4 LT |
312 | /* |
313 | * Status register bits available in all MIPS CPUs. | |
314 | */ | |
315 | #define ST0_IM 0x0000ff00 | |
70342287 RB |
316 | #define STATUSB_IP0 8 |
317 | #define STATUSF_IP0 (_ULCAST_(1) << 8) | |
318 | #define STATUSB_IP1 9 | |
319 | #define STATUSF_IP1 (_ULCAST_(1) << 9) | |
320 | #define STATUSB_IP2 10 | |
321 | #define STATUSF_IP2 (_ULCAST_(1) << 10) | |
322 | #define STATUSB_IP3 11 | |
323 | #define STATUSF_IP3 (_ULCAST_(1) << 11) | |
324 | #define STATUSB_IP4 12 | |
325 | #define STATUSF_IP4 (_ULCAST_(1) << 12) | |
326 | #define STATUSB_IP5 13 | |
327 | #define STATUSF_IP5 (_ULCAST_(1) << 13) | |
328 | #define STATUSB_IP6 14 | |
329 | #define STATUSF_IP6 (_ULCAST_(1) << 14) | |
330 | #define STATUSB_IP7 15 | |
331 | #define STATUSF_IP7 (_ULCAST_(1) << 15) | |
332 | #define STATUSB_IP8 0 | |
333 | #define STATUSF_IP8 (_ULCAST_(1) << 0) | |
334 | #define STATUSB_IP9 1 | |
335 | #define STATUSF_IP9 (_ULCAST_(1) << 1) | |
336 | #define STATUSB_IP10 2 | |
337 | #define STATUSF_IP10 (_ULCAST_(1) << 2) | |
338 | #define STATUSB_IP11 3 | |
339 | #define STATUSF_IP11 (_ULCAST_(1) << 3) | |
340 | #define STATUSB_IP12 4 | |
341 | #define STATUSF_IP12 (_ULCAST_(1) << 4) | |
342 | #define STATUSB_IP13 5 | |
343 | #define STATUSF_IP13 (_ULCAST_(1) << 5) | |
344 | #define STATUSB_IP14 6 | |
345 | #define STATUSF_IP14 (_ULCAST_(1) << 6) | |
346 | #define STATUSB_IP15 7 | |
347 | #define STATUSF_IP15 (_ULCAST_(1) << 7) | |
1da177e4 | 348 | #define ST0_CH 0x00040000 |
96ffa02d | 349 | #define ST0_NMI 0x00080000 |
1da177e4 LT |
350 | #define ST0_SR 0x00100000 |
351 | #define ST0_TS 0x00200000 | |
352 | #define ST0_BEV 0x00400000 | |
353 | #define ST0_RE 0x02000000 | |
354 | #define ST0_FR 0x04000000 | |
355 | #define ST0_CU 0xf0000000 | |
356 | #define ST0_CU0 0x10000000 | |
357 | #define ST0_CU1 0x20000000 | |
358 | #define ST0_CU2 0x40000000 | |
359 | #define ST0_CU3 0x80000000 | |
360 | #define ST0_XX 0x80000000 /* MIPS IV naming */ | |
361 | ||
010c108d DV |
362 | /* |
363 | * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) | |
010c108d | 364 | */ |
9323f84f JH |
365 | #define INTCTLB_IPFDC 23 |
366 | #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC) | |
010c108d DV |
367 | #define INTCTLB_IPPCI 26 |
368 | #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) | |
369 | #define INTCTLB_IPTI 29 | |
370 | #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) | |
371 | ||
1da177e4 LT |
372 | /* |
373 | * Bitfields and bit numbers in the coprocessor 0 cause register. | |
374 | * | |
375 | * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. | |
376 | */ | |
1054533a MR |
377 | #define CAUSEB_EXCCODE 2 |
378 | #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) | |
379 | #define CAUSEB_IP 8 | |
380 | #define CAUSEF_IP (_ULCAST_(255) << 8) | |
70342287 RB |
381 | #define CAUSEB_IP0 8 |
382 | #define CAUSEF_IP0 (_ULCAST_(1) << 8) | |
383 | #define CAUSEB_IP1 9 | |
384 | #define CAUSEF_IP1 (_ULCAST_(1) << 9) | |
385 | #define CAUSEB_IP2 10 | |
386 | #define CAUSEF_IP2 (_ULCAST_(1) << 10) | |
387 | #define CAUSEB_IP3 11 | |
388 | #define CAUSEF_IP3 (_ULCAST_(1) << 11) | |
389 | #define CAUSEB_IP4 12 | |
390 | #define CAUSEF_IP4 (_ULCAST_(1) << 12) | |
391 | #define CAUSEB_IP5 13 | |
392 | #define CAUSEF_IP5 (_ULCAST_(1) << 13) | |
393 | #define CAUSEB_IP6 14 | |
394 | #define CAUSEF_IP6 (_ULCAST_(1) << 14) | |
395 | #define CAUSEB_IP7 15 | |
396 | #define CAUSEF_IP7 (_ULCAST_(1) << 15) | |
1054533a MR |
397 | #define CAUSEB_FDCI 21 |
398 | #define CAUSEF_FDCI (_ULCAST_(1) << 21) | |
399 | #define CAUSEB_IV 23 | |
400 | #define CAUSEF_IV (_ULCAST_(1) << 23) | |
401 | #define CAUSEB_PCI 26 | |
402 | #define CAUSEF_PCI (_ULCAST_(1) << 26) | |
403 | #define CAUSEB_CE 28 | |
404 | #define CAUSEF_CE (_ULCAST_(3) << 28) | |
405 | #define CAUSEB_TI 30 | |
406 | #define CAUSEF_TI (_ULCAST_(1) << 30) | |
407 | #define CAUSEB_BD 31 | |
408 | #define CAUSEF_BD (_ULCAST_(1) << 31) | |
1da177e4 LT |
409 | |
410 | /* | |
411 | * Bits in the coprocessor 0 config register. | |
412 | */ | |
413 | /* Generic bits. */ | |
414 | #define CONF_CM_CACHABLE_NO_WA 0 | |
415 | #define CONF_CM_CACHABLE_WA 1 | |
416 | #define CONF_CM_UNCACHED 2 | |
417 | #define CONF_CM_CACHABLE_NONCOHERENT 3 | |
418 | #define CONF_CM_CACHABLE_CE 4 | |
419 | #define CONF_CM_CACHABLE_COW 5 | |
420 | #define CONF_CM_CACHABLE_CUW 6 | |
421 | #define CONF_CM_CACHABLE_ACCELERATED 7 | |
422 | #define CONF_CM_CMASK 7 | |
423 | #define CONF_BE (_ULCAST_(1) << 15) | |
424 | ||
425 | /* Bits common to various processors. */ | |
70342287 RB |
426 | #define CONF_CU (_ULCAST_(1) << 3) |
427 | #define CONF_DB (_ULCAST_(1) << 4) | |
428 | #define CONF_IB (_ULCAST_(1) << 5) | |
429 | #define CONF_DC (_ULCAST_(7) << 6) | |
430 | #define CONF_IC (_ULCAST_(7) << 9) | |
1da177e4 LT |
431 | #define CONF_EB (_ULCAST_(1) << 13) |
432 | #define CONF_EM (_ULCAST_(1) << 14) | |
433 | #define CONF_SM (_ULCAST_(1) << 16) | |
434 | #define CONF_SC (_ULCAST_(1) << 17) | |
435 | #define CONF_EW (_ULCAST_(3) << 18) | |
436 | #define CONF_EP (_ULCAST_(15)<< 24) | |
437 | #define CONF_EC (_ULCAST_(7) << 28) | |
438 | #define CONF_CM (_ULCAST_(1) << 31) | |
439 | ||
70342287 | 440 | /* Bits specific to the R4xx0. */ |
1da177e4 LT |
441 | #define R4K_CONF_SW (_ULCAST_(1) << 20) |
442 | #define R4K_CONF_SS (_ULCAST_(1) << 21) | |
e20368d5 | 443 | #define R4K_CONF_SB (_ULCAST_(3) << 22) |
1da177e4 | 444 | |
70342287 | 445 | /* Bits specific to the R5000. */ |
1da177e4 LT |
446 | #define R5K_CONF_SE (_ULCAST_(1) << 12) |
447 | #define R5K_CONF_SS (_ULCAST_(3) << 20) | |
448 | ||
70342287 RB |
449 | /* Bits specific to the RM7000. */ |
450 | #define RM7K_CONF_SE (_ULCAST_(1) << 3) | |
c6ad7b7d MR |
451 | #define RM7K_CONF_TE (_ULCAST_(1) << 12) |
452 | #define RM7K_CONF_CLK (_ULCAST_(1) << 16) | |
453 | #define RM7K_CONF_TC (_ULCAST_(1) << 17) | |
454 | #define RM7K_CONF_SI (_ULCAST_(3) << 20) | |
455 | #define RM7K_CONF_SC (_ULCAST_(1) << 31) | |
ba5187db | 456 | |
70342287 RB |
457 | /* Bits specific to the R10000. */ |
458 | #define R10K_CONF_DN (_ULCAST_(3) << 3) | |
459 | #define R10K_CONF_CT (_ULCAST_(1) << 5) | |
460 | #define R10K_CONF_PE (_ULCAST_(1) << 6) | |
461 | #define R10K_CONF_PM (_ULCAST_(3) << 7) | |
462 | #define R10K_CONF_EC (_ULCAST_(15)<< 9) | |
1da177e4 LT |
463 | #define R10K_CONF_SB (_ULCAST_(1) << 13) |
464 | #define R10K_CONF_SK (_ULCAST_(1) << 14) | |
465 | #define R10K_CONF_SS (_ULCAST_(7) << 16) | |
466 | #define R10K_CONF_SC (_ULCAST_(7) << 19) | |
467 | #define R10K_CONF_DC (_ULCAST_(7) << 26) | |
468 | #define R10K_CONF_IC (_ULCAST_(7) << 29) | |
469 | ||
70342287 | 470 | /* Bits specific to the VR41xx. */ |
1da177e4 | 471 | #define VR41_CONF_CS (_ULCAST_(1) << 12) |
2874fe55 | 472 | #define VR41_CONF_P4K (_ULCAST_(1) << 13) |
4e8ab361 | 473 | #define VR41_CONF_BP (_ULCAST_(1) << 16) |
1da177e4 LT |
474 | #define VR41_CONF_M16 (_ULCAST_(1) << 20) |
475 | #define VR41_CONF_AD (_ULCAST_(1) << 23) | |
476 | ||
70342287 | 477 | /* Bits specific to the R30xx. */ |
1da177e4 LT |
478 | #define R30XX_CONF_FDM (_ULCAST_(1) << 19) |
479 | #define R30XX_CONF_REV (_ULCAST_(1) << 22) | |
480 | #define R30XX_CONF_AC (_ULCAST_(1) << 23) | |
481 | #define R30XX_CONF_RF (_ULCAST_(1) << 24) | |
482 | #define R30XX_CONF_HALT (_ULCAST_(1) << 25) | |
483 | #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) | |
484 | #define R30XX_CONF_DBR (_ULCAST_(1) << 29) | |
485 | #define R30XX_CONF_SB (_ULCAST_(1) << 30) | |
486 | #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) | |
487 | ||
488 | /* Bits specific to the TX49. */ | |
489 | #define TX49_CONF_DC (_ULCAST_(1) << 16) | |
490 | #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ | |
491 | #define TX49_CONF_HALT (_ULCAST_(1) << 18) | |
492 | #define TX49_CONF_CWFON (_ULCAST_(1) << 27) | |
493 | ||
70342287 RB |
494 | /* Bits specific to the MIPS32/64 PRA. */ |
495 | #define MIPS_CONF_MT (_ULCAST_(7) << 7) | |
2f6f3136 JH |
496 | #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7) |
497 | #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7) | |
1da177e4 LT |
498 | #define MIPS_CONF_AR (_ULCAST_(7) << 10) |
499 | #define MIPS_CONF_AT (_ULCAST_(3) << 13) | |
500 | #define MIPS_CONF_M (_ULCAST_(1) << 31) | |
501 | ||
4194318c RB |
502 | /* |
503 | * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. | |
504 | */ | |
70342287 RB |
505 | #define MIPS_CONF1_FP (_ULCAST_(1) << 0) |
506 | #define MIPS_CONF1_EP (_ULCAST_(1) << 1) | |
507 | #define MIPS_CONF1_CA (_ULCAST_(1) << 2) | |
508 | #define MIPS_CONF1_WR (_ULCAST_(1) << 3) | |
509 | #define MIPS_CONF1_PC (_ULCAST_(1) << 4) | |
510 | #define MIPS_CONF1_MD (_ULCAST_(1) << 5) | |
511 | #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) | |
20a8d5d5 PB |
512 | #define MIPS_CONF1_DA_SHF 7 |
513 | #define MIPS_CONF1_DA_SZ 3 | |
70342287 | 514 | #define MIPS_CONF1_DA (_ULCAST_(7) << 7) |
20a8d5d5 PB |
515 | #define MIPS_CONF1_DL_SHF 10 |
516 | #define MIPS_CONF1_DL_SZ 3 | |
4194318c | 517 | #define MIPS_CONF1_DL (_ULCAST_(7) << 10) |
20a8d5d5 PB |
518 | #define MIPS_CONF1_DS_SHF 13 |
519 | #define MIPS_CONF1_DS_SZ 3 | |
4194318c | 520 | #define MIPS_CONF1_DS (_ULCAST_(7) << 13) |
20a8d5d5 PB |
521 | #define MIPS_CONF1_IA_SHF 16 |
522 | #define MIPS_CONF1_IA_SZ 3 | |
4194318c | 523 | #define MIPS_CONF1_IA (_ULCAST_(7) << 16) |
20a8d5d5 PB |
524 | #define MIPS_CONF1_IL_SHF 19 |
525 | #define MIPS_CONF1_IL_SZ 3 | |
4194318c | 526 | #define MIPS_CONF1_IL (_ULCAST_(7) << 19) |
20a8d5d5 PB |
527 | #define MIPS_CONF1_IS_SHF 22 |
528 | #define MIPS_CONF1_IS_SZ 3 | |
4194318c | 529 | #define MIPS_CONF1_IS (_ULCAST_(7) << 22) |
691038ba LY |
530 | #define MIPS_CONF1_TLBS_SHIFT (25) |
531 | #define MIPS_CONF1_TLBS_SIZE (6) | |
532 | #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) | |
4194318c | 533 | |
70342287 RB |
534 | #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) |
535 | #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) | |
536 | #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) | |
4194318c RB |
537 | #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) |
538 | #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) | |
539 | #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) | |
540 | #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) | |
541 | #define MIPS_CONF2_TU (_ULCAST_(7) << 28) | |
542 | ||
70342287 RB |
543 | #define MIPS_CONF3_TL (_ULCAST_(1) << 0) |
544 | #define MIPS_CONF3_SM (_ULCAST_(1) << 1) | |
545 | #define MIPS_CONF3_MT (_ULCAST_(1) << 2) | |
691038ba | 546 | #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) |
70342287 RB |
547 | #define MIPS_CONF3_SP (_ULCAST_(1) << 4) |
548 | #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) | |
549 | #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) | |
550 | #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) | |
691038ba LY |
551 | #define MIPS_CONF3_ITL (_ULCAST_(1) << 8) |
552 | #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) | |
e50c0a8f | 553 | #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) |
ee80f7c7 | 554 | #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) |
b2ab4f08 | 555 | #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) |
a3692020 | 556 | #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) |
f8fa4811 | 557 | #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) |
c6213c6c | 558 | #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) |
691038ba LY |
559 | #define MIPS_CONF3_MCU (_ULCAST_(1) << 17) |
560 | #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) | |
561 | #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) | |
1e7decdb | 562 | #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) |
691038ba LY |
563 | #define MIPS_CONF3_PW (_ULCAST_(1) << 24) |
564 | #define MIPS_CONF3_SC (_ULCAST_(1) << 25) | |
565 | #define MIPS_CONF3_BI (_ULCAST_(1) << 26) | |
566 | #define MIPS_CONF3_BP (_ULCAST_(1) << 27) | |
567 | #define MIPS_CONF3_MSA (_ULCAST_(1) << 28) | |
568 | #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) | |
569 | #define MIPS_CONF3_BPG (_ULCAST_(1) << 30) | |
570 | ||
571 | #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) | |
1b362e3e | 572 | #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) |
691038ba | 573 | #define MIPS_CONF4_FTLBSETS_SHIFT (0) |
691038ba LY |
574 | #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) |
575 | #define MIPS_CONF4_FTLBWAYS_SHIFT (4) | |
576 | #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) | |
577 | #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) | |
578 | /* bits 10:8 in FTLB-only configurations */ | |
579 | #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) | |
580 | /* bits 12:8 in VTLB-FTLB only configurations */ | |
581 | #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) | |
1b362e3e DD |
582 | #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) |
583 | #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) | |
691038ba LY |
584 | #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) |
585 | #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) | |
586 | #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) | |
587 | #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) | |
588 | #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) | |
589 | #define MIPS_CONF4_AE (_ULCAST_(1) << 28) | |
590 | #define MIPS_CONF4_IE (_ULCAST_(3) << 29) | |
591 | #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) | |
1b362e3e | 592 | |
2f9ee82c RB |
593 | #define MIPS_CONF5_NF (_ULCAST_(1) << 0) |
594 | #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) | |
e19d5dba | 595 | #define MIPS_CONF5_MRP (_ULCAST_(1) << 3) |
5aed9da1 | 596 | #define MIPS_CONF5_LLB (_ULCAST_(1) << 4) |
23d06e4f | 597 | #define MIPS_CONF5_MVH (_ULCAST_(1) << 5) |
5ff04a84 PB |
598 | #define MIPS_CONF5_FRE (_ULCAST_(1) << 8) |
599 | #define MIPS_CONF5_UFE (_ULCAST_(1) << 9) | |
2f9ee82c RB |
600 | #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) |
601 | #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) | |
602 | #define MIPS_CONF5_CV (_ULCAST_(1) << 29) | |
603 | #define MIPS_CONF5_K (_ULCAST_(1) << 30) | |
604 | ||
006a851b | 605 | #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) |
75b5b5e0 LY |
606 | /* proAptiv FTLB on/off bit */ |
607 | #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) | |
cf0a8aa0 MC |
608 | /* FTLB probability bits */ |
609 | #define MIPS_CONF6_FTLBP_SHIFT (16) | |
006a851b | 610 | |
4b3e975e RB |
611 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) |
612 | ||
9267a30d MSJ |
613 | #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) |
614 | ||
02dc6bfb MC |
615 | #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) |
616 | #define MIPS_CONF7_AR (_ULCAST_(1) << 16) | |
20a7f7e5 MC |
617 | /* FTLB probability bits for R6 */ |
618 | #define MIPS_CONF7_FTLBP_SHIFT (18) | |
02dc6bfb | 619 | |
e19d5dba PB |
620 | /* MAAR bit definitions */ |
621 | #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) | |
622 | #define MIPS_MAAR_ADDR_SHIFT 12 | |
623 | #define MIPS_MAAR_S (_ULCAST_(1) << 1) | |
624 | #define MIPS_MAAR_V (_ULCAST_(1) << 0) | |
625 | ||
4dd8ee5d PB |
626 | /* CMGCRBase bit definitions */ |
627 | #define MIPS_CMGCRB_BASE 11 | |
628 | #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) | |
629 | ||
4a0156fb SH |
630 | /* |
631 | * Bits in the MIPS32 Memory Segmentation registers. | |
632 | */ | |
633 | #define MIPS_SEGCFG_PA_SHIFT 9 | |
634 | #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) | |
635 | #define MIPS_SEGCFG_AM_SHIFT 4 | |
636 | #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) | |
637 | #define MIPS_SEGCFG_EU_SHIFT 3 | |
638 | #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) | |
639 | #define MIPS_SEGCFG_C_SHIFT 0 | |
640 | #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) | |
641 | ||
642 | #define MIPS_SEGCFG_UUSK _ULCAST_(7) | |
643 | #define MIPS_SEGCFG_USK _ULCAST_(5) | |
644 | #define MIPS_SEGCFG_MUSUK _ULCAST_(4) | |
645 | #define MIPS_SEGCFG_MUSK _ULCAST_(3) | |
646 | #define MIPS_SEGCFG_MSK _ULCAST_(2) | |
647 | #define MIPS_SEGCFG_MK _ULCAST_(1) | |
648 | #define MIPS_SEGCFG_UK _ULCAST_(0) | |
649 | ||
87d08bc9 MC |
650 | #define MIPS_PWFIELD_GDI_SHIFT 24 |
651 | #define MIPS_PWFIELD_GDI_MASK 0x3f000000 | |
652 | #define MIPS_PWFIELD_UDI_SHIFT 18 | |
653 | #define MIPS_PWFIELD_UDI_MASK 0x00fc0000 | |
654 | #define MIPS_PWFIELD_MDI_SHIFT 12 | |
655 | #define MIPS_PWFIELD_MDI_MASK 0x0003f000 | |
656 | #define MIPS_PWFIELD_PTI_SHIFT 6 | |
657 | #define MIPS_PWFIELD_PTI_MASK 0x00000fc0 | |
658 | #define MIPS_PWFIELD_PTEI_SHIFT 0 | |
659 | #define MIPS_PWFIELD_PTEI_MASK 0x0000003f | |
660 | ||
661 | #define MIPS_PWSIZE_GDW_SHIFT 24 | |
662 | #define MIPS_PWSIZE_GDW_MASK 0x3f000000 | |
663 | #define MIPS_PWSIZE_UDW_SHIFT 18 | |
664 | #define MIPS_PWSIZE_UDW_MASK 0x00fc0000 | |
665 | #define MIPS_PWSIZE_MDW_SHIFT 12 | |
666 | #define MIPS_PWSIZE_MDW_MASK 0x0003f000 | |
667 | #define MIPS_PWSIZE_PTW_SHIFT 6 | |
668 | #define MIPS_PWSIZE_PTW_MASK 0x00000fc0 | |
669 | #define MIPS_PWSIZE_PTEW_SHIFT 0 | |
670 | #define MIPS_PWSIZE_PTEW_MASK 0x0000003f | |
671 | ||
672 | #define MIPS_PWCTL_PWEN_SHIFT 31 | |
673 | #define MIPS_PWCTL_PWEN_MASK 0x80000000 | |
674 | #define MIPS_PWCTL_DPH_SHIFT 7 | |
675 | #define MIPS_PWCTL_DPH_MASK 0x00000080 | |
676 | #define MIPS_PWCTL_HUGEPG_SHIFT 6 | |
677 | #define MIPS_PWCTL_HUGEPG_MASK 0x00000060 | |
678 | #define MIPS_PWCTL_PSN_SHIFT 0 | |
679 | #define MIPS_PWCTL_PSN_MASK 0x0000003f | |
680 | ||
9b3274bd JH |
681 | /* CDMMBase register bit definitions */ |
682 | #define MIPS_CDMMBASE_SIZE_SHIFT 0 | |
683 | #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT) | |
684 | #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9) | |
685 | #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10) | |
686 | #define MIPS_CDMMBASE_ADDR_SHIFT 11 | |
687 | #define MIPS_CDMMBASE_ADDR_START 15 | |
688 | ||
e08384ca MR |
689 | /* |
690 | * Bitfields in the TX39 family CP0 Configuration Register 3 | |
691 | */ | |
692 | #define TX39_CONF_ICS_SHIFT 19 | |
693 | #define TX39_CONF_ICS_MASK 0x00380000 | |
694 | #define TX39_CONF_ICS_1KB 0x00000000 | |
695 | #define TX39_CONF_ICS_2KB 0x00080000 | |
696 | #define TX39_CONF_ICS_4KB 0x00100000 | |
697 | #define TX39_CONF_ICS_8KB 0x00180000 | |
698 | #define TX39_CONF_ICS_16KB 0x00200000 | |
699 | ||
700 | #define TX39_CONF_DCS_SHIFT 16 | |
701 | #define TX39_CONF_DCS_MASK 0x00070000 | |
702 | #define TX39_CONF_DCS_1KB 0x00000000 | |
703 | #define TX39_CONF_DCS_2KB 0x00010000 | |
704 | #define TX39_CONF_DCS_4KB 0x00020000 | |
705 | #define TX39_CONF_DCS_8KB 0x00030000 | |
706 | #define TX39_CONF_DCS_16KB 0x00040000 | |
707 | ||
708 | #define TX39_CONF_CWFON 0x00004000 | |
709 | #define TX39_CONF_WBON 0x00002000 | |
710 | #define TX39_CONF_RF_SHIFT 10 | |
711 | #define TX39_CONF_RF_MASK 0x00000c00 | |
712 | #define TX39_CONF_DOZE 0x00000200 | |
713 | #define TX39_CONF_HALT 0x00000100 | |
714 | #define TX39_CONF_LOCK 0x00000080 | |
715 | #define TX39_CONF_ICE 0x00000020 | |
716 | #define TX39_CONF_DCE 0x00000010 | |
717 | #define TX39_CONF_IRSIZE_SHIFT 2 | |
718 | #define TX39_CONF_IRSIZE_MASK 0x0000000c | |
719 | #define TX39_CONF_DRSIZE_SHIFT 0 | |
720 | #define TX39_CONF_DRSIZE_MASK 0x00000003 | |
721 | ||
8d5ded16 JK |
722 | /* |
723 | * Interesting Bits in the R10K CP0 Branch Diagnostic Register | |
724 | */ | |
725 | /* Disable Branch Target Address Cache */ | |
726 | #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27) | |
727 | /* Enable Branch Prediction Global History */ | |
728 | #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26) | |
729 | /* Disable Branch Return Cache */ | |
730 | #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22) | |
fda51906 MR |
731 | |
732 | /* | |
733 | * Coprocessor 1 (FPU) register names | |
734 | */ | |
c491cfa2 MR |
735 | #define CP1_REVISION $0 |
736 | #define CP1_UFR $1 | |
737 | #define CP1_UNFR $4 | |
738 | #define CP1_FCCR $25 | |
739 | #define CP1_FEXR $26 | |
740 | #define CP1_FENR $28 | |
741 | #define CP1_STATUS $31 | |
fda51906 MR |
742 | |
743 | ||
744 | /* | |
745 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. | |
746 | */ | |
747 | #define MIPS_FPIR_S (_ULCAST_(1) << 16) | |
748 | #define MIPS_FPIR_D (_ULCAST_(1) << 17) | |
749 | #define MIPS_FPIR_PS (_ULCAST_(1) << 18) | |
750 | #define MIPS_FPIR_3D (_ULCAST_(1) << 19) | |
751 | #define MIPS_FPIR_W (_ULCAST_(1) << 20) | |
752 | #define MIPS_FPIR_L (_ULCAST_(1) << 21) | |
753 | #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) | |
f1f3b7eb MR |
754 | #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) |
755 | #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) | |
fda51906 MR |
756 | #define MIPS_FPIR_FREP (_ULCAST_(1) << 29) |
757 | ||
c491cfa2 MR |
758 | /* |
759 | * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register. | |
760 | */ | |
761 | #define MIPS_FCCR_CONDX_S 0 | |
762 | #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) | |
763 | #define MIPS_FCCR_COND0_S 0 | |
764 | #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) | |
765 | #define MIPS_FCCR_COND1_S 1 | |
766 | #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) | |
767 | #define MIPS_FCCR_COND2_S 2 | |
768 | #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) | |
769 | #define MIPS_FCCR_COND3_S 3 | |
770 | #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) | |
771 | #define MIPS_FCCR_COND4_S 4 | |
772 | #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) | |
773 | #define MIPS_FCCR_COND5_S 5 | |
774 | #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) | |
775 | #define MIPS_FCCR_COND6_S 6 | |
776 | #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) | |
777 | #define MIPS_FCCR_COND7_S 7 | |
778 | #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) | |
779 | ||
780 | /* | |
781 | * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register. | |
782 | */ | |
783 | #define MIPS_FENR_FS_S 2 | |
784 | #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) | |
785 | ||
fda51906 MR |
786 | /* |
787 | * FPU Status Register Values | |
788 | */ | |
c491cfa2 MR |
789 | #define FPU_CSR_COND_S 23 /* $fcc0 */ |
790 | #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) | |
791 | ||
792 | #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ | |
793 | #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) | |
794 | ||
795 | #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ | |
796 | #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) | |
797 | #define FPU_CSR_COND1_S 25 /* $fcc1 */ | |
798 | #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) | |
799 | #define FPU_CSR_COND2_S 26 /* $fcc2 */ | |
800 | #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) | |
801 | #define FPU_CSR_COND3_S 27 /* $fcc3 */ | |
802 | #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) | |
803 | #define FPU_CSR_COND4_S 28 /* $fcc4 */ | |
804 | #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) | |
805 | #define FPU_CSR_COND5_S 29 /* $fcc5 */ | |
806 | #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) | |
807 | #define FPU_CSR_COND6_S 30 /* $fcc6 */ | |
808 | #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) | |
809 | #define FPU_CSR_COND7_S 31 /* $fcc7 */ | |
810 | #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) | |
fda51906 MR |
811 | |
812 | /* | |
f1f3b7eb | 813 | * Bits 22:20 of the FPU Status Register will be read as 0, |
fda51906 MR |
814 | * and should be written as zero. |
815 | */ | |
f1f3b7eb MR |
816 | #define FPU_CSR_RSVD (_ULCAST_(7) << 20) |
817 | ||
818 | #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) | |
819 | #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) | |
fda51906 MR |
820 | |
821 | /* | |
822 | * X the exception cause indicator | |
823 | * E the exception enable | |
824 | * S the sticky/flag bit | |
825 | */ | |
826 | #define FPU_CSR_ALL_X 0x0003f000 | |
827 | #define FPU_CSR_UNI_X 0x00020000 | |
828 | #define FPU_CSR_INV_X 0x00010000 | |
829 | #define FPU_CSR_DIV_X 0x00008000 | |
830 | #define FPU_CSR_OVF_X 0x00004000 | |
831 | #define FPU_CSR_UDF_X 0x00002000 | |
832 | #define FPU_CSR_INE_X 0x00001000 | |
833 | ||
834 | #define FPU_CSR_ALL_E 0x00000f80 | |
835 | #define FPU_CSR_INV_E 0x00000800 | |
836 | #define FPU_CSR_DIV_E 0x00000400 | |
837 | #define FPU_CSR_OVF_E 0x00000200 | |
838 | #define FPU_CSR_UDF_E 0x00000100 | |
839 | #define FPU_CSR_INE_E 0x00000080 | |
840 | ||
841 | #define FPU_CSR_ALL_S 0x0000007c | |
842 | #define FPU_CSR_INV_S 0x00000040 | |
843 | #define FPU_CSR_DIV_S 0x00000020 | |
844 | #define FPU_CSR_OVF_S 0x00000010 | |
845 | #define FPU_CSR_UDF_S 0x00000008 | |
846 | #define FPU_CSR_INE_S 0x00000004 | |
847 | ||
848 | /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ | |
849 | #define FPU_CSR_RM 0x00000003 | |
850 | #define FPU_CSR_RN 0x0 /* nearest */ | |
851 | #define FPU_CSR_RZ 0x1 /* towards zero */ | |
852 | #define FPU_CSR_RU 0x2 /* towards +Infinity */ | |
853 | #define FPU_CSR_RD 0x3 /* towards -Infinity */ | |
854 | ||
855 | ||
1da177e4 LT |
856 | #ifndef __ASSEMBLY__ |
857 | ||
bfd08baa | 858 | /* |
377cb1b6 | 859 | * Macros for handling the ISA mode bit for MIPS16 and microMIPS. |
bfd08baa | 860 | */ |
377cb1b6 RB |
861 | #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ |
862 | defined(CONFIG_SYS_SUPPORTS_MICROMIPS) | |
bfd08baa SH |
863 | #define get_isa16_mode(x) ((x) & 0x1) |
864 | #define msk_isa16_mode(x) ((x) & ~0x1) | |
865 | #define set_isa16_mode(x) do { (x) |= 0x1; } while(0) | |
377cb1b6 RB |
866 | #else |
867 | #define get_isa16_mode(x) 0 | |
868 | #define msk_isa16_mode(x) (x) | |
869 | #define set_isa16_mode(x) do { } while(0) | |
870 | #endif | |
bfd08baa SH |
871 | |
872 | /* | |
873 | * microMIPS instructions can be 16-bit or 32-bit in length. This | |
874 | * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. | |
875 | */ | |
876 | static inline int mm_insn_16bit(u16 insn) | |
877 | { | |
878 | u16 opcode = (insn >> 10) & 0x7; | |
879 | ||
880 | return (opcode >= 1 && opcode <= 3) ? 1 : 0; | |
881 | } | |
882 | ||
198bb4ce LY |
883 | /* |
884 | * TLB Invalidate Flush | |
885 | */ | |
886 | static inline void tlbinvf(void) | |
887 | { | |
888 | __asm__ __volatile__( | |
889 | ".set push\n\t" | |
890 | ".set noreorder\n\t" | |
891 | ".word 0x42000004\n\t" /* tlbinvf */ | |
892 | ".set pop"); | |
893 | } | |
894 | ||
895 | ||
1da177e4 | 896 | /* |
70342287 | 897 | * Functions to access the R10000 performance counters. These are basically |
1da177e4 LT |
898 | * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit |
899 | * performance counter number encoded into bits 1 ... 5 of the instruction. | |
900 | * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware | |
901 | * disassembler these will look like an access to sel 0 or 1. | |
902 | */ | |
903 | #define read_r10k_perf_cntr(counter) \ | |
904 | ({ \ | |
905 | unsigned int __res; \ | |
906 | __asm__ __volatile__( \ | |
907 | "mfpc\t%0, %1" \ | |
70342287 | 908 | : "=r" (__res) \ |
1da177e4 LT |
909 | : "i" (counter)); \ |
910 | \ | |
70342287 | 911 | __res; \ |
1da177e4 LT |
912 | }) |
913 | ||
70342287 | 914 | #define write_r10k_perf_cntr(counter,val) \ |
1da177e4 LT |
915 | do { \ |
916 | __asm__ __volatile__( \ | |
917 | "mtpc\t%0, %1" \ | |
918 | : \ | |
919 | : "r" (val), "i" (counter)); \ | |
920 | } while (0) | |
921 | ||
922 | #define read_r10k_perf_event(counter) \ | |
923 | ({ \ | |
924 | unsigned int __res; \ | |
925 | __asm__ __volatile__( \ | |
926 | "mfps\t%0, %1" \ | |
70342287 | 927 | : "=r" (__res) \ |
1da177e4 LT |
928 | : "i" (counter)); \ |
929 | \ | |
70342287 | 930 | __res; \ |
1da177e4 LT |
931 | }) |
932 | ||
70342287 | 933 | #define write_r10k_perf_cntl(counter,val) \ |
1da177e4 LT |
934 | do { \ |
935 | __asm__ __volatile__( \ | |
936 | "mtps\t%0, %1" \ | |
937 | : \ | |
938 | : "r" (val), "i" (counter)); \ | |
939 | } while (0) | |
940 | ||
941 | ||
942 | /* | |
943 | * Macros to access the system control coprocessor | |
944 | */ | |
945 | ||
946 | #define __read_32bit_c0_register(source, sel) \ | |
82eb8f73 | 947 | ({ unsigned int __res; \ |
1da177e4 LT |
948 | if (sel == 0) \ |
949 | __asm__ __volatile__( \ | |
950 | "mfc0\t%0, " #source "\n\t" \ | |
951 | : "=r" (__res)); \ | |
952 | else \ | |
953 | __asm__ __volatile__( \ | |
954 | ".set\tmips32\n\t" \ | |
955 | "mfc0\t%0, " #source ", " #sel "\n\t" \ | |
956 | ".set\tmips0\n\t" \ | |
957 | : "=r" (__res)); \ | |
958 | __res; \ | |
959 | }) | |
960 | ||
961 | #define __read_64bit_c0_register(source, sel) \ | |
962 | ({ unsigned long long __res; \ | |
963 | if (sizeof(unsigned long) == 4) \ | |
964 | __res = __read_64bit_c0_split(source, sel); \ | |
965 | else if (sel == 0) \ | |
966 | __asm__ __volatile__( \ | |
967 | ".set\tmips3\n\t" \ | |
968 | "dmfc0\t%0, " #source "\n\t" \ | |
969 | ".set\tmips0" \ | |
970 | : "=r" (__res)); \ | |
971 | else \ | |
972 | __asm__ __volatile__( \ | |
973 | ".set\tmips64\n\t" \ | |
974 | "dmfc0\t%0, " #source ", " #sel "\n\t" \ | |
975 | ".set\tmips0" \ | |
976 | : "=r" (__res)); \ | |
977 | __res; \ | |
978 | }) | |
979 | ||
980 | #define __write_32bit_c0_register(register, sel, value) \ | |
981 | do { \ | |
982 | if (sel == 0) \ | |
983 | __asm__ __volatile__( \ | |
984 | "mtc0\t%z0, " #register "\n\t" \ | |
0952e290 | 985 | : : "Jr" ((unsigned int)(value))); \ |
1da177e4 LT |
986 | else \ |
987 | __asm__ __volatile__( \ | |
988 | ".set\tmips32\n\t" \ | |
989 | "mtc0\t%z0, " #register ", " #sel "\n\t" \ | |
990 | ".set\tmips0" \ | |
0952e290 | 991 | : : "Jr" ((unsigned int)(value))); \ |
1da177e4 LT |
992 | } while (0) |
993 | ||
994 | #define __write_64bit_c0_register(register, sel, value) \ | |
995 | do { \ | |
996 | if (sizeof(unsigned long) == 4) \ | |
997 | __write_64bit_c0_split(register, sel, value); \ | |
998 | else if (sel == 0) \ | |
999 | __asm__ __volatile__( \ | |
1000 | ".set\tmips3\n\t" \ | |
1001 | "dmtc0\t%z0, " #register "\n\t" \ | |
1002 | ".set\tmips0" \ | |
1003 | : : "Jr" (value)); \ | |
1004 | else \ | |
1005 | __asm__ __volatile__( \ | |
1006 | ".set\tmips64\n\t" \ | |
1007 | "dmtc0\t%z0, " #register ", " #sel "\n\t" \ | |
1008 | ".set\tmips0" \ | |
1009 | : : "Jr" (value)); \ | |
1010 | } while (0) | |
1011 | ||
1012 | #define __read_ulong_c0_register(reg, sel) \ | |
1013 | ((sizeof(unsigned long) == 4) ? \ | |
1014 | (unsigned long) __read_32bit_c0_register(reg, sel) : \ | |
1015 | (unsigned long) __read_64bit_c0_register(reg, sel)) | |
1016 | ||
1017 | #define __write_ulong_c0_register(reg, sel, val) \ | |
1018 | do { \ | |
1019 | if (sizeof(unsigned long) == 4) \ | |
1020 | __write_32bit_c0_register(reg, sel, val); \ | |
1021 | else \ | |
1022 | __write_64bit_c0_register(reg, sel, val); \ | |
1023 | } while (0) | |
1024 | ||
1025 | /* | |
1026 | * On RM7000/RM9000 these are uses to access cop0 set 1 registers | |
1027 | */ | |
1028 | #define __read_32bit_c0_ctrl_register(source) \ | |
82eb8f73 | 1029 | ({ unsigned int __res; \ |
1da177e4 LT |
1030 | __asm__ __volatile__( \ |
1031 | "cfc0\t%0, " #source "\n\t" \ | |
1032 | : "=r" (__res)); \ | |
1033 | __res; \ | |
1034 | }) | |
1035 | ||
1036 | #define __write_32bit_c0_ctrl_register(register, value) \ | |
1037 | do { \ | |
1038 | __asm__ __volatile__( \ | |
1039 | "ctc0\t%z0, " #register "\n\t" \ | |
0952e290 | 1040 | : : "Jr" ((unsigned int)(value))); \ |
1da177e4 LT |
1041 | } while (0) |
1042 | ||
1043 | /* | |
1044 | * These versions are only needed for systems with more than 38 bits of | |
1045 | * physical address space running the 32-bit kernel. That's none atm :-) | |
1046 | */ | |
1047 | #define __read_64bit_c0_split(source, sel) \ | |
1048 | ({ \ | |
87d43dd4 AN |
1049 | unsigned long long __val; \ |
1050 | unsigned long __flags; \ | |
1da177e4 | 1051 | \ |
87d43dd4 | 1052 | local_irq_save(__flags); \ |
1da177e4 LT |
1053 | if (sel == 0) \ |
1054 | __asm__ __volatile__( \ | |
1055 | ".set\tmips64\n\t" \ | |
1056 | "dmfc0\t%M0, " #source "\n\t" \ | |
1057 | "dsll\t%L0, %M0, 32\n\t" \ | |
0b543526 RB |
1058 | "dsra\t%M0, %M0, 32\n\t" \ |
1059 | "dsra\t%L0, %L0, 32\n\t" \ | |
1da177e4 | 1060 | ".set\tmips0" \ |
87d43dd4 | 1061 | : "=r" (__val)); \ |
1da177e4 LT |
1062 | else \ |
1063 | __asm__ __volatile__( \ | |
1064 | ".set\tmips64\n\t" \ | |
1065 | "dmfc0\t%M0, " #source ", " #sel "\n\t" \ | |
1066 | "dsll\t%L0, %M0, 32\n\t" \ | |
0b543526 RB |
1067 | "dsra\t%M0, %M0, 32\n\t" \ |
1068 | "dsra\t%L0, %L0, 32\n\t" \ | |
1da177e4 | 1069 | ".set\tmips0" \ |
87d43dd4 AN |
1070 | : "=r" (__val)); \ |
1071 | local_irq_restore(__flags); \ | |
1da177e4 | 1072 | \ |
87d43dd4 | 1073 | __val; \ |
1da177e4 LT |
1074 | }) |
1075 | ||
1076 | #define __write_64bit_c0_split(source, sel, val) \ | |
1077 | do { \ | |
87d43dd4 | 1078 | unsigned long __flags; \ |
1da177e4 | 1079 | \ |
87d43dd4 | 1080 | local_irq_save(__flags); \ |
1da177e4 LT |
1081 | if (sel == 0) \ |
1082 | __asm__ __volatile__( \ | |
1083 | ".set\tmips64\n\t" \ | |
1084 | "dsll\t%L0, %L0, 32\n\t" \ | |
1085 | "dsrl\t%L0, %L0, 32\n\t" \ | |
1086 | "dsll\t%M0, %M0, 32\n\t" \ | |
1087 | "or\t%L0, %L0, %M0\n\t" \ | |
1088 | "dmtc0\t%L0, " #source "\n\t" \ | |
1089 | ".set\tmips0" \ | |
1090 | : : "r" (val)); \ | |
1091 | else \ | |
1092 | __asm__ __volatile__( \ | |
1093 | ".set\tmips64\n\t" \ | |
1094 | "dsll\t%L0, %L0, 32\n\t" \ | |
1095 | "dsrl\t%L0, %L0, 32\n\t" \ | |
1096 | "dsll\t%M0, %M0, 32\n\t" \ | |
1097 | "or\t%L0, %L0, %M0\n\t" \ | |
1098 | "dmtc0\t%L0, " #source ", " #sel "\n\t" \ | |
1099 | ".set\tmips0" \ | |
1100 | : : "r" (val)); \ | |
87d43dd4 | 1101 | local_irq_restore(__flags); \ |
1da177e4 LT |
1102 | } while (0) |
1103 | ||
23d06e4f SH |
1104 | #define __readx_32bit_c0_register(source) \ |
1105 | ({ \ | |
1106 | unsigned int __res; \ | |
1107 | \ | |
1108 | __asm__ __volatile__( \ | |
1109 | " .set push \n" \ | |
1110 | " .set noat \n" \ | |
1111 | " .set mips32r2 \n" \ | |
1112 | " .insn \n" \ | |
1113 | " # mfhc0 $1, %1 \n" \ | |
1114 | " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ | |
1115 | " move %0, $1 \n" \ | |
1116 | " .set pop \n" \ | |
1117 | : "=r" (__res) \ | |
1118 | : "i" (source)); \ | |
1119 | __res; \ | |
1120 | }) | |
1121 | ||
1122 | #define __writex_32bit_c0_register(register, value) \ | |
1123 | do { \ | |
1124 | __asm__ __volatile__( \ | |
1125 | " .set push \n" \ | |
1126 | " .set noat \n" \ | |
1127 | " .set mips32r2 \n" \ | |
1128 | " move $1, %0 \n" \ | |
1129 | " # mthc0 $1, %1 \n" \ | |
1130 | " .insn \n" \ | |
1131 | " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ | |
1132 | " .set pop \n" \ | |
1133 | : \ | |
1134 | : "r" (value), "i" (register)); \ | |
1135 | } while (0) | |
1136 | ||
1da177e4 LT |
1137 | #define read_c0_index() __read_32bit_c0_register($0, 0) |
1138 | #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) | |
1139 | ||
272bace7 RB |
1140 | #define read_c0_random() __read_32bit_c0_register($1, 0) |
1141 | #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) | |
1142 | ||
1da177e4 LT |
1143 | #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) |
1144 | #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) | |
1145 | ||
23d06e4f SH |
1146 | #define readx_c0_entrylo0() __readx_32bit_c0_register(2) |
1147 | #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val) | |
1148 | ||
1da177e4 LT |
1149 | #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) |
1150 | #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) | |
1151 | ||
23d06e4f SH |
1152 | #define readx_c0_entrylo1() __readx_32bit_c0_register(3) |
1153 | #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val) | |
1154 | ||
1da177e4 LT |
1155 | #define read_c0_conf() __read_32bit_c0_register($3, 0) |
1156 | #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) | |
1157 | ||
1158 | #define read_c0_context() __read_ulong_c0_register($4, 0) | |
1159 | #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) | |
1160 | ||
a3692020 | 1161 | #define read_c0_userlocal() __read_ulong_c0_register($4, 2) |
70342287 | 1162 | #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) |
a3692020 | 1163 | |
1da177e4 LT |
1164 | #define read_c0_pagemask() __read_32bit_c0_register($5, 0) |
1165 | #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) | |
1166 | ||
9fe2e9d6 | 1167 | #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) |
70342287 | 1168 | #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) |
9fe2e9d6 | 1169 | |
1da177e4 LT |
1170 | #define read_c0_wired() __read_32bit_c0_register($6, 0) |
1171 | #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) | |
1172 | ||
1173 | #define read_c0_info() __read_32bit_c0_register($7, 0) | |
1174 | ||
70342287 | 1175 | #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ |
1da177e4 LT |
1176 | #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) |
1177 | ||
15c4f67a RB |
1178 | #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) |
1179 | #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) | |
1180 | ||
1da177e4 LT |
1181 | #define read_c0_count() __read_32bit_c0_register($9, 0) |
1182 | #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) | |
1183 | ||
bdf21b18 PP |
1184 | #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ |
1185 | #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) | |
1186 | ||
1187 | #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ | |
1188 | #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) | |
1189 | ||
1da177e4 LT |
1190 | #define read_c0_entryhi() __read_ulong_c0_register($10, 0) |
1191 | #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) | |
1192 | ||
1193 | #define read_c0_compare() __read_32bit_c0_register($11, 0) | |
1194 | #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) | |
1195 | ||
bdf21b18 PP |
1196 | #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ |
1197 | #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) | |
1198 | ||
1199 | #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ | |
1200 | #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) | |
1201 | ||
1da177e4 | 1202 | #define read_c0_status() __read_32bit_c0_register($12, 0) |
b633648c | 1203 | |
1da177e4 LT |
1204 | #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) |
1205 | ||
1206 | #define read_c0_cause() __read_32bit_c0_register($13, 0) | |
1207 | #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) | |
1208 | ||
1209 | #define read_c0_epc() __read_ulong_c0_register($14, 0) | |
1210 | #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) | |
1211 | ||
1212 | #define read_c0_prid() __read_32bit_c0_register($15, 0) | |
1213 | ||
4dd8ee5d PB |
1214 | #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) |
1215 | ||
1da177e4 LT |
1216 | #define read_c0_config() __read_32bit_c0_register($16, 0) |
1217 | #define read_c0_config1() __read_32bit_c0_register($16, 1) | |
1218 | #define read_c0_config2() __read_32bit_c0_register($16, 2) | |
1219 | #define read_c0_config3() __read_32bit_c0_register($16, 3) | |
0efe2761 RB |
1220 | #define read_c0_config4() __read_32bit_c0_register($16, 4) |
1221 | #define read_c0_config5() __read_32bit_c0_register($16, 5) | |
1222 | #define read_c0_config6() __read_32bit_c0_register($16, 6) | |
1223 | #define read_c0_config7() __read_32bit_c0_register($16, 7) | |
1da177e4 LT |
1224 | #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) |
1225 | #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) | |
1226 | #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) | |
1227 | #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) | |
0efe2761 RB |
1228 | #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) |
1229 | #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) | |
1230 | #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) | |
1231 | #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) | |
1da177e4 | 1232 | |
b55b9e27 MC |
1233 | #define read_c0_lladdr() __read_ulong_c0_register($17, 0) |
1234 | #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) | |
e19d5dba PB |
1235 | #define read_c0_maar() __read_ulong_c0_register($17, 1) |
1236 | #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) | |
1237 | #define read_c0_maari() __read_32bit_c0_register($17, 2) | |
1238 | #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val) | |
1239 | ||
1da177e4 | 1240 | /* |
25985edc | 1241 | * The WatchLo register. There may be up to 8 of them. |
1da177e4 LT |
1242 | */ |
1243 | #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) | |
1244 | #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) | |
1245 | #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) | |
1246 | #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) | |
1247 | #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) | |
1248 | #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) | |
1249 | #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) | |
1250 | #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) | |
1251 | #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) | |
1252 | #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) | |
1253 | #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) | |
1254 | #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) | |
1255 | #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) | |
1256 | #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) | |
1257 | #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) | |
1258 | #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) | |
1259 | ||
1260 | /* | |
25985edc | 1261 | * The WatchHi register. There may be up to 8 of them. |
1da177e4 LT |
1262 | */ |
1263 | #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) | |
1264 | #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) | |
1265 | #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) | |
1266 | #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) | |
1267 | #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) | |
1268 | #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) | |
1269 | #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) | |
1270 | #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) | |
1271 | ||
1272 | #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) | |
1273 | #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) | |
1274 | #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) | |
1275 | #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) | |
1276 | #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) | |
1277 | #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) | |
1278 | #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) | |
1279 | #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) | |
1280 | ||
1281 | #define read_c0_xcontext() __read_ulong_c0_register($20, 0) | |
1282 | #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) | |
1283 | ||
1284 | #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) | |
1285 | #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) | |
1286 | ||
1287 | #define read_c0_framemask() __read_32bit_c0_register($21, 0) | |
70342287 | 1288 | #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) |
1da177e4 | 1289 | |
1da177e4 LT |
1290 | #define read_c0_diag() __read_32bit_c0_register($22, 0) |
1291 | #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) | |
1292 | ||
8d5ded16 JK |
1293 | /* R10K CP0 Branch Diagnostic register is 64bits wide */ |
1294 | #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0) | |
1295 | #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val) | |
1296 | ||
1da177e4 LT |
1297 | #define read_c0_diag1() __read_32bit_c0_register($22, 1) |
1298 | #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) | |
1299 | ||
1300 | #define read_c0_diag2() __read_32bit_c0_register($22, 2) | |
1301 | #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) | |
1302 | ||
1303 | #define read_c0_diag3() __read_32bit_c0_register($22, 3) | |
1304 | #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) | |
1305 | ||
1306 | #define read_c0_diag4() __read_32bit_c0_register($22, 4) | |
1307 | #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) | |
1308 | ||
1309 | #define read_c0_diag5() __read_32bit_c0_register($22, 5) | |
1310 | #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) | |
1311 | ||
1312 | #define read_c0_debug() __read_32bit_c0_register($23, 0) | |
1313 | #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) | |
1314 | ||
1315 | #define read_c0_depc() __read_ulong_c0_register($24, 0) | |
1316 | #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) | |
1317 | ||
1318 | /* | |
1319 | * MIPS32 / MIPS64 performance counters | |
1320 | */ | |
1321 | #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) | |
70342287 | 1322 | #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) |
1da177e4 | 1323 | #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) |
70342287 | 1324 | #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) |
4d36f59d DD |
1325 | #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) |
1326 | #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) | |
1da177e4 | 1327 | #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) |
70342287 | 1328 | #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) |
1da177e4 | 1329 | #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) |
70342287 | 1330 | #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) |
4d36f59d DD |
1331 | #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) |
1332 | #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) | |
1da177e4 | 1333 | #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) |
70342287 | 1334 | #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) |
1da177e4 | 1335 | #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) |
70342287 | 1336 | #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) |
4d36f59d DD |
1337 | #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) |
1338 | #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) | |
1da177e4 | 1339 | #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) |
70342287 | 1340 | #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) |
1da177e4 | 1341 | #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) |
70342287 | 1342 | #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) |
4d36f59d DD |
1343 | #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) |
1344 | #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) | |
1da177e4 | 1345 | |
1da177e4 LT |
1346 | #define read_c0_ecc() __read_32bit_c0_register($26, 0) |
1347 | #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) | |
1348 | ||
1349 | #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) | |
70342287 | 1350 | #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) |
1da177e4 LT |
1351 | |
1352 | #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) | |
1353 | ||
1354 | #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) | |
70342287 | 1355 | #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) |
1da177e4 LT |
1356 | |
1357 | #define read_c0_taglo() __read_32bit_c0_register($28, 0) | |
1358 | #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) | |
1359 | ||
41c594ab RB |
1360 | #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) |
1361 | #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) | |
1362 | ||
af231172 KC |
1363 | #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) |
1364 | #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) | |
1365 | ||
1366 | #define read_c0_staglo() __read_32bit_c0_register($28, 4) | |
1367 | #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) | |
1368 | ||
1da177e4 LT |
1369 | #define read_c0_taghi() __read_32bit_c0_register($29, 0) |
1370 | #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) | |
1371 | ||
1372 | #define read_c0_errorepc() __read_ulong_c0_register($30, 0) | |
1373 | #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) | |
1374 | ||
7a0fc58c | 1375 | /* MIPSR2 */ |
21a151d8 | 1376 | #define read_c0_hwrena() __read_32bit_c0_register($7, 0) |
7a0fc58c RB |
1377 | #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) |
1378 | ||
1379 | #define read_c0_intctl() __read_32bit_c0_register($12, 1) | |
1380 | #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) | |
1381 | ||
1382 | #define read_c0_srsctl() __read_32bit_c0_register($12, 2) | |
1383 | #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) | |
1384 | ||
1385 | #define read_c0_srsmap() __read_32bit_c0_register($12, 3) | |
1386 | #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) | |
1387 | ||
21a151d8 | 1388 | #define read_c0_ebase() __read_32bit_c0_register($15, 1) |
7a0fc58c RB |
1389 | #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) |
1390 | ||
9b3274bd JH |
1391 | #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2) |
1392 | #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val) | |
1393 | ||
4a0156fb SH |
1394 | /* MIPSR3 */ |
1395 | #define read_c0_segctl0() __read_32bit_c0_register($5, 2) | |
1396 | #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) | |
1397 | ||
1398 | #define read_c0_segctl1() __read_32bit_c0_register($5, 3) | |
1399 | #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) | |
1400 | ||
1401 | #define read_c0_segctl2() __read_32bit_c0_register($5, 4) | |
1402 | #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) | |
ed918c2d | 1403 | |
87d08bc9 MC |
1404 | /* Hardware Page Table Walker */ |
1405 | #define read_c0_pwbase() __read_ulong_c0_register($5, 5) | |
1406 | #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val) | |
1407 | ||
1408 | #define read_c0_pwfield() __read_ulong_c0_register($5, 6) | |
1409 | #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val) | |
1410 | ||
1411 | #define read_c0_pwsize() __read_ulong_c0_register($5, 7) | |
1412 | #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val) | |
1413 | ||
1414 | #define read_c0_pwctl() __read_32bit_c0_register($6, 6) | |
1415 | #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) | |
1416 | ||
ed918c2d DD |
1417 | /* Cavium OCTEON (cnMIPS) */ |
1418 | #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) | |
1419 | #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) | |
1420 | ||
1421 | #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) | |
1422 | #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) | |
1423 | ||
1424 | #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) | |
70342287 | 1425 | #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) |
ed918c2d | 1426 | /* |
70342287 | 1427 | * The cacheerr registers are not standardized. On OCTEON, they are |
ed918c2d DD |
1428 | * 64 bits wide. |
1429 | */ | |
1430 | #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) | |
1431 | #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) | |
1432 | ||
1433 | #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) | |
1434 | #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) | |
1435 | ||
af231172 KC |
1436 | /* BMIPS3300 */ |
1437 | #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) | |
1438 | #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) | |
1439 | ||
1440 | #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) | |
1441 | #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) | |
1442 | ||
1443 | #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) | |
1444 | #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) | |
1445 | ||
020232f1 | 1446 | /* BMIPS43xx */ |
af231172 KC |
1447 | #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) |
1448 | #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) | |
1449 | ||
1450 | #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) | |
1451 | #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) | |
1452 | ||
1453 | #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) | |
1454 | #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) | |
1455 | ||
1456 | #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) | |
1457 | #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) | |
1458 | ||
1459 | #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) | |
1460 | #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) | |
1461 | ||
1462 | /* BMIPS5000 */ | |
1463 | #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) | |
1464 | #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) | |
1465 | ||
1466 | #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) | |
1467 | #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) | |
1468 | ||
1469 | #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) | |
1470 | #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) | |
1471 | ||
1472 | #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) | |
1473 | #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) | |
1474 | ||
1475 | #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) | |
1476 | #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) | |
1477 | ||
1478 | #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) | |
1479 | #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) | |
1480 | ||
1da177e4 LT |
1481 | /* |
1482 | * Macros to access the floating point coprocessor control registers | |
1483 | */ | |
842dfc11 | 1484 | #define _read_32bit_cp1_register(source, gas_hardfloat) \ |
b9688310 | 1485 | ({ \ |
c46a2f01 | 1486 | unsigned int __res; \ |
b9688310 SH |
1487 | \ |
1488 | __asm__ __volatile__( \ | |
1489 | " .set push \n" \ | |
1490 | " .set reorder \n" \ | |
1491 | " # gas fails to assemble cfc1 for some archs, \n" \ | |
1492 | " # like Octeon. \n" \ | |
1493 | " .set mips1 \n" \ | |
842dfc11 | 1494 | " "STR(gas_hardfloat)" \n" \ |
b9688310 SH |
1495 | " cfc1 %0,"STR(source)" \n" \ |
1496 | " .set pop \n" \ | |
1497 | : "=r" (__res)); \ | |
1498 | __res; \ | |
1499 | }) | |
1da177e4 | 1500 | |
5e32033e JH |
1501 | #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \ |
1502 | do { \ | |
1503 | __asm__ __volatile__( \ | |
1504 | " .set push \n" \ | |
1505 | " .set reorder \n" \ | |
1506 | " "STR(gas_hardfloat)" \n" \ | |
1507 | " ctc1 %0,"STR(dest)" \n" \ | |
1508 | " .set pop \n" \ | |
1509 | : : "r" (val)); \ | |
1510 | } while (0) | |
1511 | ||
842dfc11 ML |
1512 | #ifdef GAS_HAS_SET_HARDFLOAT |
1513 | #define read_32bit_cp1_register(source) \ | |
1514 | _read_32bit_cp1_register(source, .set hardfloat) | |
5e32033e JH |
1515 | #define write_32bit_cp1_register(dest, val) \ |
1516 | _write_32bit_cp1_register(dest, val, .set hardfloat) | |
842dfc11 ML |
1517 | #else |
1518 | #define read_32bit_cp1_register(source) \ | |
1519 | _read_32bit_cp1_register(source, ) | |
5e32033e JH |
1520 | #define write_32bit_cp1_register(dest, val) \ |
1521 | _write_32bit_cp1_register(dest, val, ) | |
842dfc11 ML |
1522 | #endif |
1523 | ||
32a7ede6 | 1524 | #ifdef HAVE_AS_DSP |
e50c0a8f RB |
1525 | #define rddsp(mask) \ |
1526 | ({ \ | |
32a7ede6 | 1527 | unsigned int __dspctl; \ |
e50c0a8f RB |
1528 | \ |
1529 | __asm__ __volatile__( \ | |
63c2b681 FF |
1530 | " .set push \n" \ |
1531 | " .set dsp \n" \ | |
32a7ede6 | 1532 | " rddsp %0, %x1 \n" \ |
63c2b681 | 1533 | " .set pop \n" \ |
32a7ede6 | 1534 | : "=r" (__dspctl) \ |
e50c0a8f | 1535 | : "i" (mask)); \ |
32a7ede6 | 1536 | __dspctl; \ |
e50c0a8f RB |
1537 | }) |
1538 | ||
1539 | #define wrdsp(val, mask) \ | |
1540 | do { \ | |
e50c0a8f | 1541 | __asm__ __volatile__( \ |
63c2b681 FF |
1542 | " .set push \n" \ |
1543 | " .set dsp \n" \ | |
32a7ede6 | 1544 | " wrdsp %0, %x1 \n" \ |
63c2b681 | 1545 | " .set pop \n" \ |
70342287 | 1546 | : \ |
e50c0a8f | 1547 | : "r" (val), "i" (mask)); \ |
e50c0a8f RB |
1548 | } while (0) |
1549 | ||
63c2b681 FF |
1550 | #define mflo0() \ |
1551 | ({ \ | |
1552 | long mflo0; \ | |
1553 | __asm__( \ | |
1554 | " .set push \n" \ | |
1555 | " .set dsp \n" \ | |
1556 | " mflo %0, $ac0 \n" \ | |
1557 | " .set pop \n" \ | |
1558 | : "=r" (mflo0)); \ | |
1559 | mflo0; \ | |
1560 | }) | |
1561 | ||
1562 | #define mflo1() \ | |
1563 | ({ \ | |
1564 | long mflo1; \ | |
1565 | __asm__( \ | |
1566 | " .set push \n" \ | |
1567 | " .set dsp \n" \ | |
1568 | " mflo %0, $ac1 \n" \ | |
1569 | " .set pop \n" \ | |
1570 | : "=r" (mflo1)); \ | |
1571 | mflo1; \ | |
1572 | }) | |
1573 | ||
1574 | #define mflo2() \ | |
1575 | ({ \ | |
1576 | long mflo2; \ | |
1577 | __asm__( \ | |
1578 | " .set push \n" \ | |
1579 | " .set dsp \n" \ | |
1580 | " mflo %0, $ac2 \n" \ | |
1581 | " .set pop \n" \ | |
1582 | : "=r" (mflo2)); \ | |
1583 | mflo2; \ | |
1584 | }) | |
1585 | ||
1586 | #define mflo3() \ | |
1587 | ({ \ | |
1588 | long mflo3; \ | |
1589 | __asm__( \ | |
1590 | " .set push \n" \ | |
1591 | " .set dsp \n" \ | |
1592 | " mflo %0, $ac3 \n" \ | |
1593 | " .set pop \n" \ | |
1594 | : "=r" (mflo3)); \ | |
1595 | mflo3; \ | |
1596 | }) | |
1597 | ||
1598 | #define mfhi0() \ | |
1599 | ({ \ | |
1600 | long mfhi0; \ | |
1601 | __asm__( \ | |
1602 | " .set push \n" \ | |
1603 | " .set dsp \n" \ | |
1604 | " mfhi %0, $ac0 \n" \ | |
1605 | " .set pop \n" \ | |
1606 | : "=r" (mfhi0)); \ | |
1607 | mfhi0; \ | |
1608 | }) | |
1609 | ||
1610 | #define mfhi1() \ | |
1611 | ({ \ | |
1612 | long mfhi1; \ | |
1613 | __asm__( \ | |
1614 | " .set push \n" \ | |
1615 | " .set dsp \n" \ | |
1616 | " mfhi %0, $ac1 \n" \ | |
1617 | " .set pop \n" \ | |
1618 | : "=r" (mfhi1)); \ | |
1619 | mfhi1; \ | |
1620 | }) | |
1621 | ||
1622 | #define mfhi2() \ | |
1623 | ({ \ | |
1624 | long mfhi2; \ | |
1625 | __asm__( \ | |
1626 | " .set push \n" \ | |
1627 | " .set dsp \n" \ | |
1628 | " mfhi %0, $ac2 \n" \ | |
1629 | " .set pop \n" \ | |
1630 | : "=r" (mfhi2)); \ | |
1631 | mfhi2; \ | |
1632 | }) | |
1633 | ||
1634 | #define mfhi3() \ | |
1635 | ({ \ | |
1636 | long mfhi3; \ | |
1637 | __asm__( \ | |
1638 | " .set push \n" \ | |
1639 | " .set dsp \n" \ | |
1640 | " mfhi %0, $ac3 \n" \ | |
1641 | " .set pop \n" \ | |
1642 | : "=r" (mfhi3)); \ | |
1643 | mfhi3; \ | |
1644 | }) | |
1645 | ||
1646 | ||
1647 | #define mtlo0(x) \ | |
1648 | ({ \ | |
1649 | __asm__( \ | |
1650 | " .set push \n" \ | |
1651 | " .set dsp \n" \ | |
1652 | " mtlo %0, $ac0 \n" \ | |
1653 | " .set pop \n" \ | |
1654 | : \ | |
1655 | : "r" (x)); \ | |
1656 | }) | |
1657 | ||
1658 | #define mtlo1(x) \ | |
1659 | ({ \ | |
1660 | __asm__( \ | |
1661 | " .set push \n" \ | |
1662 | " .set dsp \n" \ | |
1663 | " mtlo %0, $ac1 \n" \ | |
1664 | " .set pop \n" \ | |
1665 | : \ | |
1666 | : "r" (x)); \ | |
1667 | }) | |
1668 | ||
1669 | #define mtlo2(x) \ | |
1670 | ({ \ | |
1671 | __asm__( \ | |
1672 | " .set push \n" \ | |
1673 | " .set dsp \n" \ | |
1674 | " mtlo %0, $ac2 \n" \ | |
1675 | " .set pop \n" \ | |
1676 | : \ | |
1677 | : "r" (x)); \ | |
1678 | }) | |
1679 | ||
1680 | #define mtlo3(x) \ | |
1681 | ({ \ | |
1682 | __asm__( \ | |
1683 | " .set push \n" \ | |
1684 | " .set dsp \n" \ | |
1685 | " mtlo %0, $ac3 \n" \ | |
1686 | " .set pop \n" \ | |
1687 | : \ | |
1688 | : "r" (x)); \ | |
1689 | }) | |
1690 | ||
1691 | #define mthi0(x) \ | |
1692 | ({ \ | |
1693 | __asm__( \ | |
1694 | " .set push \n" \ | |
1695 | " .set dsp \n" \ | |
1696 | " mthi %0, $ac0 \n" \ | |
1697 | " .set pop \n" \ | |
1698 | : \ | |
1699 | : "r" (x)); \ | |
1700 | }) | |
1701 | ||
1702 | #define mthi1(x) \ | |
1703 | ({ \ | |
1704 | __asm__( \ | |
1705 | " .set push \n" \ | |
1706 | " .set dsp \n" \ | |
1707 | " mthi %0, $ac1 \n" \ | |
1708 | " .set pop \n" \ | |
1709 | : \ | |
1710 | : "r" (x)); \ | |
1711 | }) | |
1712 | ||
1713 | #define mthi2(x) \ | |
1714 | ({ \ | |
1715 | __asm__( \ | |
1716 | " .set push \n" \ | |
1717 | " .set dsp \n" \ | |
1718 | " mthi %0, $ac2 \n" \ | |
1719 | " .set pop \n" \ | |
1720 | : \ | |
1721 | : "r" (x)); \ | |
1722 | }) | |
1723 | ||
1724 | #define mthi3(x) \ | |
1725 | ({ \ | |
1726 | __asm__( \ | |
1727 | " .set push \n" \ | |
1728 | " .set dsp \n" \ | |
1729 | " mthi %0, $ac3 \n" \ | |
1730 | " .set pop \n" \ | |
1731 | : \ | |
1732 | : "r" (x)); \ | |
1733 | }) | |
e50c0a8f RB |
1734 | |
1735 | #else | |
1736 | ||
d0c1b478 SH |
1737 | #ifdef CONFIG_CPU_MICROMIPS |
1738 | #define rddsp(mask) \ | |
e50c0a8f | 1739 | ({ \ |
d0c1b478 | 1740 | unsigned int __res; \ |
e50c0a8f RB |
1741 | \ |
1742 | __asm__ __volatile__( \ | |
e50c0a8f RB |
1743 | " .set push \n" \ |
1744 | " .set noat \n" \ | |
d0c1b478 SH |
1745 | " # rddsp $1, %x1 \n" \ |
1746 | " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ | |
1747 | " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ | |
1748 | " move %0, $1 \n" \ | |
e50c0a8f | 1749 | " .set pop \n" \ |
d0c1b478 SH |
1750 | : "=r" (__res) \ |
1751 | : "i" (mask)); \ | |
1752 | __res; \ | |
1753 | }) | |
e50c0a8f | 1754 | |
d0c1b478 | 1755 | #define wrdsp(val, mask) \ |
e50c0a8f RB |
1756 | do { \ |
1757 | __asm__ __volatile__( \ | |
1758 | " .set push \n" \ | |
1759 | " .set noat \n" \ | |
1760 | " move $1, %0 \n" \ | |
d0c1b478 SH |
1761 | " # wrdsp $1, %x1 \n" \ |
1762 | " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ | |
1763 | " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ | |
e50c0a8f RB |
1764 | " .set pop \n" \ |
1765 | : \ | |
d0c1b478 | 1766 | : "r" (val), "i" (mask)); \ |
e50c0a8f RB |
1767 | } while (0) |
1768 | ||
d0c1b478 SH |
1769 | #define _umips_dsp_mfxxx(ins) \ |
1770 | ({ \ | |
1771 | unsigned long __treg; \ | |
1772 | \ | |
e50c0a8f RB |
1773 | __asm__ __volatile__( \ |
1774 | " .set push \n" \ | |
1775 | " .set noat \n" \ | |
d0c1b478 SH |
1776 | " .hword 0x0001 \n" \ |
1777 | " .hword %x1 \n" \ | |
1778 | " move %0, $1 \n" \ | |
e50c0a8f | 1779 | " .set pop \n" \ |
d0c1b478 SH |
1780 | : "=r" (__treg) \ |
1781 | : "i" (ins)); \ | |
1782 | __treg; \ | |
1783 | }) | |
e50c0a8f | 1784 | |
d0c1b478 | 1785 | #define _umips_dsp_mtxxx(val, ins) \ |
e50c0a8f RB |
1786 | do { \ |
1787 | __asm__ __volatile__( \ | |
1788 | " .set push \n" \ | |
1789 | " .set noat \n" \ | |
1790 | " move $1, %0 \n" \ | |
d0c1b478 SH |
1791 | " .hword 0x0001 \n" \ |
1792 | " .hword %x1 \n" \ | |
e50c0a8f RB |
1793 | " .set pop \n" \ |
1794 | : \ | |
d0c1b478 | 1795 | : "r" (val), "i" (ins)); \ |
e50c0a8f RB |
1796 | } while (0) |
1797 | ||
d0c1b478 SH |
1798 | #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) |
1799 | #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) | |
1800 | ||
1801 | #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) | |
1802 | #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) | |
1803 | ||
1804 | #define mflo0() _umips_dsp_mflo(0) | |
1805 | #define mflo1() _umips_dsp_mflo(1) | |
1806 | #define mflo2() _umips_dsp_mflo(2) | |
1807 | #define mflo3() _umips_dsp_mflo(3) | |
1808 | ||
1809 | #define mfhi0() _umips_dsp_mfhi(0) | |
1810 | #define mfhi1() _umips_dsp_mfhi(1) | |
1811 | #define mfhi2() _umips_dsp_mfhi(2) | |
1812 | #define mfhi3() _umips_dsp_mfhi(3) | |
1813 | ||
1814 | #define mtlo0(x) _umips_dsp_mtlo(x, 0) | |
1815 | #define mtlo1(x) _umips_dsp_mtlo(x, 1) | |
1816 | #define mtlo2(x) _umips_dsp_mtlo(x, 2) | |
1817 | #define mtlo3(x) _umips_dsp_mtlo(x, 3) | |
1818 | ||
1819 | #define mthi0(x) _umips_dsp_mthi(x, 0) | |
1820 | #define mthi1(x) _umips_dsp_mthi(x, 1) | |
1821 | #define mthi2(x) _umips_dsp_mthi(x, 2) | |
1822 | #define mthi3(x) _umips_dsp_mthi(x, 3) | |
1823 | ||
1824 | #else /* !CONFIG_CPU_MICROMIPS */ | |
32a7ede6 SH |
1825 | #define rddsp(mask) \ |
1826 | ({ \ | |
1827 | unsigned int __res; \ | |
1828 | \ | |
e50c0a8f | 1829 | __asm__ __volatile__( \ |
32a7ede6 SH |
1830 | " .set push \n" \ |
1831 | " .set noat \n" \ | |
1832 | " # rddsp $1, %x1 \n" \ | |
1833 | " .word 0x7c000cb8 | (%x1 << 16) \n" \ | |
1834 | " move %0, $1 \n" \ | |
1835 | " .set pop \n" \ | |
1836 | : "=r" (__res) \ | |
1837 | : "i" (mask)); \ | |
1838 | __res; \ | |
1839 | }) | |
e50c0a8f | 1840 | |
32a7ede6 | 1841 | #define wrdsp(val, mask) \ |
e50c0a8f RB |
1842 | do { \ |
1843 | __asm__ __volatile__( \ | |
1844 | " .set push \n" \ | |
1845 | " .set noat \n" \ | |
1846 | " move $1, %0 \n" \ | |
32a7ede6 SH |
1847 | " # wrdsp $1, %x1 \n" \ |
1848 | " .word 0x7c2004f8 | (%x1 << 11) \n" \ | |
e50c0a8f | 1849 | " .set pop \n" \ |
32a7ede6 SH |
1850 | : \ |
1851 | : "r" (val), "i" (mask)); \ | |
e50c0a8f RB |
1852 | } while (0) |
1853 | ||
4cb764b4 | 1854 | #define _dsp_mfxxx(ins) \ |
e50c0a8f RB |
1855 | ({ \ |
1856 | unsigned long __treg; \ | |
1857 | \ | |
e50c0a8f RB |
1858 | __asm__ __volatile__( \ |
1859 | " .set push \n" \ | |
1860 | " .set noat \n" \ | |
4cb764b4 SH |
1861 | " .word (0x00000810 | %1) \n" \ |
1862 | " move %0, $1 \n" \ | |
e50c0a8f | 1863 | " .set pop \n" \ |
4cb764b4 SH |
1864 | : "=r" (__treg) \ |
1865 | : "i" (ins)); \ | |
1866 | __treg; \ | |
1867 | }) | |
e50c0a8f | 1868 | |
4cb764b4 | 1869 | #define _dsp_mtxxx(val, ins) \ |
e50c0a8f RB |
1870 | do { \ |
1871 | __asm__ __volatile__( \ | |
1872 | " .set push \n" \ | |
1873 | " .set noat \n" \ | |
1874 | " move $1, %0 \n" \ | |
4cb764b4 | 1875 | " .word (0x00200011 | %1) \n" \ |
e50c0a8f RB |
1876 | " .set pop \n" \ |
1877 | : \ | |
4cb764b4 | 1878 | : "r" (val), "i" (ins)); \ |
e50c0a8f RB |
1879 | } while (0) |
1880 | ||
4cb764b4 SH |
1881 | #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) |
1882 | #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) | |
e50c0a8f | 1883 | |
4cb764b4 SH |
1884 | #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) |
1885 | #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) | |
e50c0a8f | 1886 | |
4cb764b4 SH |
1887 | #define mflo0() _dsp_mflo(0) |
1888 | #define mflo1() _dsp_mflo(1) | |
1889 | #define mflo2() _dsp_mflo(2) | |
1890 | #define mflo3() _dsp_mflo(3) | |
e50c0a8f | 1891 | |
4cb764b4 SH |
1892 | #define mfhi0() _dsp_mfhi(0) |
1893 | #define mfhi1() _dsp_mfhi(1) | |
1894 | #define mfhi2() _dsp_mfhi(2) | |
1895 | #define mfhi3() _dsp_mfhi(3) | |
e50c0a8f | 1896 | |
4cb764b4 SH |
1897 | #define mtlo0(x) _dsp_mtlo(x, 0) |
1898 | #define mtlo1(x) _dsp_mtlo(x, 1) | |
1899 | #define mtlo2(x) _dsp_mtlo(x, 2) | |
1900 | #define mtlo3(x) _dsp_mtlo(x, 3) | |
e50c0a8f | 1901 | |
4cb764b4 SH |
1902 | #define mthi0(x) _dsp_mthi(x, 0) |
1903 | #define mthi1(x) _dsp_mthi(x, 1) | |
1904 | #define mthi2(x) _dsp_mthi(x, 2) | |
1905 | #define mthi3(x) _dsp_mthi(x, 3) | |
e50c0a8f | 1906 | |
d0c1b478 | 1907 | #endif /* CONFIG_CPU_MICROMIPS */ |
e50c0a8f RB |
1908 | #endif |
1909 | ||
1da177e4 LT |
1910 | /* |
1911 | * TLB operations. | |
1912 | * | |
1913 | * It is responsibility of the caller to take care of any TLB hazards. | |
1914 | */ | |
1915 | static inline void tlb_probe(void) | |
1916 | { | |
1917 | __asm__ __volatile__( | |
1918 | ".set noreorder\n\t" | |
1919 | "tlbp\n\t" | |
1920 | ".set reorder"); | |
1921 | } | |
1922 | ||
1923 | static inline void tlb_read(void) | |
1924 | { | |
9267a30d MSJ |
1925 | #if MIPS34K_MISSED_ITLB_WAR |
1926 | int res = 0; | |
1927 | ||
1928 | __asm__ __volatile__( | |
1929 | " .set push \n" | |
1930 | " .set noreorder \n" | |
1931 | " .set noat \n" | |
1932 | " .set mips32r2 \n" | |
1933 | " .word 0x41610001 # dvpe $1 \n" | |
1934 | " move %0, $1 \n" | |
1935 | " ehb \n" | |
1936 | " .set pop \n" | |
1937 | : "=r" (res)); | |
1938 | ||
1939 | instruction_hazard(); | |
1940 | #endif | |
1941 | ||
1da177e4 LT |
1942 | __asm__ __volatile__( |
1943 | ".set noreorder\n\t" | |
1944 | "tlbr\n\t" | |
1945 | ".set reorder"); | |
9267a30d MSJ |
1946 | |
1947 | #if MIPS34K_MISSED_ITLB_WAR | |
1948 | if ((res & _ULCAST_(1))) | |
1949 | __asm__ __volatile__( | |
1950 | " .set push \n" | |
1951 | " .set noreorder \n" | |
1952 | " .set noat \n" | |
1953 | " .set mips32r2 \n" | |
1954 | " .word 0x41600021 # evpe \n" | |
1955 | " ehb \n" | |
1956 | " .set pop \n"); | |
1957 | #endif | |
1da177e4 LT |
1958 | } |
1959 | ||
1960 | static inline void tlb_write_indexed(void) | |
1961 | { | |
1962 | __asm__ __volatile__( | |
1963 | ".set noreorder\n\t" | |
1964 | "tlbwi\n\t" | |
1965 | ".set reorder"); | |
1966 | } | |
1967 | ||
1968 | static inline void tlb_write_random(void) | |
1969 | { | |
1970 | __asm__ __volatile__( | |
1971 | ".set noreorder\n\t" | |
1972 | "tlbwr\n\t" | |
1973 | ".set reorder"); | |
1974 | } | |
1975 | ||
1976 | /* | |
1977 | * Manipulate bits in a c0 register. | |
1978 | */ | |
1979 | #define __BUILD_SET_C0(name) \ | |
1980 | static inline unsigned int \ | |
1981 | set_c0_##name(unsigned int set) \ | |
1982 | { \ | |
89e18eb3 | 1983 | unsigned int res, new; \ |
1da177e4 LT |
1984 | \ |
1985 | res = read_c0_##name(); \ | |
89e18eb3 RB |
1986 | new = res | set; \ |
1987 | write_c0_##name(new); \ | |
1da177e4 LT |
1988 | \ |
1989 | return res; \ | |
1990 | } \ | |
1991 | \ | |
1992 | static inline unsigned int \ | |
1993 | clear_c0_##name(unsigned int clear) \ | |
1994 | { \ | |
89e18eb3 | 1995 | unsigned int res, new; \ |
1da177e4 LT |
1996 | \ |
1997 | res = read_c0_##name(); \ | |
89e18eb3 RB |
1998 | new = res & ~clear; \ |
1999 | write_c0_##name(new); \ | |
1da177e4 LT |
2000 | \ |
2001 | return res; \ | |
2002 | } \ | |
2003 | \ | |
2004 | static inline unsigned int \ | |
89e18eb3 | 2005 | change_c0_##name(unsigned int change, unsigned int val) \ |
1da177e4 | 2006 | { \ |
89e18eb3 | 2007 | unsigned int res, new; \ |
1da177e4 LT |
2008 | \ |
2009 | res = read_c0_##name(); \ | |
89e18eb3 RB |
2010 | new = res & ~change; \ |
2011 | new |= (val & change); \ | |
2012 | write_c0_##name(new); \ | |
1da177e4 LT |
2013 | \ |
2014 | return res; \ | |
2015 | } | |
2016 | ||
2017 | __BUILD_SET_C0(status) | |
2018 | __BUILD_SET_C0(cause) | |
2019 | __BUILD_SET_C0(config) | |
7f65afb9 | 2020 | __BUILD_SET_C0(config5) |
1da177e4 | 2021 | __BUILD_SET_C0(intcontrol) |
7a0fc58c RB |
2022 | __BUILD_SET_C0(intctl) |
2023 | __BUILD_SET_C0(srsmap) | |
a5770df0 | 2024 | __BUILD_SET_C0(pagegrain) |
020232f1 KC |
2025 | __BUILD_SET_C0(brcm_config_0) |
2026 | __BUILD_SET_C0(brcm_bus_pll) | |
2027 | __BUILD_SET_C0(brcm_reset) | |
2028 | __BUILD_SET_C0(brcm_cmt_intr) | |
2029 | __BUILD_SET_C0(brcm_cmt_ctrl) | |
2030 | __BUILD_SET_C0(brcm_config) | |
2031 | __BUILD_SET_C0(brcm_mode) | |
1da177e4 | 2032 | |
45b585c8 DD |
2033 | /* |
2034 | * Return low 10 bits of ebase. | |
2035 | * Note that under KVM (MIPSVZ) this returns vcpu id. | |
2036 | */ | |
2037 | static inline unsigned int get_ebase_cpunum(void) | |
2038 | { | |
2039 | return read_c0_ebase() & 0x3ff; | |
2040 | } | |
2041 | ||
1da177e4 LT |
2042 | #endif /* !__ASSEMBLY__ */ |
2043 | ||
2044 | #endif /* _ASM_MIPSREGS_H */ |