Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Switch a MMU context. | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | */ | |
11 | #ifndef _ASM_MMU_CONTEXT_H | |
12 | #define _ASM_MMU_CONTEXT_H | |
13 | ||
1da177e4 LT |
14 | #include <linux/errno.h> |
15 | #include <linux/sched.h> | |
631330f5 | 16 | #include <linux/smp.h> |
1da177e4 LT |
17 | #include <linux/slab.h> |
18 | #include <asm/cacheflush.h> | |
c2ea1d56 | 19 | #include <asm/hazards.h> |
1da177e4 | 20 | #include <asm/tlbflush.h> |
d6dd61c8 | 21 | #include <asm-generic/mm_hooks.h> |
1da177e4 | 22 | |
f1014d1b MC |
23 | #define htw_set_pwbase(pgd) \ |
24 | do { \ | |
25 | if (cpu_has_htw) { \ | |
26 | write_c0_pwbase(pgd); \ | |
27 | back_to_back_c0_hazard(); \ | |
f1014d1b MC |
28 | } \ |
29 | } while (0) | |
30 | ||
0bfbf6a2 RB |
31 | #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ |
32 | do { \ | |
6ba045f9 | 33 | extern void tlbmiss_handler_setup_pgd(unsigned long); \ |
0bfbf6a2 | 34 | tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ |
f1014d1b | 35 | htw_set_pwbase((unsigned long)pgd); \ |
0bfbf6a2 | 36 | } while (0) |
82622284 | 37 | |
f4ae17aa | 38 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
ae4ce454 JH |
39 | |
40 | #define TLBMISS_HANDLER_RESTORE() \ | |
41 | write_c0_xcontext((unsigned long) smp_processor_id() << \ | |
42 | SMP_CPUID_REGSHIFT) | |
43 | ||
82622284 DD |
44 | #define TLBMISS_HANDLER_SETUP() \ |
45 | do { \ | |
46 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ | |
ae4ce454 | 47 | TLBMISS_HANDLER_RESTORE(); \ |
82622284 DD |
48 | } while (0) |
49 | ||
c2377a42 | 50 | #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ |
82622284 | 51 | |
1da177e4 LT |
52 | /* |
53 | * For the fast tlb miss handlers, we keep a per cpu array of pointers | |
54 | * to the current pgd for each processor. Also, the proc. id is stuffed | |
55 | * into the context register. | |
56 | */ | |
57 | extern unsigned long pgd_current[]; | |
58 | ||
ae4ce454 | 59 | #define TLBMISS_HANDLER_RESTORE() \ |
c2377a42 | 60 | write_c0_context((unsigned long) smp_processor_id() << \ |
ae4ce454 JH |
61 | SMP_CPUID_REGSHIFT) |
62 | ||
63 | #define TLBMISS_HANDLER_SETUP() \ | |
64 | TLBMISS_HANDLER_RESTORE(); \ | |
c2ea1d56 | 65 | back_to_back_c0_hazard(); \ |
1da177e4 | 66 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) |
82622284 | 67 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ |
1da177e4 | 68 | |
4edf00a4 PB |
69 | /* |
70 | * All unused by hardware upper bits will be considered | |
71 | * as a software asid extension. | |
72 | */ | |
73 | static unsigned long asid_version_mask(unsigned int cpu) | |
74 | { | |
75 | unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]); | |
48c4ac97 | 76 | |
4edf00a4 PB |
77 | return ~(asid_mask | (asid_mask - 1)); |
78 | } | |
1da177e4 | 79 | |
4edf00a4 PB |
80 | static unsigned long asid_first_version(unsigned int cpu) |
81 | { | |
82 | return ~asid_version_mask(cpu) + 1; | |
83 | } | |
1da177e4 | 84 | |
c52d0d30 | 85 | #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) |
1da177e4 | 86 | #define asid_cache(cpu) (cpu_data[cpu].asid_cache) |
4edf00a4 PB |
87 | #define cpu_asid(cpu, mm) \ |
88 | (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu])) | |
1da177e4 LT |
89 | |
90 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | |
91 | { | |
92 | } | |
93 | ||
48c4ac97 | 94 | |
41c594ab | 95 | /* Normal, classic MIPS get_new_mmu_context */ |
1da177e4 LT |
96 | static inline void |
97 | get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) | |
98 | { | |
f9afbd45 | 99 | extern void kvm_local_flush_tlb_all(void); |
1da177e4 LT |
100 | unsigned long asid = asid_cache(cpu); |
101 | ||
4edf00a4 | 102 | if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) { |
1da177e4 LT |
103 | if (cpu_has_vtag_icache) |
104 | flush_icache_all(); | |
d414976d | 105 | #ifdef CONFIG_KVM |
f9afbd45 SL |
106 | kvm_local_flush_tlb_all(); /* start new asid cycle */ |
107 | #else | |
1da177e4 | 108 | local_flush_tlb_all(); /* start new asid cycle */ |
f9afbd45 | 109 | #endif |
1da177e4 | 110 | if (!asid) /* fix version if needed */ |
4edf00a4 | 111 | asid = asid_first_version(cpu); |
1da177e4 | 112 | } |
f9afbd45 | 113 | |
1da177e4 LT |
114 | cpu_context(cpu, mm) = asid_cache(cpu) = asid; |
115 | } | |
116 | ||
117 | /* | |
118 | * Initialize the context related info for a new mm_struct | |
119 | * instance. | |
120 | */ | |
121 | static inline int | |
122 | init_new_context(struct task_struct *tsk, struct mm_struct *mm) | |
123 | { | |
124 | int i; | |
125 | ||
22478677 | 126 | for_each_possible_cpu(i) |
1da177e4 LT |
127 | cpu_context(i, mm) = 0; |
128 | ||
9791554b PB |
129 | atomic_set(&mm->context.fp_mode_switching, 0); |
130 | ||
1da177e4 LT |
131 | return 0; |
132 | } | |
133 | ||
134 | static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | |
70342287 | 135 | struct task_struct *tsk) |
1da177e4 LT |
136 | { |
137 | unsigned int cpu = smp_processor_id(); | |
138 | unsigned long flags; | |
41c594ab | 139 | local_irq_save(flags); |
1da177e4 | 140 | |
ed4cbc81 | 141 | htw_stop(); |
1da177e4 | 142 | /* Check if our ASID is of an older version and thus invalid */ |
4edf00a4 | 143 | if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu)) |
1da177e4 | 144 | get_new_mmu_context(next, cpu); |
d30cecbc | 145 | write_c0_entryhi(cpu_asid(cpu, next)); |
1da177e4 LT |
146 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); |
147 | ||
148 | /* | |
149 | * Mark current->active_mm as not "active" anymore. | |
150 | * We don't want to mislead possible IPI tlb flush routines. | |
151 | */ | |
55b8cab4 RR |
152 | cpumask_clear_cpu(cpu, mm_cpumask(prev)); |
153 | cpumask_set_cpu(cpu, mm_cpumask(next)); | |
ed4cbc81 | 154 | htw_start(); |
1da177e4 LT |
155 | |
156 | local_irq_restore(flags); | |
157 | } | |
158 | ||
159 | /* | |
160 | * Destroy context related info for an mm_struct that is about | |
161 | * to be put to rest. | |
162 | */ | |
163 | static inline void destroy_context(struct mm_struct *mm) | |
164 | { | |
165 | } | |
166 | ||
21a151d8 | 167 | #define deactivate_mm(tsk, mm) do { } while (0) |
1da177e4 LT |
168 | |
169 | /* | |
170 | * After we have set current->mm to a new value, this activates | |
171 | * the context for the new mm so we see the new mappings. | |
172 | */ | |
173 | static inline void | |
174 | activate_mm(struct mm_struct *prev, struct mm_struct *next) | |
175 | { | |
176 | unsigned long flags; | |
177 | unsigned int cpu = smp_processor_id(); | |
178 | ||
179 | local_irq_save(flags); | |
180 | ||
ed4cbc81 | 181 | htw_stop(); |
1da177e4 LT |
182 | /* Unconditionally get a new ASID. */ |
183 | get_new_mmu_context(next, cpu); | |
184 | ||
d30cecbc | 185 | write_c0_entryhi(cpu_asid(cpu, next)); |
1da177e4 LT |
186 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); |
187 | ||
188 | /* mark mmu ownership change */ | |
55b8cab4 RR |
189 | cpumask_clear_cpu(cpu, mm_cpumask(prev)); |
190 | cpumask_set_cpu(cpu, mm_cpumask(next)); | |
ed4cbc81 | 191 | htw_start(); |
1da177e4 LT |
192 | |
193 | local_irq_restore(flags); | |
194 | } | |
195 | ||
196 | /* | |
197 | * If mm is currently active_mm, we can't really drop it. Instead, | |
198 | * we will get a new one for it. | |
199 | */ | |
200 | static inline void | |
201 | drop_mmu_context(struct mm_struct *mm, unsigned cpu) | |
202 | { | |
203 | unsigned long flags; | |
204 | ||
205 | local_irq_save(flags); | |
ed4cbc81 | 206 | htw_stop(); |
1da177e4 | 207 | |
55b8cab4 | 208 | if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { |
1da177e4 LT |
209 | get_new_mmu_context(mm, cpu); |
210 | write_c0_entryhi(cpu_asid(cpu, mm)); | |
211 | } else { | |
212 | /* will get a new context next time */ | |
213 | cpu_context(cpu, mm) = 0; | |
214 | } | |
ed4cbc81 | 215 | htw_start(); |
1da177e4 LT |
216 | local_irq_restore(flags); |
217 | } | |
218 | ||
219 | #endif /* _ASM_MMU_CONTEXT_H */ |