[deliverable/linux.git] / arch / mips / include / asm / mmu_context.h

/*
 * Switch a MMU context.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
 * Copyright (C) 1999 Silicon Graphics, Inc.
 */
#ifndef _ASM_MMU_CONTEXT_H
#define _ASM_MMU_CONTEXT_H

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/slab.h>
#include <asm/cacheflush.h>
#include <asm/hazards.h>
#include <asm/tlbflush.h>
#ifdef CONFIG_MIPS_MT_SMTC
#include <asm/mipsmtregs.h>
#include <asm/smtc.h>
#endif /* SMTC */
#include <asm-generic/mm_hooks.h>

#ifdef CONFIG_MIPS_PGD_C0_CONTEXT

#define TLBMISS_HANDLER_SETUP_PGD(pgd)					\
do {									\
	extern void tlbmiss_handler_setup_pgd(unsigned long);		\
	tlbmiss_handler_setup_pgd((unsigned long)(pgd));		\
} while (0)

#define TLBMISS_HANDLER_SETUP()						\
	do {								\
		TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);		\
		write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
	} while (0)

#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/

/*
 * For the fast tlb miss handlers, we keep a per cpu array of pointers
 * to the current pgd for each processor. Also, the proc. id is stuffed
 * into the context register.
 */
extern unsigned long pgd_current[];

#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
	pgd_current[smp_processor_id()] = (unsigned long)(pgd)

#ifdef CONFIG_32BIT
#define TLBMISS_HANDLER_SETUP()						\
	write_c0_context((unsigned long) smp_processor_id() << 25);	\
	back_to_back_c0_hazard();					\
	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
#endif
#ifdef CONFIG_64BIT
#define TLBMISS_HANDLER_SETUP()						\
	write_c0_context((unsigned long) smp_processor_id() << 26);	\
	back_to_back_c0_hazard();					\
	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
#endif
#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

#define ASID_INC	0x40
#define ASID_MASK	0xfc0

#elif defined(CONFIG_CPU_R8000)

#define ASID_INC	0x10
#define ASID_MASK	0xff0

#elif defined(CONFIG_MIPS_MT_SMTC)

#define ASID_INC	0x1
extern unsigned long smtc_asid_mask;
#define ASID_MASK	(smtc_asid_mask)
#define HW_ASID_MASK	0xff
/* End SMTC/34K debug hack */
#else /* FIXME: not correct for R6000 */

#define ASID_INC	0x1
#define ASID_MASK	0xff

#endif

#define cpu_context(cpu, mm)	((mm)->context.asid[cpu])
#define cpu_asid(cpu, mm)	(cpu_context((cpu), (mm)) & ASID_MASK)
#define asid_cache(cpu)		(cpu_data[cpu].asid_cache)

static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}

/*
 *  All unused by hardware upper bits will be considered
 *  as a software asid extension.
 */
#define ASID_VERSION_MASK  ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)

#ifndef CONFIG_MIPS_MT_SMTC
/* Normal, classic MIPS get_new_mmu_context */
static inline void
get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
{
	extern void kvm_local_flush_tlb_all(void);
	unsigned long asid = asid_cache(cpu);

	if (! ((asid += ASID_INC) & ASID_MASK) ) {
		if (cpu_has_vtag_icache)
			flush_icache_all();
#ifdef CONFIG_KVM
		kvm_local_flush_tlb_all();      /* start new asid cycle */
#else
		local_flush_tlb_all();	/* start new asid cycle */
#endif
		if (!asid)		/* fix version if needed */
			asid = ASID_FIRST_VERSION;
	}

	cpu_context(cpu, mm) = asid_cache(cpu) = asid;
}

#else /* CONFIG_MIPS_MT_SMTC */

#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))

#endif /* CONFIG_MIPS_MT_SMTC */

/*
 * Initialize the context related info for a new mm_struct
 * instance.
 */
static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
	int i;

	for_each_possible_cpu(i)
		cpu_context(i, mm) = 0;

	return 0;
}

static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
			     struct task_struct *tsk)
{
	unsigned int cpu = smp_processor_id();
	unsigned long flags;
#ifdef CONFIG_MIPS_MT_SMTC
	unsigned long oldasid;
	unsigned long mtflags;
	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
	local_irq_save(flags);
	mtflags = dvpe();
#else /* Not SMTC */
	local_irq_save(flags);
#endif /* CONFIG_MIPS_MT_SMTC */

	/* Check if our ASID is of an older version and thus invalid */
	if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
		get_new_mmu_context(next, cpu);
#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * If the EntryHi ASID being replaced happens to be
	 * the value flagged at ASID recycling time as having
	 * an extended life, clear the bit showing it being
	 * in use by this "CPU", and if that's the last bit,
	 * free up the ASID value for use and flush any old
	 * instances of it from the TLB.
	 */
	oldasid = (read_c0_entryhi() & ASID_MASK);
	if(smtc_live_asid[mytlb][oldasid]) {
		smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
		if(smtc_live_asid[mytlb][oldasid] == 0)
			smtc_flush_tlb_asid(oldasid);
	}
	/*
	 * Tread softly on EntryHi, and so long as we support
	 * having ASID_MASK smaller than the hardware maximum,
	 * make sure no "soft" bits become "hard"...
	 */
	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
			 cpu_asid(cpu, next));
	ehb(); /* Make sure it propagates to TCStatus */
	evpe(mtflags);
#else
	write_c0_entryhi(cpu_asid(cpu, next));
#endif /* CONFIG_MIPS_MT_SMTC */
	TLBMISS_HANDLER_SETUP_PGD(next->pgd);

	/*
	 * Mark current->active_mm as not "active" anymore.
	 * We don't want to mislead possible IPI tlb flush routines.
	 */
	cpumask_clear_cpu(cpu, mm_cpumask(prev));
	cpumask_set_cpu(cpu, mm_cpumask(next));

	local_irq_restore(flags);
}

/*
 * Destroy context related info for an mm_struct that is about
 * to be put to rest.
 */
static inline void destroy_context(struct mm_struct *mm)
{
}

#define deactivate_mm(tsk, mm)	do { } while (0)

/*
 * After we have set current->mm to a new value, this activates
 * the context for the new mm so we see the new mappings.
 */
static inline void
activate_mm(struct mm_struct *prev, struct mm_struct *next)
{
	unsigned long flags;
	unsigned int cpu = smp_processor_id();

#ifdef CONFIG_MIPS_MT_SMTC
	unsigned long oldasid;
	unsigned long mtflags;
	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
#endif /* CONFIG_MIPS_MT_SMTC */

	local_irq_save(flags);

	/* Unconditionally get a new ASID.  */
	get_new_mmu_context(next, cpu);

#ifdef CONFIG_MIPS_MT_SMTC
	/* See comments for similar code above */
	mtflags = dvpe();
	oldasid = read_c0_entryhi() & ASID_MASK;
	if(smtc_live_asid[mytlb][oldasid]) {
		smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
		if(smtc_live_asid[mytlb][oldasid] == 0)
			 smtc_flush_tlb_asid(oldasid);
	}
	/* See comments for similar code above */
	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
			 cpu_asid(cpu, next));
	ehb(); /* Make sure it propagates to TCStatus */
	evpe(mtflags);
#else
	write_c0_entryhi(cpu_asid(cpu, next));
#endif /* CONFIG_MIPS_MT_SMTC */
	TLBMISS_HANDLER_SETUP_PGD(next->pgd);

	/* mark mmu ownership change */
	cpumask_clear_cpu(cpu, mm_cpumask(prev));
	cpumask_set_cpu(cpu, mm_cpumask(next));

	local_irq_restore(flags);
}

/*
 * If mm is currently active_mm, we can't really drop it.  Instead,
 * we will get a new one for it.
 */
static inline void
drop_mmu_context(struct mm_struct *mm, unsigned cpu)
{
	unsigned long flags;
#ifdef CONFIG_MIPS_MT_SMTC
	unsigned long oldasid;
	/* Can't use spinlock because called from TLB flush within DVPE */
	unsigned int prevvpe;
	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
#endif /* CONFIG_MIPS_MT_SMTC */

	local_irq_save(flags);

	if (cpumask_test_cpu(cpu, mm_cpumask(mm)))  {
		get_new_mmu_context(mm, cpu);
#ifdef CONFIG_MIPS_MT_SMTC
		/* See comments for similar code above */
		prevvpe = dvpe();
		oldasid = (read_c0_entryhi() & ASID_MASK);
		if (smtc_live_asid[mytlb][oldasid]) {
			smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
			if(smtc_live_asid[mytlb][oldasid] == 0)
				smtc_flush_tlb_asid(oldasid);
		}
		/* See comments for similar code above */
		write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
				| cpu_asid(cpu, mm));
		ehb(); /* Make sure it propagates to TCStatus */
		evpe(prevvpe);
#else /* not CONFIG_MIPS_MT_SMTC */
		write_c0_entryhi(cpu_asid(cpu, mm));
#endif /* CONFIG_MIPS_MT_SMTC */
	} else {
		/* will get a new context next time */
#ifndef CONFIG_MIPS_MT_SMTC
		cpu_context(cpu, mm) = 0;
#else /* SMTC */
		int i;

		/* SMTC shares the TLB (and ASIDs) across VPEs */
		for_each_online_cpu(i) {
		    if((smtc_status & SMTC_TLB_SHARED)
		    || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
			cpu_context(i, mm) = 0;
		}
#endif /* CONFIG_MIPS_MT_SMTC */
	}
	local_irq_restore(flags);
}

#endif /* _ASM_MMU_CONTEXT_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Switch a MMU context.
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
	9	* Copyright (C) 1999 Silicon Graphics, Inc.
	10	*/
	11	#ifndef _ASM_MMU_CONTEXT_H
	12	#define _ASM_MMU_CONTEXT_H
	13
1da177e4 LT	14	#include <linux/errno.h>
1da177e4 LT	15	#include <linux/sched.h>
631330f5	16	#include <linux/smp.h>
1da177e4 LT	17	#include <linux/slab.h>
1da177e4 LT	18	#include <asm/cacheflush.h>
c2ea1d56	19	#include <asm/hazards.h>
1da177e4	20	#include <asm/tlbflush.h>
41c594ab RB	21	#ifdef CONFIG_MIPS_MT_SMTC
	22	#include <asm/mipsmtregs.h>
	23	#include <asm/smtc.h>
	24	#endif /* SMTC */
d6dd61c8	25	#include <asm-generic/mm_hooks.h>
1da177e4	26
82622284 DD	27	#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
82622284 DD	28
0bfbf6a2 RB	29	#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
0bfbf6a2 RB	30	do { \
6ba045f9	31	extern void tlbmiss_handler_setup_pgd(unsigned long); \
0bfbf6a2 RB	32	tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
0bfbf6a2 RB	33	} while (0)
82622284 DD	34
	35	#define TLBMISS_HANDLER_SETUP() \
	36	do { \
	37	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
	38	write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
	39	} while (0)
	40
82622284 DD	41	#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
82622284 DD	42
1da177e4 LT	43	/*
	44	* For the fast tlb miss handlers, we keep a per cpu array of pointers
	45	* to the current pgd for each processor. Also, the proc. id is stuffed
	46	* into the context register.
	47	*/
	48	extern unsigned long pgd_current[];
	49
	50	#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
	51	pgd_current[smp_processor_id()] = (unsigned long)(pgd)
	52
875d43e7	53	#ifdef CONFIG_32BIT
1da177e4	54	#define TLBMISS_HANDLER_SETUP() \
1b3a6e97	55	write_c0_context((unsigned long) smp_processor_id() << 25); \
c2ea1d56	56	back_to_back_c0_hazard(); \
1da177e4 LT	57	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
1da177e4 LT	58	#endif
8145095c	59	#ifdef CONFIG_64BIT
1da177e4	60	#define TLBMISS_HANDLER_SETUP() \
1b3a6e97	61	write_c0_context((unsigned long) smp_processor_id() << 26); \
c2ea1d56	62	back_to_back_c0_hazard(); \
1da177e4 LT	63	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
1da177e4 LT	64	#endif
82622284	65	#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
48c4ac97	66	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
1da177e4	67
48c4ac97 DD	68	#define ASID_INC 0x40
	69	#define ASID_MASK 0xfc0
	70
	71	#elif defined(CONFIG_CPU_R8000)
	72
	73	#define ASID_INC 0x10
	74	#define ASID_MASK 0xff0
	75
	76	#elif defined(CONFIG_MIPS_MT_SMTC)
	77
	78	#define ASID_INC 0x1
	79	extern unsigned long smtc_asid_mask;
	80	#define ASID_MASK (smtc_asid_mask)
	81	#define HW_ASID_MASK 0xff
	82	/* End SMTC/34K debug hack */
	83	#else /* FIXME: not correct for R6000 */
	84
	85	#define ASID_INC 0x1
	86	#define ASID_MASK 0xff
1da177e4 LT	87
	88	#endif
	89
c52d0d30	90	#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
48c4ac97	91	#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
1da177e4 LT	92	#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
	93
	94	static inline void enter_lazy_tlb(struct mm_struct mm, struct task_struct tsk)
	95	{
	96	}
	97
48c4ac97 DD	98	/*
	99	* All unused by hardware upper bits will be considered
	100	* as a software asid extension.
	101	*/
	102	#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK\|(ASID_MASK-1)))
	103	#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
	104
41c594ab RB	105	#ifndef CONFIG_MIPS_MT_SMTC
41c594ab RB	106	/* Normal, classic MIPS get_new_mmu_context */
1da177e4 LT	107	static inline void
	108	get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
	109	{
f9afbd45	110	extern void kvm_local_flush_tlb_all(void);
1da177e4 LT	111	unsigned long asid = asid_cache(cpu);
1da177e4 LT	112
48c4ac97	113	if (! ((asid += ASID_INC) & ASID_MASK) ) {
1da177e4 LT	114	if (cpu_has_vtag_icache)
1da177e4 LT	115	flush_icache_all();
d414976d	116	#ifdef CONFIG_KVM
f9afbd45 SL	117	kvm_local_flush_tlb_all(); /* start new asid cycle */
f9afbd45 SL	118	#else
1da177e4	119	local_flush_tlb_all(); /* start new asid cycle */
f9afbd45	120	#endif
1da177e4 LT	121	if (!asid) /* fix version if needed */
	122	asid = ASID_FIRST_VERSION;
	123	}
f9afbd45	124
1da177e4 LT	125	cpu_context(cpu, mm) = asid_cache(cpu) = asid;
	126	}
	127
41c594ab RB	128	#else /* CONFIG_MIPS_MT_SMTC */
41c594ab RB	129
21a151d8	130	#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))
41c594ab RB	131
	132	#endif /* CONFIG_MIPS_MT_SMTC */
	133
1da177e4 LT	134	/*
	135	* Initialize the context related info for a new mm_struct
	136	* instance.
	137	*/
	138	static inline int
	139	init_new_context(struct task_struct tsk, struct mm_struct mm)
	140	{
	141	int i;
	142
22478677	143	for_each_possible_cpu(i)
1da177e4 LT	144	cpu_context(i, mm) = 0;
	145
	146	return 0;
	147	}
	148
	149	static inline void switch_mm(struct mm_struct prev, struct mm_struct next,
70342287	150	struct task_struct *tsk)
1da177e4 LT	151	{
	152	unsigned int cpu = smp_processor_id();
	153	unsigned long flags;
41c594ab RB	154	#ifdef CONFIG_MIPS_MT_SMTC
	155	unsigned long oldasid;
	156	unsigned long mtflags;
	157	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
1da177e4	158	local_irq_save(flags);
41c594ab RB	159	mtflags = dvpe();
	160	#else /* Not SMTC */
	161	local_irq_save(flags);
	162	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	163
	164	/* Check if our ASID is of an older version and thus invalid */
	165	if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
	166	get_new_mmu_context(next, cpu);
41c594ab RB	167	#ifdef CONFIG_MIPS_MT_SMTC
	168	/*
	169	* If the EntryHi ASID being replaced happens to be
	170	* the value flagged at ASID recycling time as having
	171	* an extended life, clear the bit showing it being
	172	* in use by this "CPU", and if that's the last bit,
	173	* free up the ASID value for use and flush any old
	174	* instances of it from the TLB.
	175	*/
48c4ac97	176	oldasid = (read_c0_entryhi() & ASID_MASK);
41c594ab RB	177	if(smtc_live_asid[mytlb][oldasid]) {
	178	smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
	179	if(smtc_live_asid[mytlb][oldasid] == 0)
	180	smtc_flush_tlb_asid(oldasid);
	181	}
	182	/*
	183	* Tread softly on EntryHi, and so long as we support
	184	* having ASID_MASK smaller than the hardware maximum,
	185	* make sure no "soft" bits become "hard"...
	186	*/
48c4ac97	187	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) \|
d30cecbc	188	cpu_asid(cpu, next));
41c594ab RB	189	ehb(); /* Make sure it propagates to TCStatus */
	190	evpe(mtflags);
	191	#else
d30cecbc	192	write_c0_entryhi(cpu_asid(cpu, next));
41c594ab	193	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	194	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
	195
	196	/*
	197	* Mark current->active_mm as not "active" anymore.
	198	* We don't want to mislead possible IPI tlb flush routines.
	199	*/
55b8cab4 RR	200	cpumask_clear_cpu(cpu, mm_cpumask(prev));
55b8cab4 RR	201	cpumask_set_cpu(cpu, mm_cpumask(next));
1da177e4 LT	202
	203	local_irq_restore(flags);
	204	}
	205
	206	/*
	207	* Destroy context related info for an mm_struct that is about
	208	* to be put to rest.
	209	*/
	210	static inline void destroy_context(struct mm_struct *mm)
	211	{
	212	}
	213
21a151d8	214	#define deactivate_mm(tsk, mm) do { } while (0)
1da177e4 LT	215
	216	/*
	217	* After we have set current->mm to a new value, this activates
	218	* the context for the new mm so we see the new mappings.
	219	*/
	220	static inline void
	221	activate_mm(struct mm_struct prev, struct mm_struct next)
	222	{
	223	unsigned long flags;
	224	unsigned int cpu = smp_processor_id();
	225
41c594ab RB	226	#ifdef CONFIG_MIPS_MT_SMTC
	227	unsigned long oldasid;
	228	unsigned long mtflags;
	229	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
	230	#endif /* CONFIG_MIPS_MT_SMTC */
	231
1da177e4 LT	232	local_irq_save(flags);
	233
	234	/* Unconditionally get a new ASID. */
	235	get_new_mmu_context(next, cpu);
	236
41c594ab RB	237	#ifdef CONFIG_MIPS_MT_SMTC
	238	/* See comments for similar code above */
	239	mtflags = dvpe();
48c4ac97	240	oldasid = read_c0_entryhi() & ASID_MASK;
41c594ab RB	241	if(smtc_live_asid[mytlb][oldasid]) {
41c594ab RB	242	smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
384740dc RB	243	if(smtc_live_asid[mytlb][oldasid] == 0)
384740dc RB	244	smtc_flush_tlb_asid(oldasid);
41c594ab RB	245	}
41c594ab RB	246	/* See comments for similar code above */
48c4ac97 DD	247	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) \|
48c4ac97 DD	248	cpu_asid(cpu, next));
41c594ab RB	249	ehb(); /* Make sure it propagates to TCStatus */
	250	evpe(mtflags);
	251	#else
d30cecbc	252	write_c0_entryhi(cpu_asid(cpu, next));
41c594ab	253	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	254	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
	255
	256	/* mark mmu ownership change */
55b8cab4 RR	257	cpumask_clear_cpu(cpu, mm_cpumask(prev));
55b8cab4 RR	258	cpumask_set_cpu(cpu, mm_cpumask(next));
1da177e4 LT	259
	260	local_irq_restore(flags);
	261	}
	262
	263	/*
	264	* If mm is currently active_mm, we can't really drop it. Instead,
	265	* we will get a new one for it.
	266	*/
	267	static inline void
	268	drop_mmu_context(struct mm_struct *mm, unsigned cpu)
	269	{
	270	unsigned long flags;
41c594ab RB	271	#ifdef CONFIG_MIPS_MT_SMTC
	272	unsigned long oldasid;
	273	/* Can't use spinlock because called from TLB flush within DVPE */
	274	unsigned int prevvpe;
	275	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
	276	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	277
	278	local_irq_save(flags);
	279
55b8cab4	280	if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
1da177e4	281	get_new_mmu_context(mm, cpu);
41c594ab RB	282	#ifdef CONFIG_MIPS_MT_SMTC
	283	/* See comments for similar code above */
	284	prevvpe = dvpe();
48c4ac97	285	oldasid = (read_c0_entryhi() & ASID_MASK);
6b8aab09 RB	286	if (smtc_live_asid[mytlb][oldasid]) {
	287	smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
	288	if(smtc_live_asid[mytlb][oldasid] == 0)
	289	smtc_flush_tlb_asid(oldasid);
41c594ab RB	290	}
41c594ab RB	291	/* See comments for similar code above */
48c4ac97	292	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
41c594ab RB	293	\| cpu_asid(cpu, mm));
	294	ehb(); /* Make sure it propagates to TCStatus */
	295	evpe(prevvpe);
	296	#else /* not CONFIG_MIPS_MT_SMTC */
1da177e4	297	write_c0_entryhi(cpu_asid(cpu, mm));
41c594ab	298	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	299	} else {
1da177e4 LT	300	/* will get a new context next time */
41c594ab	301	#ifndef CONFIG_MIPS_MT_SMTC
1da177e4	302	cpu_context(cpu, mm) = 0;
41c594ab RB	303	#else /* SMTC */
	304	int i;
	305
	306	/* SMTC shares the TLB (and ASIDs) across VPEs */
b5eb5511	307	for_each_online_cpu(i) {
384740dc RB	308	if((smtc_status & SMTC_TLB_SHARED)
384740dc RB	309	\|\| (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
41c594ab RB	310	cpu_context(i, mm) = 0;
	311	}
	312	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4	313	}
1da177e4 LT	314	local_irq_restore(flags);
	315	}
	316
	317	#endif /* _ASM_MMU_CONTEXT_H */