Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Switch a MMU context. | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | */ | |
11 | #ifndef _ASM_MMU_CONTEXT_H | |
12 | #define _ASM_MMU_CONTEXT_H | |
13 | ||
1da177e4 LT |
14 | #include <linux/errno.h> |
15 | #include <linux/sched.h> | |
631330f5 | 16 | #include <linux/smp.h> |
1da177e4 LT |
17 | #include <linux/slab.h> |
18 | #include <asm/cacheflush.h> | |
c2ea1d56 | 19 | #include <asm/hazards.h> |
1da177e4 | 20 | #include <asm/tlbflush.h> |
41c594ab RB |
21 | #ifdef CONFIG_MIPS_MT_SMTC |
22 | #include <asm/mipsmtregs.h> | |
23 | #include <asm/smtc.h> | |
24 | #endif /* SMTC */ | |
d6dd61c8 | 25 | #include <asm-generic/mm_hooks.h> |
1da177e4 | 26 | |
82622284 DD |
27 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
28 | ||
29 | #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ | |
30 | tlbmiss_handler_setup_pgd((unsigned long)(pgd)) | |
31 | ||
3d8bfdd0 | 32 | extern void tlbmiss_handler_setup_pgd(unsigned long pgd); |
82622284 DD |
33 | |
34 | #define TLBMISS_HANDLER_SETUP() \ | |
35 | do { \ | |
36 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ | |
37 | write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ | |
38 | } while (0) | |
39 | ||
82622284 DD |
40 | #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ |
41 | ||
1da177e4 LT |
42 | /* |
43 | * For the fast tlb miss handlers, we keep a per cpu array of pointers | |
44 | * to the current pgd for each processor. Also, the proc. id is stuffed | |
45 | * into the context register. | |
46 | */ | |
47 | extern unsigned long pgd_current[]; | |
48 | ||
49 | #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ | |
50 | pgd_current[smp_processor_id()] = (unsigned long)(pgd) | |
51 | ||
875d43e7 | 52 | #ifdef CONFIG_32BIT |
1da177e4 | 53 | #define TLBMISS_HANDLER_SETUP() \ |
1b3a6e97 | 54 | write_c0_context((unsigned long) smp_processor_id() << 25); \ |
c2ea1d56 | 55 | back_to_back_c0_hazard(); \ |
1da177e4 LT |
56 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) |
57 | #endif | |
8145095c | 58 | #ifdef CONFIG_64BIT |
1da177e4 | 59 | #define TLBMISS_HANDLER_SETUP() \ |
1b3a6e97 | 60 | write_c0_context((unsigned long) smp_processor_id() << 26); \ |
c2ea1d56 | 61 | back_to_back_c0_hazard(); \ |
1da177e4 LT |
62 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) |
63 | #endif | |
82622284 | 64 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ |
1da177e4 LT |
65 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) |
66 | ||
67 | #define ASID_INC 0x40 | |
68 | #define ASID_MASK 0xfc0 | |
69 | ||
70 | #elif defined(CONFIG_CPU_R8000) | |
71 | ||
72 | #define ASID_INC 0x10 | |
73 | #define ASID_MASK 0xff0 | |
74 | ||
41c594ab RB |
75 | #elif defined(CONFIG_MIPS_MT_SMTC) |
76 | ||
77 | #define ASID_INC 0x1 | |
78 | extern unsigned long smtc_asid_mask; | |
79 | #define ASID_MASK (smtc_asid_mask) | |
70342287 | 80 | #define HW_ASID_MASK 0xff |
41c594ab | 81 | /* End SMTC/34K debug hack */ |
1da177e4 LT |
82 | #else /* FIXME: not correct for R6000 */ |
83 | ||
84 | #define ASID_INC 0x1 | |
85 | #define ASID_MASK 0xff | |
86 | ||
87 | #endif | |
88 | ||
c52d0d30 | 89 | #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) |
1da177e4 LT |
90 | #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) |
91 | #define asid_cache(cpu) (cpu_data[cpu].asid_cache) | |
92 | ||
93 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | |
94 | { | |
95 | } | |
96 | ||
97 | /* | |
98 | * All unused by hardware upper bits will be considered | |
99 | * as a software asid extension. | |
100 | */ | |
101 | #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) | |
102 | #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) | |
103 | ||
41c594ab RB |
104 | #ifndef CONFIG_MIPS_MT_SMTC |
105 | /* Normal, classic MIPS get_new_mmu_context */ | |
1da177e4 LT |
106 | static inline void |
107 | get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) | |
108 | { | |
109 | unsigned long asid = asid_cache(cpu); | |
110 | ||
111 | if (! ((asid += ASID_INC) & ASID_MASK) ) { | |
112 | if (cpu_has_vtag_icache) | |
113 | flush_icache_all(); | |
114 | local_flush_tlb_all(); /* start new asid cycle */ | |
115 | if (!asid) /* fix version if needed */ | |
116 | asid = ASID_FIRST_VERSION; | |
117 | } | |
118 | cpu_context(cpu, mm) = asid_cache(cpu) = asid; | |
119 | } | |
120 | ||
41c594ab RB |
121 | #else /* CONFIG_MIPS_MT_SMTC */ |
122 | ||
21a151d8 | 123 | #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) |
41c594ab RB |
124 | |
125 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
126 | ||
1da177e4 LT |
127 | /* |
128 | * Initialize the context related info for a new mm_struct | |
129 | * instance. | |
130 | */ | |
131 | static inline int | |
132 | init_new_context(struct task_struct *tsk, struct mm_struct *mm) | |
133 | { | |
134 | int i; | |
135 | ||
b5eb5511 | 136 | for_each_online_cpu(i) |
1da177e4 LT |
137 | cpu_context(i, mm) = 0; |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | |
70342287 | 143 | struct task_struct *tsk) |
1da177e4 LT |
144 | { |
145 | unsigned int cpu = smp_processor_id(); | |
146 | unsigned long flags; | |
41c594ab RB |
147 | #ifdef CONFIG_MIPS_MT_SMTC |
148 | unsigned long oldasid; | |
149 | unsigned long mtflags; | |
150 | int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; | |
1da177e4 | 151 | local_irq_save(flags); |
41c594ab RB |
152 | mtflags = dvpe(); |
153 | #else /* Not SMTC */ | |
154 | local_irq_save(flags); | |
155 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
156 | |
157 | /* Check if our ASID is of an older version and thus invalid */ | |
158 | if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) | |
159 | get_new_mmu_context(next, cpu); | |
41c594ab RB |
160 | #ifdef CONFIG_MIPS_MT_SMTC |
161 | /* | |
162 | * If the EntryHi ASID being replaced happens to be | |
163 | * the value flagged at ASID recycling time as having | |
164 | * an extended life, clear the bit showing it being | |
165 | * in use by this "CPU", and if that's the last bit, | |
166 | * free up the ASID value for use and flush any old | |
167 | * instances of it from the TLB. | |
168 | */ | |
169 | oldasid = (read_c0_entryhi() & ASID_MASK); | |
170 | if(smtc_live_asid[mytlb][oldasid]) { | |
171 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); | |
172 | if(smtc_live_asid[mytlb][oldasid] == 0) | |
173 | smtc_flush_tlb_asid(oldasid); | |
174 | } | |
175 | /* | |
176 | * Tread softly on EntryHi, and so long as we support | |
177 | * having ASID_MASK smaller than the hardware maximum, | |
178 | * make sure no "soft" bits become "hard"... | |
179 | */ | |
d30cecbc RB |
180 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | |
181 | cpu_asid(cpu, next)); | |
41c594ab RB |
182 | ehb(); /* Make sure it propagates to TCStatus */ |
183 | evpe(mtflags); | |
184 | #else | |
d30cecbc | 185 | write_c0_entryhi(cpu_asid(cpu, next)); |
41c594ab | 186 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 LT |
187 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); |
188 | ||
189 | /* | |
190 | * Mark current->active_mm as not "active" anymore. | |
191 | * We don't want to mislead possible IPI tlb flush routines. | |
192 | */ | |
55b8cab4 RR |
193 | cpumask_clear_cpu(cpu, mm_cpumask(prev)); |
194 | cpumask_set_cpu(cpu, mm_cpumask(next)); | |
1da177e4 LT |
195 | |
196 | local_irq_restore(flags); | |
197 | } | |
198 | ||
199 | /* | |
200 | * Destroy context related info for an mm_struct that is about | |
201 | * to be put to rest. | |
202 | */ | |
203 | static inline void destroy_context(struct mm_struct *mm) | |
204 | { | |
205 | } | |
206 | ||
21a151d8 | 207 | #define deactivate_mm(tsk, mm) do { } while (0) |
1da177e4 LT |
208 | |
209 | /* | |
210 | * After we have set current->mm to a new value, this activates | |
211 | * the context for the new mm so we see the new mappings. | |
212 | */ | |
213 | static inline void | |
214 | activate_mm(struct mm_struct *prev, struct mm_struct *next) | |
215 | { | |
216 | unsigned long flags; | |
217 | unsigned int cpu = smp_processor_id(); | |
218 | ||
41c594ab RB |
219 | #ifdef CONFIG_MIPS_MT_SMTC |
220 | unsigned long oldasid; | |
221 | unsigned long mtflags; | |
222 | int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; | |
223 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
224 | ||
1da177e4 LT |
225 | local_irq_save(flags); |
226 | ||
227 | /* Unconditionally get a new ASID. */ | |
228 | get_new_mmu_context(next, cpu); | |
229 | ||
41c594ab RB |
230 | #ifdef CONFIG_MIPS_MT_SMTC |
231 | /* See comments for similar code above */ | |
232 | mtflags = dvpe(); | |
233 | oldasid = read_c0_entryhi() & ASID_MASK; | |
234 | if(smtc_live_asid[mytlb][oldasid]) { | |
235 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); | |
384740dc RB |
236 | if(smtc_live_asid[mytlb][oldasid] == 0) |
237 | smtc_flush_tlb_asid(oldasid); | |
41c594ab RB |
238 | } |
239 | /* See comments for similar code above */ | |
240 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | | |
70342287 | 241 | cpu_asid(cpu, next)); |
41c594ab RB |
242 | ehb(); /* Make sure it propagates to TCStatus */ |
243 | evpe(mtflags); | |
244 | #else | |
d30cecbc | 245 | write_c0_entryhi(cpu_asid(cpu, next)); |
41c594ab | 246 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 LT |
247 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); |
248 | ||
249 | /* mark mmu ownership change */ | |
55b8cab4 RR |
250 | cpumask_clear_cpu(cpu, mm_cpumask(prev)); |
251 | cpumask_set_cpu(cpu, mm_cpumask(next)); | |
1da177e4 LT |
252 | |
253 | local_irq_restore(flags); | |
254 | } | |
255 | ||
256 | /* | |
257 | * If mm is currently active_mm, we can't really drop it. Instead, | |
258 | * we will get a new one for it. | |
259 | */ | |
260 | static inline void | |
261 | drop_mmu_context(struct mm_struct *mm, unsigned cpu) | |
262 | { | |
263 | unsigned long flags; | |
41c594ab RB |
264 | #ifdef CONFIG_MIPS_MT_SMTC |
265 | unsigned long oldasid; | |
266 | /* Can't use spinlock because called from TLB flush within DVPE */ | |
267 | unsigned int prevvpe; | |
268 | int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; | |
269 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
270 | |
271 | local_irq_save(flags); | |
272 | ||
55b8cab4 | 273 | if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { |
1da177e4 | 274 | get_new_mmu_context(mm, cpu); |
41c594ab RB |
275 | #ifdef CONFIG_MIPS_MT_SMTC |
276 | /* See comments for similar code above */ | |
277 | prevvpe = dvpe(); | |
278 | oldasid = (read_c0_entryhi() & ASID_MASK); | |
6b8aab09 RB |
279 | if (smtc_live_asid[mytlb][oldasid]) { |
280 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); | |
281 | if(smtc_live_asid[mytlb][oldasid] == 0) | |
282 | smtc_flush_tlb_asid(oldasid); | |
41c594ab RB |
283 | } |
284 | /* See comments for similar code above */ | |
285 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | |
286 | | cpu_asid(cpu, mm)); | |
287 | ehb(); /* Make sure it propagates to TCStatus */ | |
288 | evpe(prevvpe); | |
289 | #else /* not CONFIG_MIPS_MT_SMTC */ | |
1da177e4 | 290 | write_c0_entryhi(cpu_asid(cpu, mm)); |
41c594ab | 291 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 LT |
292 | } else { |
293 | /* will get a new context next time */ | |
41c594ab | 294 | #ifndef CONFIG_MIPS_MT_SMTC |
1da177e4 | 295 | cpu_context(cpu, mm) = 0; |
41c594ab RB |
296 | #else /* SMTC */ |
297 | int i; | |
298 | ||
299 | /* SMTC shares the TLB (and ASIDs) across VPEs */ | |
b5eb5511 | 300 | for_each_online_cpu(i) { |
384740dc RB |
301 | if((smtc_status & SMTC_TLB_SHARED) |
302 | || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) | |
41c594ab RB |
303 | cpu_context(i, mm) = 0; |
304 | } | |
305 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 | 306 | } |
1da177e4 LT |
307 | local_irq_restore(flags); |
308 | } | |
309 | ||
310 | #endif /* _ASM_MMU_CONTEXT_H */ |