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1 | /***********************license start*************** |
2 | * Author: Cavium Networks | |
3 | * | |
4 | * Contact: support@caviumnetworks.com | |
5 | * This file is part of the OCTEON SDK | |
6 | * | |
7 | * Copyright (c) 2003-2008 Cavium Networks | |
8 | * | |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this file; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * or visit http://www.gnu.org/licenses/. | |
23 | * | |
24 | * This file may also be available under a different license from Cavium. | |
25 | * Contact Cavium Networks for more information | |
26 | ***********************license end**************************************/ | |
27 | ||
28 | #ifndef __CVMX_H__ | |
29 | #define __CVMX_H__ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/string.h> | |
33 | ||
34 | #include "cvmx-asm.h" | |
35 | #include "cvmx-packet.h" | |
36 | #include "cvmx-sysinfo.h" | |
37 | ||
38 | #include "cvmx-ciu-defs.h" | |
39 | #include "cvmx-gpio-defs.h" | |
40 | #include "cvmx-iob-defs.h" | |
41 | #include "cvmx-ipd-defs.h" | |
42 | #include "cvmx-l2c-defs.h" | |
43 | #include "cvmx-l2d-defs.h" | |
44 | #include "cvmx-l2t-defs.h" | |
45 | #include "cvmx-led-defs.h" | |
46 | #include "cvmx-mio-defs.h" | |
47 | #include "cvmx-pow-defs.h" | |
48 | ||
49 | #include "cvmx-bootinfo.h" | |
50 | #include "cvmx-bootmem.h" | |
51 | #include "cvmx-l2c.h" | |
52 | ||
53 | #ifndef CVMX_ENABLE_DEBUG_PRINTS | |
54 | #define CVMX_ENABLE_DEBUG_PRINTS 1 | |
55 | #endif | |
56 | ||
57 | #if CVMX_ENABLE_DEBUG_PRINTS | |
58 | #define cvmx_dprintf printk | |
59 | #else | |
60 | #define cvmx_dprintf(...) {} | |
61 | #endif | |
62 | ||
63 | #define CVMX_MAX_CORES (16) | |
64 | #define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ | |
65 | #define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */ | |
66 | #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE))) | |
67 | #define CAST64(v) ((long long)(long)(v)) | |
68 | #define CASTPTR(type, v) ((type *)(long)(v)) | |
69 | ||
70 | /* | |
71 | * Returns processor ID, different Linux and simple exec versions | |
72 | * provided in the cvmx-app-init*.c files. | |
73 | */ | |
74 | static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); | |
75 | static inline uint32_t cvmx_get_proc_id(void) | |
76 | { | |
77 | uint32_t id; | |
78 | asm("mfc0 %0, $15,0" : "=r"(id)); | |
79 | return id; | |
80 | } | |
81 | ||
82 | /* turn the variable name into a string */ | |
83 | #define CVMX_TMP_STR(x) CVMX_TMP_STR2(x) | |
84 | #define CVMX_TMP_STR2(x) #x | |
85 | ||
86 | /** | |
87 | * Builds a bit mask given the required size in bits. | |
88 | * | |
89 | * @bits: Number of bits in the mask | |
90 | * Returns The mask | |
91 | */ static inline uint64_t cvmx_build_mask(uint64_t bits) | |
92 | { | |
93 | return ~((~0x0ull) << bits); | |
94 | } | |
95 | ||
96 | /** | |
97 | * Builds a memory address for I/O based on the Major and Sub DID. | |
98 | * | |
99 | * @major_did: 5 bit major did | |
100 | * @sub_did: 3 bit sub did | |
101 | * Returns I/O base address | |
102 | */ | |
103 | static inline uint64_t cvmx_build_io_address(uint64_t major_did, | |
104 | uint64_t sub_did) | |
105 | { | |
106 | return (0x1ull << 48) | (major_did << 43) | (sub_did << 40); | |
107 | } | |
108 | ||
109 | /** | |
110 | * Perform mask and shift to place the supplied value into | |
111 | * the supplied bit rage. | |
112 | * | |
113 | * Example: cvmx_build_bits(39,24,value) | |
114 | * <pre> | |
115 | * 6 5 4 3 3 2 1 | |
116 | * 3 5 7 9 1 3 5 7 0 | |
117 | * +-------+-------+-------+-------+-------+-------+-------+------+ | |
118 | * 000000000000000000000000___________value000000000000000000000000 | |
119 | * </pre> | |
120 | * | |
121 | * @high_bit: Highest bit value can occupy (inclusive) 0-63 | |
122 | * @low_bit: Lowest bit value can occupy inclusive 0-high_bit | |
123 | * @value: Value to use | |
124 | * Returns Value masked and shifted | |
125 | */ | |
126 | static inline uint64_t cvmx_build_bits(uint64_t high_bit, | |
127 | uint64_t low_bit, uint64_t value) | |
128 | { | |
129 | return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit; | |
130 | } | |
131 | ||
132 | enum cvmx_mips_space { | |
133 | CVMX_MIPS_SPACE_XKSEG = 3LL, | |
134 | CVMX_MIPS_SPACE_XKPHYS = 2LL, | |
135 | CVMX_MIPS_SPACE_XSSEG = 1LL, | |
136 | CVMX_MIPS_SPACE_XUSEG = 0LL | |
137 | }; | |
138 | ||
139 | /* These macros for use when using 32 bit pointers. */ | |
140 | #define CVMX_MIPS32_SPACE_KSEG0 1l | |
141 | #define CVMX_ADD_SEG32(segment, add) \ | |
142 | (((int32_t)segment << 31) | (int32_t)(add)) | |
143 | ||
144 | #define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS | |
145 | ||
146 | /* These macros simplify the process of creating common IO addresses */ | |
147 | #define CVMX_ADD_SEG(segment, add) \ | |
148 | ((((uint64_t)segment) << 62) | (add)) | |
149 | #ifndef CVMX_ADD_IO_SEG | |
150 | #define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) | |
151 | #endif | |
152 | ||
153 | /** | |
154 | * Convert a memory pointer (void*) into a hardware compatable | |
155 | * memory address (uint64_t). Octeon hardware widgets don't | |
156 | * understand logical addresses. | |
157 | * | |
158 | * @ptr: C style memory pointer | |
159 | * Returns Hardware physical address | |
160 | */ | |
161 | static inline uint64_t cvmx_ptr_to_phys(void *ptr) | |
162 | { | |
163 | if (sizeof(void *) == 8) { | |
164 | /* | |
165 | * We're running in 64 bit mode. Normally this means | |
166 | * that we can use 40 bits of address space (the | |
167 | * hardware limit). Unfortunately there is one case | |
168 | * were we need to limit this to 30 bits, sign | |
169 | * extended 32 bit. Although these are 64 bits wide, | |
170 | * only 30 bits can be used. | |
171 | */ | |
172 | if ((CAST64(ptr) >> 62) == 3) | |
173 | return CAST64(ptr) & cvmx_build_mask(30); | |
174 | else | |
175 | return CAST64(ptr) & cvmx_build_mask(40); | |
176 | } else { | |
177 | return (long)(ptr) & 0x1fffffff; | |
178 | } | |
179 | } | |
180 | ||
181 | /** | |
182 | * Convert a hardware physical address (uint64_t) into a | |
183 | * memory pointer (void *). | |
184 | * | |
185 | * @physical_address: | |
186 | * Hardware physical address to memory | |
187 | * Returns Pointer to memory | |
188 | */ | |
189 | static inline void *cvmx_phys_to_ptr(uint64_t physical_address) | |
190 | { | |
191 | if (sizeof(void *) == 8) { | |
192 | /* Just set the top bit, avoiding any TLB uglyness */ | |
193 | return CASTPTR(void, | |
194 | CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, | |
195 | physical_address)); | |
196 | } else { | |
197 | return CASTPTR(void, | |
198 | CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, | |
199 | physical_address)); | |
200 | } | |
201 | } | |
202 | ||
203 | /* The following #if controls the definition of the macro | |
204 | CVMX_BUILD_WRITE64. This macro is used to build a store operation to | |
205 | a full 64bit address. With a 64bit ABI, this can be done with a simple | |
206 | pointer access. 32bit ABIs require more complicated assembly */ | |
207 | ||
208 | /* We have a full 64bit ABI. Writing to a 64bit address can be done with | |
209 | a simple volatile pointer */ | |
210 | #define CVMX_BUILD_WRITE64(TYPE, ST) \ | |
211 | static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ | |
212 | { \ | |
213 | *CASTPTR(volatile TYPE##_t, addr) = val; \ | |
214 | } | |
215 | ||
216 | ||
217 | /* The following #if controls the definition of the macro | |
218 | CVMX_BUILD_READ64. This macro is used to build a load operation from | |
219 | a full 64bit address. With a 64bit ABI, this can be done with a simple | |
220 | pointer access. 32bit ABIs require more complicated assembly */ | |
221 | ||
222 | /* We have a full 64bit ABI. Writing to a 64bit address can be done with | |
223 | a simple volatile pointer */ | |
224 | #define CVMX_BUILD_READ64(TYPE, LT) \ | |
225 | static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \ | |
226 | { \ | |
227 | return *CASTPTR(volatile TYPE##_t, addr); \ | |
228 | } | |
229 | ||
230 | ||
231 | /* The following defines 8 functions for writing to a 64bit address. Each | |
232 | takes two arguments, the address and the value to write. | |
233 | cvmx_write64_int64 cvmx_write64_uint64 | |
234 | cvmx_write64_int32 cvmx_write64_uint32 | |
235 | cvmx_write64_int16 cvmx_write64_uint16 | |
236 | cvmx_write64_int8 cvmx_write64_uint8 */ | |
237 | CVMX_BUILD_WRITE64(int64, "sd"); | |
238 | CVMX_BUILD_WRITE64(int32, "sw"); | |
239 | CVMX_BUILD_WRITE64(int16, "sh"); | |
240 | CVMX_BUILD_WRITE64(int8, "sb"); | |
241 | CVMX_BUILD_WRITE64(uint64, "sd"); | |
242 | CVMX_BUILD_WRITE64(uint32, "sw"); | |
243 | CVMX_BUILD_WRITE64(uint16, "sh"); | |
244 | CVMX_BUILD_WRITE64(uint8, "sb"); | |
245 | #define cvmx_write64 cvmx_write64_uint64 | |
246 | ||
247 | /* The following defines 8 functions for reading from a 64bit address. Each | |
248 | takes the address as the only argument | |
249 | cvmx_read64_int64 cvmx_read64_uint64 | |
250 | cvmx_read64_int32 cvmx_read64_uint32 | |
251 | cvmx_read64_int16 cvmx_read64_uint16 | |
252 | cvmx_read64_int8 cvmx_read64_uint8 */ | |
253 | CVMX_BUILD_READ64(int64, "ld"); | |
254 | CVMX_BUILD_READ64(int32, "lw"); | |
255 | CVMX_BUILD_READ64(int16, "lh"); | |
256 | CVMX_BUILD_READ64(int8, "lb"); | |
257 | CVMX_BUILD_READ64(uint64, "ld"); | |
258 | CVMX_BUILD_READ64(uint32, "lw"); | |
259 | CVMX_BUILD_READ64(uint16, "lhu"); | |
260 | CVMX_BUILD_READ64(uint8, "lbu"); | |
261 | #define cvmx_read64 cvmx_read64_uint64 | |
262 | ||
263 | ||
264 | static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) | |
265 | { | |
266 | cvmx_write64(csr_addr, val); | |
267 | ||
268 | /* | |
269 | * Perform an immediate read after every write to an RSL | |
270 | * register to force the write to complete. It doesn't matter | |
271 | * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT | |
272 | * because it is fast and harmless. | |
273 | */ | |
26084411 | 274 | if (((csr_addr >> 40) & 0x7ffff) == (0x118)) |
58f07778 DD |
275 | cvmx_read64(CVMX_MIO_BOOT_BIST_STAT); |
276 | } | |
277 | ||
278 | static inline void cvmx_write_io(uint64_t io_addr, uint64_t val) | |
279 | { | |
280 | cvmx_write64(io_addr, val); | |
281 | ||
282 | } | |
283 | ||
284 | static inline uint64_t cvmx_read_csr(uint64_t csr_addr) | |
285 | { | |
286 | uint64_t val = cvmx_read64(csr_addr); | |
287 | return val; | |
288 | } | |
289 | ||
290 | ||
291 | static inline void cvmx_send_single(uint64_t data) | |
292 | { | |
293 | const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull; | |
294 | cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data); | |
295 | } | |
296 | ||
297 | static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr) | |
298 | { | |
299 | union { | |
300 | uint64_t u64; | |
301 | struct { | |
302 | uint64_t scraddr:8; | |
303 | uint64_t len:8; | |
304 | uint64_t addr:48; | |
305 | } s; | |
306 | } addr; | |
307 | addr.u64 = csr_addr; | |
308 | addr.s.scraddr = scraddr >> 3; | |
309 | addr.s.len = 1; | |
310 | cvmx_send_single(addr.u64); | |
311 | } | |
312 | ||
313 | /* Return true if Octeon is CN38XX pass 1 */ | |
314 | static inline int cvmx_octeon_is_pass1(void) | |
315 | { | |
316 | #if OCTEON_IS_COMMON_BINARY() | |
317 | return 0; /* Pass 1 isn't supported for common binaries */ | |
318 | #else | |
319 | /* Now that we know we're built for a specific model, only check CN38XX */ | |
320 | #if OCTEON_IS_MODEL(OCTEON_CN38XX) | |
321 | return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1; | |
322 | #else | |
323 | return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */ | |
324 | #endif | |
325 | #endif | |
326 | } | |
327 | ||
328 | static inline unsigned int cvmx_get_core_num(void) | |
329 | { | |
330 | unsigned int core_num; | |
331 | CVMX_RDHWRNV(core_num, 0); | |
332 | return core_num; | |
333 | } | |
334 | ||
335 | /** | |
336 | * Returns the number of bits set in the provided value. | |
337 | * Simple wrapper for POP instruction. | |
338 | * | |
339 | * @val: 32 bit value to count set bits in | |
340 | * | |
341 | * Returns Number of bits set | |
342 | */ | |
343 | static inline uint32_t cvmx_pop(uint32_t val) | |
344 | { | |
345 | uint32_t pop; | |
346 | CVMX_POP(pop, val); | |
347 | return pop; | |
348 | } | |
349 | ||
350 | /** | |
351 | * Returns the number of bits set in the provided value. | |
352 | * Simple wrapper for DPOP instruction. | |
353 | * | |
354 | * @val: 64 bit value to count set bits in | |
355 | * | |
356 | * Returns Number of bits set | |
357 | */ | |
358 | static inline int cvmx_dpop(uint64_t val) | |
359 | { | |
360 | int pop; | |
361 | CVMX_DPOP(pop, val); | |
362 | return pop; | |
363 | } | |
364 | ||
365 | /** | |
366 | * Provide current cycle counter as a return value | |
367 | * | |
368 | * Returns current cycle counter | |
369 | */ | |
370 | ||
371 | static inline uint64_t cvmx_get_cycle(void) | |
372 | { | |
373 | uint64_t cycle; | |
374 | CVMX_RDHWR(cycle, 31); | |
375 | return cycle; | |
376 | } | |
377 | ||
e8635b48 DD |
378 | /** |
379 | * Wait for the specified number of cycle | |
380 | * | |
381 | */ | |
382 | static inline void cvmx_wait(uint64_t cycles) | |
383 | { | |
384 | uint64_t done = cvmx_get_cycle() + cycles; | |
385 | ||
386 | while (cvmx_get_cycle() < done) | |
387 | ; /* Spin */ | |
388 | } | |
389 | ||
58f07778 DD |
390 | /** |
391 | * Reads a chip global cycle counter. This counts CPU cycles since | |
392 | * chip reset. The counter is 64 bit. | |
393 | * This register does not exist on CN38XX pass 1 silicion | |
394 | * | |
395 | * Returns Global chip cycle count since chip reset. | |
396 | */ | |
397 | static inline uint64_t cvmx_get_cycle_global(void) | |
398 | { | |
399 | if (cvmx_octeon_is_pass1()) | |
400 | return 0; | |
401 | else | |
402 | return cvmx_read64(CVMX_IPD_CLK_COUNT); | |
403 | } | |
404 | ||
405 | /** | |
406 | * This macro spins on a field waiting for it to reach a value. It | |
407 | * is common in code to need to wait for a specific field in a CSR | |
408 | * to match a specific value. Conceptually this macro expands to: | |
409 | * | |
410 | * 1) read csr at "address" with a csr typedef of "type" | |
411 | * 2) Check if ("type".s."field" "op" "value") | |
412 | * 3) If #2 isn't true loop to #1 unless too much time has passed. | |
413 | */ | |
414 | #define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\ | |
415 | ( \ | |
416 | { \ | |
417 | int result; \ | |
418 | do { \ | |
419 | uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \ | |
420 | cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \ | |
421 | type c; \ | |
422 | while (1) { \ | |
423 | c.u64 = cvmx_read_csr(address); \ | |
424 | if ((c.s.field) op(value)) { \ | |
425 | result = 0; \ | |
426 | break; \ | |
427 | } else if (cvmx_get_cycle() > done) { \ | |
428 | result = -1; \ | |
429 | break; \ | |
430 | } else \ | |
431 | cvmx_wait(100); \ | |
432 | } \ | |
433 | } while (0); \ | |
434 | result; \ | |
435 | }) | |
436 | ||
437 | /***************************************************************************/ | |
438 | ||
439 | static inline void cvmx_reset_octeon(void) | |
440 | { | |
441 | union cvmx_ciu_soft_rst ciu_soft_rst; | |
442 | ciu_soft_rst.u64 = 0; | |
443 | ciu_soft_rst.s.soft_rst = 1; | |
444 | cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64); | |
445 | } | |
446 | ||
447 | /* Return the number of cores available in the chip */ | |
448 | static inline uint32_t cvmx_octeon_num_cores(void) | |
449 | { | |
450 | uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff; | |
451 | return cvmx_pop(ciu_fuse); | |
452 | } | |
453 | ||
454 | /** | |
455 | * Read a byte of fuse data | |
456 | * @byte_addr: address to read | |
457 | * | |
458 | * Returns fuse value: 0 or 1 | |
459 | */ | |
460 | static uint8_t cvmx_fuse_read_byte(int byte_addr) | |
461 | { | |
462 | union cvmx_mio_fus_rcmd read_cmd; | |
463 | ||
464 | read_cmd.u64 = 0; | |
465 | read_cmd.s.addr = byte_addr; | |
466 | read_cmd.s.pend = 1; | |
467 | cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64); | |
468 | while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD)) | |
469 | && read_cmd.s.pend) | |
470 | ; | |
471 | return read_cmd.s.dat; | |
472 | } | |
473 | ||
474 | /** | |
475 | * Read a single fuse bit | |
476 | * | |
477 | * @fuse: Fuse number (0-1024) | |
478 | * | |
479 | * Returns fuse value: 0 or 1 | |
480 | */ | |
481 | static inline int cvmx_fuse_read(int fuse) | |
482 | { | |
483 | return (cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1; | |
484 | } | |
485 | ||
486 | static inline int cvmx_octeon_model_CN36XX(void) | |
487 | { | |
488 | return OCTEON_IS_MODEL(OCTEON_CN38XX) | |
489 | && !cvmx_octeon_is_pass1() | |
490 | && cvmx_fuse_read(264); | |
491 | } | |
492 | ||
493 | static inline int cvmx_octeon_zip_present(void) | |
494 | { | |
495 | return octeon_has_feature(OCTEON_FEATURE_ZIP); | |
496 | } | |
497 | ||
498 | static inline int cvmx_octeon_dfa_present(void) | |
499 | { | |
500 | if (!OCTEON_IS_MODEL(OCTEON_CN38XX) | |
501 | && !OCTEON_IS_MODEL(OCTEON_CN31XX) | |
502 | && !OCTEON_IS_MODEL(OCTEON_CN58XX)) | |
503 | return 0; | |
504 | else if (OCTEON_IS_MODEL(OCTEON_CN3020)) | |
505 | return 0; | |
506 | else if (cvmx_octeon_is_pass1()) | |
507 | return 1; | |
508 | else | |
509 | return !cvmx_fuse_read(120); | |
510 | } | |
511 | ||
512 | static inline int cvmx_octeon_crypto_present(void) | |
513 | { | |
514 | return octeon_has_feature(OCTEON_FEATURE_CRYPTO); | |
515 | } | |
516 | ||
517 | #endif /* __CVMX_H__ */ |