[deliverable/linux.git] / arch / mips / include / asm / octeon / octeon.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004-2008 Cavium Networks
 */
#ifndef __ASM_OCTEON_OCTEON_H
#define __ASM_OCTEON_OCTEON_H

#include <asm/octeon/cvmx.h>

extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
						uint64_t alignment,
						uint64_t min_addr,
						uint64_t max_addr,
						int do_locking);
extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
				  int do_locking);
extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
					uint64_t min_addr, uint64_t max_addr,
					int do_locking);
extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
					char *name);
extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
					      uint64_t max_addr, uint64_t align,
					      char *name);
extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
						char *name);
extern int octeon_bootmem_free_named(char *name);
extern void octeon_bootmem_lock(void);
extern void octeon_bootmem_unlock(void);

extern int octeon_is_simulation(void);
extern int octeon_is_pci_host(void);
extern int octeon_usb_is_ref_clk(void);
extern uint64_t octeon_get_clock_rate(void);
extern u64 octeon_get_io_clock_rate(void);
extern const char *octeon_board_type_string(void);
extern const char *octeon_get_pci_interrupts(void);
extern int octeon_get_southbridge_interrupt(void);
extern int octeon_get_boot_coremask(void);
extern int octeon_get_boot_num_arguments(void);
extern const char *octeon_get_boot_argument(int arg);
extern void octeon_hal_setup_reserved32(void);
extern void octeon_user_io_init(void);

extern void octeon_init_cvmcount(void);
extern void octeon_setup_delays(void);
extern void octeon_io_clk_delay(unsigned long);

#define OCTEON_ARGV_MAX_ARGS	64
#define OCTOEN_SERIAL_LEN	20

struct octeon_boot_descriptor {
	/* Start of block referenced by assembly code - do not change! */
	uint32_t desc_version;
	uint32_t desc_size;
	uint64_t stack_top;
	uint64_t heap_base;
	uint64_t heap_end;
	/* Only used by bootloader */
	uint64_t entry_point;
	uint64_t desc_vaddr;
	/* End of This block referenced by assembly code - do not change! */
	uint32_t exception_base_addr;
	uint32_t stack_size;
	uint32_t heap_size;
	/* Argc count for application. */
	uint32_t argc;
	uint32_t argv[OCTEON_ARGV_MAX_ARGS];

#define	 BOOT_FLAG_INIT_CORE		(1 << 0)
#define	 OCTEON_BL_FLAG_DEBUG		(1 << 1)
#define	 OCTEON_BL_FLAG_NO_MAGIC	(1 << 2)
	/* If set, use uart1 for console */
#define	 OCTEON_BL_FLAG_CONSOLE_UART1	(1 << 3)
	/* If set, use PCI console */
#define	 OCTEON_BL_FLAG_CONSOLE_PCI	(1 << 4)
	/* Call exit on break on serial port */
#define	 OCTEON_BL_FLAG_BREAK		(1 << 5)

	uint32_t flags;
	uint32_t core_mask;
	/* DRAM size in megabyes. */
	uint32_t dram_size;
	/* physical address of free memory descriptor block. */
	uint32_t phy_mem_desc_addr;
	/* used to pass flags from app to debugger. */
	uint32_t debugger_flags_base_addr;
	/* CPU clock speed, in hz. */
	uint32_t eclock_hz;
	/* DRAM clock speed, in hz. */
	uint32_t dclock_hz;
	/* SPI4 clock in hz. */
	uint32_t spi_clock_hz;
	uint16_t board_type;
	uint8_t board_rev_major;
	uint8_t board_rev_minor;
	uint16_t chip_type;
	uint8_t chip_rev_major;
	uint8_t chip_rev_minor;
	char board_serial_number[OCTOEN_SERIAL_LEN];
	uint8_t mac_addr_base[6];
	uint8_t mac_addr_count;
	uint64_t cvmx_desc_vaddr;
};

union octeon_cvmemctl {
	uint64_t u64;
	struct {
		/* RO 1 = BIST fail, 0 = BIST pass */
		uint64_t tlbbist:1;
		/* RO 1 = BIST fail, 0 = BIST pass */
		uint64_t l1cbist:1;
		/* RO 1 = BIST fail, 0 = BIST pass */
		uint64_t l1dbist:1;
		/* RO 1 = BIST fail, 0 = BIST pass */
		uint64_t dcmbist:1;
		/* RO 1 = BIST fail, 0 = BIST pass */
		uint64_t ptgbist:1;
		/* RO 1 = BIST fail, 0 = BIST pass */
		uint64_t wbfbist:1;
		/* Reserved */
		uint64_t reserved:22;
		/* R/W If set, marked write-buffer entries time out
		 * the same as as other entries; if clear, marked
		 * write-buffer entries use the maximum timeout. */
		uint64_t dismarkwblongto:1;
		/* R/W If set, a merged store does not clear the
		 * write-buffer entry timeout state. */
		uint64_t dismrgclrwbto:1;
		/* R/W Two bits that are the MSBs of the resultant
		 * CVMSEG LM word location for an IOBDMA. The other 8
		 * bits come from the SCRADDR field of the IOBDMA. */
		uint64_t iobdmascrmsb:2;
		/* R/W If set, SYNCWS and SYNCS only order marked
		 * stores; if clear, SYNCWS and SYNCS only order
		 * unmarked stores. SYNCWSMARKED has no effect when
		 * DISSYNCWS is set. */
		uint64_t syncwsmarked:1;
		/* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
		 * SYNC. */
		uint64_t dissyncws:1;
		/* R/W If set, no stall happens on write buffer
		 * full. */
		uint64_t diswbfst:1;
		/* R/W If set (and SX set), supervisor-level
		 * loads/stores can use XKPHYS addresses with
		 * VA<48>==0 */
		uint64_t xkmemenas:1;
		/* R/W If set (and UX set), user-level loads/stores
		 * can use XKPHYS addresses with VA<48>==0 */
		uint64_t xkmemenau:1;
		/* R/W If set (and SX set), supervisor-level
		 * loads/stores can use XKPHYS addresses with
		 * VA<48>==1 */
		uint64_t xkioenas:1;
		/* R/W If set (and UX set), user-level loads/stores
		 * can use XKPHYS addresses with VA<48>==1 */
		uint64_t xkioenau:1;
		/* R/W If set, all stores act as SYNCW (NOMERGE must
		 * be set when this is set) RW, reset to 0. */
		uint64_t allsyncw:1;
		/* R/W If set, no stores merge, and all stores reach
		 * the coherent bus in order. */
		uint64_t nomerge:1;
		/* R/W Selects the bit in the counter used for DID
		 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
		 * 214. Actual time-out is between 1x and 2x this
		 * interval. For example, with DIDTTO=3, expiration
		 * interval is between 16K and 32K. */
		uint64_t didtto:2;
		/* R/W If set, the (mem) CSR clock never turns off. */
		uint64_t csrckalwys:1;
		/* R/W If set, mclk never turns off. */
		uint64_t mclkalwys:1;
		/* R/W Selects the bit in the counter used for write
		 * buffer flush time-outs (WBFLT+11) is the bit
		 * position in an internal counter used to determine
		 * expiration. The write buffer expires between 1x and
		 * 2x this interval. For example, with WBFLT = 0, a
		 * write buffer expires between 2K and 4K cycles after
		 * the write buffer entry is allocated. */
		uint64_t wbfltime:3;
		/* R/W If set, do not put Istream in the L2 cache. */
		uint64_t istrnol2:1;
		/* R/W The write buffer threshold. */
		uint64_t wbthresh:4;
		/* Reserved */
		uint64_t reserved2:2;
		/* R/W If set, CVMSEG is available for loads/stores in
		 * kernel/debug mode. */
		uint64_t cvmsegenak:1;
		/* R/W If set, CVMSEG is available for loads/stores in
		 * supervisor mode. */
		uint64_t cvmsegenas:1;
		/* R/W If set, CVMSEG is available for loads/stores in
		 * user mode. */
		uint64_t cvmsegenau:1;
		/* R/W Size of local memory in cache blocks, 54 (6912
		 * bytes) is max legal value. */
		uint64_t lmemsz:6;
	} s;
};

extern void octeon_write_lcd(const char *s);
extern void octeon_check_cpu_bist(void);
extern int octeon_get_boot_uart(void);

struct uart_port;
extern unsigned int octeon_serial_in(struct uart_port *, int);
extern void octeon_serial_out(struct uart_port *, int, int);

/**
 * Write a 32bit value to the Octeon NPI register space
 *
 * @address: Address to write to
 * @val:     Value to write
 */
static inline void octeon_npi_write32(uint64_t address, uint32_t val)
{
	cvmx_write64_uint32(address ^ 4, val);
	cvmx_read64_uint32(address ^ 4);
}


/**
 * Read a 32bit value from the Octeon NPI register space
 *
 * @address: Address to read
 * Returns The result
 */
static inline uint32_t octeon_npi_read32(uint64_t address)
{
	return cvmx_read64_uint32(address ^ 4);
}

extern struct cvmx_bootinfo *octeon_bootinfo;

extern uint64_t octeon_bootloader_entry_addr;

extern void (*octeon_irq_setup_secondary)(void);

typedef void (*octeon_irq_ip4_handler_t)(void);
void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);

extern void octeon_fixup_irqs(void);

#endif /* __ASM_OCTEON_OCTEON_H */
Commit	Line	Data
5b3b1688 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2004-2008 Cavium Networks
	7	*/
	8	#ifndef __ASM_OCTEON_OCTEON_H
	9	#define __ASM_OCTEON_OCTEON_H
	10
a1ce3928	11	#include <asm/octeon/cvmx.h>
5b3b1688 DD	12
	13	extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
	14	uint64_t alignment,
	15	uint64_t min_addr,
	16	uint64_t max_addr,
	17	int do_locking);
	18	extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
	19	int do_locking);
	20	extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
	21	uint64_t min_addr, uint64_t max_addr,
	22	int do_locking);
	23	extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
	24	char *name);
	25	extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
	26	uint64_t max_addr, uint64_t align,
	27	char *name);
	28	extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
	29	char *name);
	30	extern int octeon_bootmem_free_named(char *name);
	31	extern void octeon_bootmem_lock(void);
	32	extern void octeon_bootmem_unlock(void);
	33
	34	extern int octeon_is_simulation(void);
	35	extern int octeon_is_pci_host(void);
	36	extern int octeon_usb_is_ref_clk(void);
	37	extern uint64_t octeon_get_clock_rate(void);
e195aa30	38	extern u64 octeon_get_io_clock_rate(void);
5b3b1688 DD	39	extern const char *octeon_board_type_string(void);
	40	extern const char *octeon_get_pci_interrupts(void);
	41	extern int octeon_get_southbridge_interrupt(void);
	42	extern int octeon_get_boot_coremask(void);
	43	extern int octeon_get_boot_num_arguments(void);
	44	extern const char *octeon_get_boot_argument(int arg);
	45	extern void octeon_hal_setup_reserved32(void);
	46	extern void octeon_user_io_init(void);
5b3b1688 DD	47
5b3b1688 DD	48	extern void octeon_init_cvmcount(void);
ca148125	49	extern void octeon_setup_delays(void);
70a26a21	50	extern void octeon_io_clk_delay(unsigned long);
5b3b1688 DD	51
	52	#define OCTEON_ARGV_MAX_ARGS 64
	53	#define OCTOEN_SERIAL_LEN 20
	54
	55	struct octeon_boot_descriptor {
	56	/* Start of block referenced by assembly code - do not change! */
	57	uint32_t desc_version;
	58	uint32_t desc_size;
	59	uint64_t stack_top;
	60	uint64_t heap_base;
	61	uint64_t heap_end;
	62	/* Only used by bootloader */
	63	uint64_t entry_point;
	64	uint64_t desc_vaddr;
	65	/* End of This block referenced by assembly code - do not change! */
	66	uint32_t exception_base_addr;
	67	uint32_t stack_size;
	68	uint32_t heap_size;
	69	/* Argc count for application. */
	70	uint32_t argc;
	71	uint32_t argv[OCTEON_ARGV_MAX_ARGS];
	72
70342287 RB	73	#define BOOT_FLAG_INIT_CORE (1 << 0)
	74	#define OCTEON_BL_FLAG_DEBUG (1 << 1)
	75	#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
5b3b1688	76	/* If set, use uart1 for console */
70342287	77	#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
5b3b1688	78	/* If set, use PCI console */
70342287	79	#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
5b3b1688	80	/* Call exit on break on serial port */
70342287	81	#define OCTEON_BL_FLAG_BREAK (1 << 5)
5b3b1688 DD	82
	83	uint32_t flags;
	84	uint32_t core_mask;
	85	/* DRAM size in megabyes. */
	86	uint32_t dram_size;
	87	/* physical address of free memory descriptor block. */
	88	uint32_t phy_mem_desc_addr;
	89	/* used to pass flags from app to debugger. */
	90	uint32_t debugger_flags_base_addr;
	91	/* CPU clock speed, in hz. */
	92	uint32_t eclock_hz;
	93	/* DRAM clock speed, in hz. */
	94	uint32_t dclock_hz;
	95	/* SPI4 clock in hz. */
	96	uint32_t spi_clock_hz;
	97	uint16_t board_type;
	98	uint8_t board_rev_major;
	99	uint8_t board_rev_minor;
	100	uint16_t chip_type;
	101	uint8_t chip_rev_major;
	102	uint8_t chip_rev_minor;
	103	char board_serial_number[OCTOEN_SERIAL_LEN];
	104	uint8_t mac_addr_base[6];
	105	uint8_t mac_addr_count;
	106	uint64_t cvmx_desc_vaddr;
	107	};
	108
	109	union octeon_cvmemctl {
	110	uint64_t u64;
	111	struct {
	112	/* RO 1 = BIST fail, 0 = BIST pass */
	113	uint64_t tlbbist:1;
	114	/* RO 1 = BIST fail, 0 = BIST pass */
	115	uint64_t l1cbist:1;
	116	/* RO 1 = BIST fail, 0 = BIST pass */
	117	uint64_t l1dbist:1;
	118	/* RO 1 = BIST fail, 0 = BIST pass */
	119	uint64_t dcmbist:1;
	120	/* RO 1 = BIST fail, 0 = BIST pass */
	121	uint64_t ptgbist:1;
	122	/* RO 1 = BIST fail, 0 = BIST pass */
	123	uint64_t wbfbist:1;
	124	/* Reserved */
	125	uint64_t reserved:22;
	126	/* R/W If set, marked write-buffer entries time out
	127	* the same as as other entries; if clear, marked
	128	* write-buffer entries use the maximum timeout. */
	129	uint64_t dismarkwblongto:1;
	130	/* R/W If set, a merged store does not clear the
	131	* write-buffer entry timeout state. */
	132	uint64_t dismrgclrwbto:1;
	133	/* R/W Two bits that are the MSBs of the resultant
	134	* CVMSEG LM word location for an IOBDMA. The other 8
	135	* bits come from the SCRADDR field of the IOBDMA. */
	136	uint64_t iobdmascrmsb:2;
	137	/* R/W If set, SYNCWS and SYNCS only order marked
	138	* stores; if clear, SYNCWS and SYNCS only order
	139	* unmarked stores. SYNCWSMARKED has no effect when
	140	* DISSYNCWS is set. */
	141	uint64_t syncwsmarked:1;
	142	/* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
	143	* SYNC. */
	144	uint64_t dissyncws:1;
	145	/* R/W If set, no stall happens on write buffer
146	* full. */
147	uint64_t diswbfst:1;
148	/* R/W If set (and SX set), supervisor-level
149	* loads/stores can use XKPHYS addresses with
150	* VA<48>==0 */
151	uint64_t xkmemenas:1;
152	/* R/W If set (and UX set), user-level loads/stores
153	* can use XKPHYS addresses with VA<48>==0 */
154	uint64_t xkmemenau:1;
155	/* R/W If set (and SX set), supervisor-level
156	* loads/stores can use XKPHYS addresses with
157	* VA<48>==1 */
158	uint64_t xkioenas:1;
159	/* R/W If set (and UX set), user-level loads/stores
160	* can use XKPHYS addresses with VA<48>==1 */
161	uint64_t xkioenau:1;
162	/* R/W If set, all stores act as SYNCW (NOMERGE must
163	* be set when this is set) RW, reset to 0. */
164	uint64_t allsyncw:1;
165	/* R/W If set, no stores merge, and all stores reach
166	* the coherent bus in order. */
167	uint64_t nomerge:1;
168	/* R/W Selects the bit in the counter used for DID
169	* time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
170	* 214. Actual time-out is between 1x and 2x this
171	* interval. For example, with DIDTTO=3, expiration
172	* interval is between 16K and 32K. */
173	uint64_t didtto:2;
174	/* R/W If set, the (mem) CSR clock never turns off. */
175	uint64_t csrckalwys:1;
176	/* R/W If set, mclk never turns off. */
177	uint64_t mclkalwys:1;
178	/* R/W Selects the bit in the counter used for write
179	* buffer flush time-outs (WBFLT+11) is the bit
180	* position in an internal counter used to determine
181	* expiration. The write buffer expires between 1x and
182	* 2x this interval. For example, with WBFLT = 0, a
183	* write buffer expires between 2K and 4K cycles after
184	* the write buffer entry is allocated. */
185	uint64_t wbfltime:3;
186	/* R/W If set, do not put Istream in the L2 cache. */
187	uint64_t istrnol2:1;
188	/* R/W The write buffer threshold. */
189	uint64_t wbthresh:4;
190	/* Reserved */
191	uint64_t reserved2:2;
192	/* R/W If set, CVMSEG is available for loads/stores in
193	* kernel/debug mode. */
194	uint64_t cvmsegenak:1;
195	/* R/W If set, CVMSEG is available for loads/stores in
196	* supervisor mode. */
197	uint64_t cvmsegenas:1;
198	/* R/W If set, CVMSEG is available for loads/stores in
199	* user mode. */
200	uint64_t cvmsegenau:1;
201	/* R/W Size of local memory in cache blocks, 54 (6912
202	* bytes) is max legal value. */
203	uint64_t lmemsz:6;
204	} s;
205	};
206
5b3b1688 DD	207	extern void octeon_write_lcd(const char *s);
5b3b1688 DD	208	extern void octeon_check_cpu_bist(void);
5b3b1688 DD	209	extern int octeon_get_boot_uart(void);
	210
	211	struct uart_port;
	212	extern unsigned int octeon_serial_in(struct uart_port *, int);
	213	extern void octeon_serial_out(struct uart_port *, int, int);
	214
	215	/**
	216	* Write a 32bit value to the Octeon NPI register space
	217	*
	218	* @address: Address to write to
	219	* @val: Value to write
	220	*/
	221	static inline void octeon_npi_write32(uint64_t address, uint32_t val)
	222	{
	223	cvmx_write64_uint32(address ^ 4, val);
	224	cvmx_read64_uint32(address ^ 4);
	225	}
	226
	227
	228	/**
	229	* Read a 32bit value from the Octeon NPI register space
	230	*
	231	* @address: Address to read
	232	* Returns The result
	233	*/
	234	static inline uint32_t octeon_npi_read32(uint64_t address)
	235	{
	236	return cvmx_read64_uint32(address ^ 4);
	237	}
	238
e8635b48 DD	239	extern struct cvmx_bootinfo *octeon_bootinfo;
e8635b48 DD	240
babba4f1 DD	241	extern uint64_t octeon_bootloader_entry_addr;
babba4f1 DD	242
0c326387 DD	243	extern void (*octeon_irq_setup_secondary)(void);
0c326387 DD	244
88fd8589 DD	245	typedef void (*octeon_irq_ip4_handler_t)(void);
	246	void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
	247
17efb59a RB	248	extern void octeon_fixup_irqs(void);
17efb59a RB	249
5b3b1688	250	#endif /* __ASM_OCTEON_OCTEON_H */