[deliverable/linux.git] / arch / mips / include / asm / pgtable-32.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
 */
#ifndef _ASM_PGTABLE_32_H
#define _ASM_PGTABLE_32_H

#include <asm/addrspace.h>
#include <asm/page.h>

#include <linux/linkage.h>
#include <asm/cachectl.h>
#include <asm/fixmap.h>

#include <asm-generic/pgtable-nopmd.h>

extern int temp_tlb_entry __cpuinitdata;

/*
 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
 *	starting at the top and working down. This is for populating the
 *	TLB before trap_init() puts the TLB miss handler in place. It
 *	should be used only for entries matching the actual page tables,
 *	to prevent inconsistencies.
 */
extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
			       unsigned long entryhi, unsigned long pagemask);

/*
 * Basically we have the same two-level (which is the logical three level
 * Linux page table layout folded) page tables as the i386.  Some day
 * when we have proper page coloring support we can have a 1% quicker
 * tlb refill handling mechanism, but for now it is a bit slower but
 * works even with the cache aliasing problem the R4k and above have.
 */

/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define PGDIR_SHIFT	(2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * Entries per page directory level: we use two-level, so
 * we don't really have any PUD/PMD directory physically.
 */
#define __PGD_ORDER	(32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
#define PGD_ORDER	(__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
#define PUD_ORDER	aieeee_attempt_to_allocate_pud
#define PMD_ORDER	1
#define PTE_ORDER	0

#define PTRS_PER_PGD	(USER_PTRS_PER_PGD * 2)
#define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))

#define USER_PTRS_PER_PGD	(0x80000000UL/PGDIR_SIZE)
#define FIRST_USER_ADDRESS	0

#define VMALLOC_START	  MAP_BASE

#define PKMAP_BASE		(0xfe000000UL)

#ifdef CONFIG_HIGHMEM
# define VMALLOC_END	(PKMAP_BASE-2*PAGE_SIZE)
#else
# define VMALLOC_END	(FIXADDR_START-2*PAGE_SIZE)
#endif

#ifdef CONFIG_PHYS_ADDR_T_64BIT
#define pte_ERROR(e) \
	printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
#else
#define pte_ERROR(e) \
	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
#endif
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))

extern void load_pgd(unsigned long pg_dir);

extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];

/*
 * Empty pgd/pmd entries point to the invalid_pte_table.
 */
static inline int pmd_none(pmd_t pmd)
{
	return pmd_val(pmd) == (unsigned long) invalid_pte_table;
}

#define pmd_bad(pmd)		(pmd_val(pmd) & ~PAGE_MASK)

static inline int pmd_present(pmd_t pmd)
{
	return pmd_val(pmd) != (unsigned long) invalid_pte_table;
}

static inline void pmd_clear(pmd_t *pmdp)
{
	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
}

#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
#define pte_page(x)		pfn_to_page(pte_pfn(x))
#define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))
static inline pte_t
pfn_pte(unsigned long pfn, pgprot_t prot)
{
	pte_t pte;
	pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
	pte.pte_low = pgprot_val(prot);
	return pte;
}

#else

#define pte_page(x)		pfn_to_page(pte_pfn(x))

#ifdef CONFIG_CPU_VR41XX
#define pte_pfn(x)		((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
#define pfn_pte(pfn, prot)	__pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
#else
#define pte_pfn(x)		((unsigned long)((x).pte >> _PFN_SHIFT))
#define pfn_pte(pfn, prot)	__pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
#endif
#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */

#define __pgd_offset(address)	pgd_index(address)
#define __pud_offset(address)	(((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
#define __pmd_offset(address)	(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

#define pgd_index(address)	(((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))

/* to find an entry in a page-table-directory */
#define pgd_offset(mm, addr)	((mm)->pgd + pgd_index(addr))

/* Find an entry in the third-level page table.. */
#define __pte_offset(address)						\
	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset(dir, address)					\
	((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
#define pte_offset_kernel(dir, address)					\
	((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))

#define pte_offset_map(dir, address)					\
	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define pte_unmap(pte) ((void)(pte))

#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

/* Swap entries must have VALID bit cleared. */
#define __swp_type(x)			(((x).val >> 10) & 0x1f)
#define __swp_offset(x)			((x).val >> 15)
#define __swp_entry(type,offset)	((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)		((pte_t) { (x).val })

/*
 * Encode and decode a nonlinear file mapping entry
 */
#define pte_to_pgoff(_pte)		((((_pte).pte >> 1 ) & 0x07) | \
					 (((_pte).pte >> 2 ) & 0x38) | \
					 (((_pte).pte >> 10) <<	 6 ))

#define pgoff_to_pte(off)		((pte_t) { (((off) & 0x07) << 1 ) | \
						   (((off) & 0x38) << 2 ) | \
						   (((off) >>  6 ) << 10) | \
						   _PAGE_FILE })

/*
 * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
 */
#define PTE_FILE_MAX_BITS		28
#else

#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)

/* Swap entries must have VALID and GLOBAL bits cleared. */
#define __swp_type(x)			(((x).val >> 2) & 0x1f)
#define __swp_offset(x)			 ((x).val >> 7)
#define __swp_entry(type,offset)	((swp_entry_t)	{ ((type) << 2) | ((offset) << 7) })
#define __pte_to_swp_entry(pte)		((swp_entry_t) { (pte).pte_high })
#define __swp_entry_to_pte(x)		((pte_t) { 0, (x).val })

/*
 * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
 */
#define pte_to_pgoff(_pte)		((_pte).pte_high >> 2)
#define pgoff_to_pte(off)		((pte_t) { _PAGE_FILE, (off) << 2 })

#define PTE_FILE_MAX_BITS		30
#else
/*
 * Constraints:
 *      _PAGE_PRESENT at bit 0
 *      _PAGE_MODIFIED at bit 4
 *      _PAGE_GLOBAL at bit 6
 *      _PAGE_VALID at bit 7
 */
#define __swp_type(x)			(((x).val >> 8) & 0x1f)
#define __swp_offset(x)			 ((x).val >> 13)
#define __swp_entry(type,offset)	((swp_entry_t)	{ ((type) << 8) | ((offset) << 13) })
#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)		((pte_t) { (x).val })

/*
 * Encode and decode a nonlinear file mapping entry
 */
#define pte_to_pgoff(_pte)		((((_pte).pte >> 1) & 0x7) | \
					 (((_pte).pte >> 2) & 0x8) | \
					 (((_pte).pte >> 8) <<	4))

#define pgoff_to_pte(off)		((pte_t) { (((off) & 0x7) << 1) | \
						   (((off) & 0x8) << 2) | \
						   (((off) >>  4) << 8) | \
						   _PAGE_FILE })

#define PTE_FILE_MAX_BITS		28
#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */

#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */

#endif /* _ASM_PGTABLE_32_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
	7	* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
	8	*/
	9	#ifndef _ASM_PGTABLE_32_H
	10	#define _ASM_PGTABLE_32_H
	11
1da177e4 LT	12	#include <asm/addrspace.h>
	13	#include <asm/page.h>
	14
	15	#include <linux/linkage.h>
	16	#include <asm/cachectl.h>
	17	#include <asm/fixmap.h>
	18
c6e8b587 RB	19	#include <asm-generic/pgtable-nopmd.h>
c6e8b587 RB	20
6ee1d934 RM	21	extern int temp_tlb_entry __cpuinitdata;
6ee1d934 RM	22
d377732c RM	23	/*
	24	* - add_temporary_entry() add a temporary TLB entry. We use TLB entries
	25	* starting at the top and working down. This is for populating the
	26	* TLB before trap_init() puts the TLB miss handler in place. It
	27	* should be used only for entries matching the actual page tables,
	28	* to prevent inconsistencies.
	29	*/
	30	extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
	31	unsigned long entryhi, unsigned long pagemask);
	32
1da177e4	33	/*
39b74143	34	* Basically we have the same two-level (which is the logical three level
1da177e4 LT	35	* Linux page table layout folded) page tables as the i386. Some day
	36	* when we have proper page coloring support we can have a 1% quicker
	37	* tlb refill handling mechanism, but for now it is a bit slower but
	38	* works even with the cache aliasing problem the R4k and above have.
	39	*/
	40
1da177e4	41	/* PGDIR_SHIFT determines what a third-level page table entry can map */
4c8081e4	42	#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
1da177e4 LT	43	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	44	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	45
	46	/*
	47	* Entries per page directory level: we use two-level, so
c6e8b587	48	* we don't really have any PUD/PMD directory physically.
1da177e4	49	*/
99e480d8 RB	50	#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
99e480d8 RB	51	#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
c6e8b587 RB	52	#define PUD_ORDER aieeee_attempt_to_allocate_pud
c6e8b587 RB	53	#define PMD_ORDER 1
1da177e4	54	#define PTE_ORDER 0
1da177e4	55
5291925a	56	#define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
1da177e4 LT	57	#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
	58
	59	#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
d455a369	60	#define FIRST_USER_ADDRESS 0
1da177e4	61
70342287	62	#define VMALLOC_START MAP_BASE
1da177e4	63
2ac7401d RB	64	#define PKMAP_BASE (0xfe000000UL)
2ac7401d RB	65
1da177e4 LT	66	#ifdef CONFIG_HIGHMEM
	67	# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
	68	#else
	69	# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
	70	#endif
	71
34adb28d	72	#ifdef CONFIG_PHYS_ADDR_T_64BIT
1da177e4 LT	73	#define pte_ERROR(e) \
	74	printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
	75	#else
	76	#define pte_ERROR(e) \
	77	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
	78	#endif
1da177e4 LT	79	#define pgd_ERROR(e) \
	80	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
	81
	82	extern void load_pgd(unsigned long pg_dir);
	83
	84	extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
	85
	86	/*
	87	* Empty pgd/pmd entries point to the invalid_pte_table.
	88	*/
	89	static inline int pmd_none(pmd_t pmd)
	90	{
	91	return pmd_val(pmd) == (unsigned long) invalid_pte_table;
	92	}
	93
	94	#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
	95
	96	static inline int pmd_present(pmd_t pmd)
	97	{
	98	return pmd_val(pmd) != (unsigned long) invalid_pte_table;
	99	}
	100
	101	static inline void pmd_clear(pmd_t *pmdp)
	102	{
	103	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
	104	}
	105
34adb28d	106	#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
1da177e4 LT	107	#define pte_page(x) pfn_to_page(pte_pfn(x))
	108	#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
	109	static inline pte_t
	110	pfn_pte(unsigned long pfn, pgprot_t prot)
	111	{
	112	pte_t pte;
	113	pte.pte_high = (pfn << 6) \| (pgprot_val(prot) & 0x3f);
	114	pte.pte_low = pgprot_val(prot);
	115	return pte;
	116	}
	117
	118	#else
	119
	120	#define pte_page(x) pfn_to_page(pte_pfn(x))
	121
	122	#ifdef CONFIG_CPU_VR41XX
	123	#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
	124	#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) \| pgprot_val(prot))
	125	#else
6dd9344c DD	126	#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
6dd9344c DD	127	#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) \| pgprot_val(prot))
1da177e4	128	#endif
34adb28d	129	#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
1da177e4 LT	130
1da177e4 LT	131	#define __pgd_offset(address) pgd_index(address)
f29244a5	132	#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1da177e4 LT	133	#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
	134
	135	/* to find an entry in a kernel page-table-directory */
	136	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	137
f29244a5	138	#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1da177e4 LT	139
1da177e4 LT	140	/* to find an entry in a page-table-directory */
21a151d8	141	#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
1da177e4	142
1da177e4 LT	143	/* Find an entry in the third-level page table.. */
	144	#define __pte_offset(address) \
	145	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	146	#define pte_offset(dir, address) \
5b70a317 FBH	147	((pte_t ) pmd_page_vaddr((dir)) + __pte_offset(address))
	148	#define pte_offset_kernel(dir, address) \
	149	((pte_t ) pmd_page_vaddr((dir)) + __pte_offset(address))
1da177e4	150
70342287	151	#define pte_offset_map(dir, address) \
1da177e4	152	((pte_t )page_address(pmd_page((dir))) + __pte_offset(address))
1da177e4	153	#define pte_unmap(pte) ((void)(pte))
1da177e4 LT	154
	155	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
	156
	157	/* Swap entries must have VALID bit cleared. */
77a5c593 SH	158	#define __swp_type(x) (((x).val >> 10) & 0x1f)
	159	#define __swp_offset(x) ((x).val >> 15)
	160	#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 10) \| ((offset) << 15) })
	161	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	162	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1da177e4 LT	163
1da177e4 LT	164	/*
77a5c593	165	* Encode and decode a nonlinear file mapping entry
1da177e4	166	*/
77a5c593 SH	167	#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) \| \
	168	(((_pte).pte >> 2 ) & 0x38) \| \
	169	(((_pte).pte >> 10) << 6 ))
1da177e4	170
77a5c593 SH	171	#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) \| \
	172	(((off) & 0x38) << 2 ) \| \
	173	(((off) >> 6 ) << 10) \| \
	174	_PAGE_FILE })
1da177e4	175
77a5c593 SH	176	/*
	177	* Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
	178	*/
	179	#define PTE_FILE_MAX_BITS 28
1da177e4 LT	180	#else
1da177e4 LT	181
34adb28d	182	#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
1da177e4	183
77a5c593 SH	184	/* Swap entries must have VALID and GLOBAL bits cleared. */
	185	#define __swp_type(x) (((x).val >> 2) & 0x1f)
	186	#define __swp_offset(x) ((x).val >> 7)
	187	#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) \| ((offset) << 7) })
	188	#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
	189	#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
	190
1da177e4	191	/*
7cb710c9	192	* Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
1da177e4	193	*/
77a5c593 SH	194	#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2)
77a5c593 SH	195	#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 })
1da177e4	196
77a5c593	197	#define PTE_FILE_MAX_BITS 30
1da177e4	198	#else
7cb710c9	199	/*
77a5c593 SH	200	* Constraints:
	201	* _PAGE_PRESENT at bit 0
	202	* _PAGE_MODIFIED at bit 4
	203	* _PAGE_GLOBAL at bit 6
	204	* _PAGE_VALID at bit 7
7cb710c9	205	*/
77a5c593 SH	206	#define __swp_type(x) (((x).val >> 8) & 0x1f)
	207	#define __swp_offset(x) ((x).val >> 13)
	208	#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 8) \| ((offset) << 13) })
	209	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	210	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
7cb710c9	211
77a5c593 SH	212	/*
	213	* Encode and decode a nonlinear file mapping entry
	214	*/
	215	#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) \| \
	216	(((_pte).pte >> 2) & 0x8) \| \
	217	(((_pte).pte >> 8) << 4))
1da177e4	218
77a5c593 SH	219	#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) \| \
	220	(((off) & 0x8) << 2) \| \
	221	(((off) >> 4) << 8) \| \
	222	_PAGE_FILE })
1da177e4	223
77a5c593 SH	224	#define PTE_FILE_MAX_BITS 28
77a5c593 SH	225	#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
1da177e4	226
77a5c593	227	#endif /* defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX) */
1da177e4 LT	228
1da177e4 LT	229	#endif /* _ASM_PGTABLE_32_H */