[deliverable/linux.git] / arch / mips / include / asm / pgtable-64.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
 */
#ifndef _ASM_PGTABLE_64_H
#define _ASM_PGTABLE_64_H

#include <linux/linkage.h>

#include <asm/addrspace.h>
#include <asm/page.h>
#include <asm/cachectl.h>
#include <asm/fixmap.h>

#include <asm-generic/pgtable-nopud.h>

/*
 * Each address space has 2 4K pages as its page directory, giving 1024
 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
 * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
 * tables. Each page table is also a single 4K page, giving 512 (==
 * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
 * invalid_pmd_table, each pmd entry is initialized to point to
 * invalid_pte_table, each pte is initialized to 0. When memory is low,
 * and a pmd table or a page table allocation fails, empty_bad_pmd_table
 * and empty_bad_page_table is returned back to higher layer code, so
 * that the failure is recognized later on. Linux does not seem to
 * handle these failures very well though. The empty_bad_page_table has
 * invalid pte entries in it, to force page faults.
 *
 * Kernel mappings: kernel mappings are held in the swapper_pg_table.
 * The layout is identical to userspace except it's indexed with the
 * fault address - VMALLOC_START.
 */

/* PMD_SHIFT determines the size of the area a second-level page table can map */
#define PMD_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
#define PMD_SIZE	(1UL << PMD_SHIFT)
#define PMD_MASK	(~(PMD_SIZE-1))

/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define PGDIR_SHIFT	(PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * For 4kB page size we use a 3 level page tree and an 8kB pud, which
 * permits us mapping 40 bits of virtual address space.
 *
 * We used to implement 41 bits by having an order 1 pmd level but that seemed
 * rather pointless.
 *
 * For 8kB page size we use a 3 level page tree which permits a total of
 * 8TB of address space.  Alternatively a 33-bit / 8GB organization using
 * two levels would be easy to implement.
 *
 * For 16kB page size we use a 2 level page tree which permits a total of
 * 36 bits of virtual address space.  We could add a third level but it seems
 * like at the moment there's no need for this.
 *
 * For 64kB page size we use a 2 level page table tree for a total of 42 bits
 * of virtual address space.
 */
#ifdef CONFIG_PAGE_SIZE_4KB
#define PGD_ORDER		1
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif
#ifdef CONFIG_PAGE_SIZE_8KB
#define PGD_ORDER		0
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif
#ifdef CONFIG_PAGE_SIZE_16KB
#define PGD_ORDER		0
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif
#ifdef CONFIG_PAGE_SIZE_32KB
#define PGD_ORDER		0
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif
#ifdef CONFIG_PAGE_SIZE_64KB
#define PGD_ORDER		0
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif

#define PTRS_PER_PGD	((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
#define PTRS_PER_PMD	((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
#define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))

#if PGDIR_SIZE >= TASK_SIZE
#define USER_PTRS_PER_PGD       (1)
#else
#define USER_PTRS_PER_PGD	(TASK_SIZE / PGDIR_SIZE)
#endif
#define FIRST_USER_ADDRESS	0UL

#define VMALLOC_START		MAP_BASE
#define VMALLOC_END	\
	(VMALLOC_START + \
	 PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32))
#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
	VMALLOC_START != CKSSEG
/* Load modules into 32bit-compatible segment. */
#define MODULE_START	CKSSEG
#define MODULE_END	(FIXADDR_START-2*PAGE_SIZE)
#endif

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
	printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))

extern pte_t invalid_pte_table[PTRS_PER_PTE];
extern pte_t empty_bad_page_table[PTRS_PER_PTE];
extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];

/*
 * Empty pgd/pmd entries point to the invalid_pte_table.
 */
static inline int pmd_none(pmd_t pmd)
{
	return pmd_val(pmd) == (unsigned long) invalid_pte_table;
}

#define pmd_bad(pmd)		(pmd_val(pmd) & ~PAGE_MASK)

static inline int pmd_present(pmd_t pmd)
{
	return pmd_val(pmd) != (unsigned long) invalid_pte_table;
}

static inline void pmd_clear(pmd_t *pmdp)
{
	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
}

/*
 * Empty pud entries point to the invalid_pmd_table.
 */
static inline int pud_none(pud_t pud)
{
	return pud_val(pud) == (unsigned long) invalid_pmd_table;
}

static inline int pud_bad(pud_t pud)
{
	return pud_val(pud) & ~PAGE_MASK;
}

static inline int pud_present(pud_t pud)
{
	return pud_val(pud) != (unsigned long) invalid_pmd_table;
}

static inline void pud_clear(pud_t *pudp)
{
	pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
}

#define pte_page(x)		pfn_to_page(pte_pfn(x))

#ifdef CONFIG_CPU_VR41XX
#define pte_pfn(x)		((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
#define pfn_pte(pfn, prot)	__pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
#else
#define pte_pfn(x)		((unsigned long)((x).pte >> PAGE_SHIFT))
#define pfn_pte(pfn, prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
#endif

#define __pgd_offset(address)	pgd_index(address)
#define __pud_offset(address)	(((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
#define __pmd_offset(address)	pmd_index(address)

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

#define pgd_index(address)	(((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
#define pmd_index(address)	(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))

/* to find an entry in a page-table-directory */
#define pgd_offset(mm, addr)	((mm)->pgd + pgd_index(addr))

static inline unsigned long pud_page_vaddr(pud_t pud)
{
	return pud_val(pud);
}
#define pud_phys(pud)		virt_to_phys((void *)pud_val(pud))
#define pud_page(pud)		(pfn_to_page(pud_phys(pud) >> PAGE_SHIFT))

/* Find an entry in the second-level page table.. */
static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
{
	return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address);
}

/* Find an entry in the third-level page table.. */
#define __pte_offset(address)						\
	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset(dir, address)					\
	((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
#define pte_offset_kernel(dir, address)					\
	((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
#define pte_offset_map(dir, address)					\
	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define pte_offset_map_nested(dir, address)				\
	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define pte_unmap(pte) ((void)(pte))
#define pte_unmap_nested(pte) ((void)(pte))

/*
 * Initialize a new pgd / pmd table with invalid pointers.
 */
extern void pgd_init(unsigned long page);
extern void pmd_init(unsigned long page, unsigned long pagetable);

/*
 * Non-present pages:  high 24 bits are offset, next 8 bits type,
 * low 32 bits zero.
 */
static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }

#define __swp_type(x)		(((x).val >> 32) & 0xff)
#define __swp_offset(x)		((x).val >> 40)
#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)	((pte_t) { (x).val })

/*
 * Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to
 * make things easier, and only use the upper 56 bits for the page offset...
 */
#define PTE_FILE_MAX_BITS	56

#define pte_to_pgoff(_pte)	((_pte).pte >> 8)
#define pgoff_to_pte(off)	((pte_t) { ((off) << 8) | _PAGE_FILE })

#endif /* _ASM_PGTABLE_64_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
	7	* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
	8	*/
	9	#ifndef _ASM_PGTABLE_64_H
	10	#define _ASM_PGTABLE_64_H
	11
1da177e4 LT	12	#include <linux/linkage.h>
	13
	14	#include <asm/addrspace.h>
	15	#include <asm/page.h>
	16	#include <asm/cachectl.h>
656be92f	17	#include <asm/fixmap.h>
1da177e4	18
c6e8b587 RB	19	#include <asm-generic/pgtable-nopud.h>
c6e8b587 RB	20
1da177e4 LT	21	/*
	22	* Each address space has 2 4K pages as its page directory, giving 1024
	23	* (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
c6e8b587 RB	24	* single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
	25	* tables. Each page table is also a single 4K page, giving 512 (==
	26	* PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
	27	* invalid_pmd_table, each pmd entry is initialized to point to
1da177e4 LT	28	* invalid_pte_table, each pte is initialized to 0. When memory is low,
	29	* and a pmd table or a page table allocation fails, empty_bad_pmd_table
	30	* and empty_bad_page_table is returned back to higher layer code, so
	31	* that the failure is recognized later on. Linux does not seem to
	32	* handle these failures very well though. The empty_bad_page_table has
	33	* invalid pte entries in it, to force page faults.
	34	*
	35	* Kernel mappings: kernel mappings are held in the swapper_pg_table.
	36	* The layout is identical to userspace except it's indexed with the
	37	* fault address - VMALLOC_START.
	38	*/
	39
	40	/* PMD_SHIFT determines the size of the area a second-level page table can map */
c6e8b587	41	#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
1da177e4 LT	42	#define PMD_SIZE (1UL << PMD_SHIFT)
	43	#define PMD_MASK (~(PMD_SIZE-1))
	44
	45	/* PGDIR_SHIFT determines what a third-level page table entry can map */
c6e8b587	46	#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
1da177e4 LT	47	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	48	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	49
	50	/*
c6e8b587	51	* For 4kB page size we use a 3 level page tree and an 8kB pud, which
1da177e4 LT	52	* permits us mapping 40 bits of virtual address space.
	53	*
	54	* We used to implement 41 bits by having an order 1 pmd level but that seemed
	55	* rather pointless.
	56	*
	57	* For 8kB page size we use a 3 level page tree which permits a total of
	58	* 8TB of address space. Alternatively a 33-bit / 8GB organization using
	59	* two levels would be easy to implement.
	60	*
	61	* For 16kB page size we use a 2 level page tree which permits a total of
f29244a5	62	* 36 bits of virtual address space. We could add a third level but it seems
1da177e4 LT	63	* like at the moment there's no need for this.
	64	*
	65	* For 64kB page size we use a 2 level page table tree for a total of 42 bits
	66	* of virtual address space.
	67	*/
	68	#ifdef CONFIG_PAGE_SIZE_4KB
	69	#define PGD_ORDER 1
c6e8b587	70	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1da177e4 LT	71	#define PMD_ORDER 0
	72	#define PTE_ORDER 0
	73	#endif
	74	#ifdef CONFIG_PAGE_SIZE_8KB
	75	#define PGD_ORDER 0
c6e8b587	76	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1da177e4 LT	77	#define PMD_ORDER 0
	78	#define PTE_ORDER 0
	79	#endif
	80	#ifdef CONFIG_PAGE_SIZE_16KB
	81	#define PGD_ORDER 0
c6e8b587	82	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1da177e4 LT	83	#define PMD_ORDER 0
	84	#define PTE_ORDER 0
	85	#endif
c52399be RB	86	#ifdef CONFIG_PAGE_SIZE_32KB
	87	#define PGD_ORDER 0
	88	#define PUD_ORDER aieeee_attempt_to_allocate_pud
	89	#define PMD_ORDER 0
	90	#define PTE_ORDER 0
	91	#endif
1da177e4 LT	92	#ifdef CONFIG_PAGE_SIZE_64KB
1da177e4 LT	93	#define PGD_ORDER 0
c6e8b587	94	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1da177e4 LT	95	#define PMD_ORDER 0
	96	#define PTE_ORDER 0
	97	#endif
	98
	99	#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
	100	#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
	101	#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
	102
9dbd7b91 PW	103	#if PGDIR_SIZE >= TASK_SIZE
	104	#define USER_PTRS_PER_PGD (1)
	105	#else
1da177e4	106	#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
9dbd7b91 PW	107	#endif
9dbd7b91 PW	108	#define FIRST_USER_ADDRESS 0UL
1da177e4	109
f29244a5	110	#define VMALLOC_START MAP_BASE
1da177e4	111	#define VMALLOC_END \
e0cc87f5 WF	112	(VMALLOC_START + \
e0cc87f5 WF	113	PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32))
054c51b4	114	#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
656be92f AN	115	VMALLOC_START != CKSSEG
	116	/* Load modules into 32bit-compatible segment. */
	117	#define MODULE_START CKSSEG
	118	#define MODULE_END (FIXADDR_START-2*PAGE_SIZE)
656be92f	119	#endif
1da177e4 LT	120
	121	#define pte_ERROR(e) \
	122	printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
	123	#define pmd_ERROR(e) \
	124	printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
	125	#define pgd_ERROR(e) \
	126	printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
	127
c6e8b587 RB	128	extern pte_t invalid_pte_table[PTRS_PER_PTE];
	129	extern pte_t empty_bad_page_table[PTRS_PER_PTE];
	130	extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
	131	extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
1da177e4 LT	132
1da177e4 LT	133	/*
1b3a6e97	134	* Empty pgd/pmd entries point to the invalid_pte_table.
1da177e4 LT	135	*/
	136	static inline int pmd_none(pmd_t pmd)
	137	{
	138	return pmd_val(pmd) == (unsigned long) invalid_pte_table;
	139	}
	140
	141	#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
	142
	143	static inline int pmd_present(pmd_t pmd)
	144	{
	145	return pmd_val(pmd) != (unsigned long) invalid_pte_table;
	146	}
	147
	148	static inline void pmd_clear(pmd_t *pmdp)
	149	{
	150	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
	151	}
	152
	153	/*
f29244a5	154	* Empty pud entries point to the invalid_pmd_table.
1da177e4	155	*/
c6e8b587	156	static inline int pud_none(pud_t pud)
1da177e4	157	{
c6e8b587	158	return pud_val(pud) == (unsigned long) invalid_pmd_table;
1da177e4 LT	159	}
1da177e4 LT	160
c6e8b587 RB	161	static inline int pud_bad(pud_t pud)
	162	{
	163	return pud_val(pud) & ~PAGE_MASK;
	164	}
1da177e4	165
c6e8b587	166	static inline int pud_present(pud_t pud)
1da177e4	167	{
c6e8b587	168	return pud_val(pud) != (unsigned long) invalid_pmd_table;
1da177e4 LT	169	}
1da177e4 LT	170
c6e8b587	171	static inline void pud_clear(pud_t *pudp)
1da177e4	172	{
c6e8b587	173	pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
1da177e4 LT	174	}
1da177e4 LT	175
1b3a6e97 TS	176	#define pte_page(x) pfn_to_page(pte_pfn(x))
1b3a6e97 TS	177
1da177e4 LT	178	#ifdef CONFIG_CPU_VR41XX
	179	#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
	180	#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) \| pgprot_val(prot))
	181	#else
	182	#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
	183	#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) \| pgprot_val(prot))
	184	#endif
	185
	186	#define __pgd_offset(address) pgd_index(address)
f29244a5	187	#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1b3a6e97	188	#define __pmd_offset(address) pmd_index(address)
1da177e4 LT	189
1da177e4 LT	190	/* to find an entry in a kernel page-table-directory */
e0cc87f5	191	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
1da177e4	192
f29244a5	193	#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1b3a6e97	194	#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1da177e4 LT	195
1da177e4 LT	196	/* to find an entry in a page-table-directory */
21a151d8	197	#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
1da177e4	198
46a82b2d	199	static inline unsigned long pud_page_vaddr(pud_t pud)
1da177e4	200	{
c6e8b587	201	return pud_val(pud);
1da177e4	202	}
c9d06962	203	#define pud_phys(pud) virt_to_phys((void *)pud_val(pud))
46a82b2d	204	#define pud_page(pud) (pfn_to_page(pud_phys(pud) >> PAGE_SHIFT))
1da177e4 LT	205
1da177e4 LT	206	/* Find an entry in the second-level page table.. */
c6e8b587	207	static inline pmd_t pmd_offset(pud_t pud, unsigned long address)
1da177e4	208	{
46a82b2d	209	return (pmd_t ) pud_page_vaddr(pud) + pmd_index(address);
1da177e4 LT	210	}
	211
	212	/* Find an entry in the third-level page table.. */
	213	#define __pte_offset(address) \
	214	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	215	#define pte_offset(dir, address) \
5b70a317	216	((pte_t ) pmd_page_vaddr((dir)) + __pte_offset(address))
1da177e4	217	#define pte_offset_kernel(dir, address) \
5b70a317	218	((pte_t ) pmd_page_vaddr((dir)) + __pte_offset(address))
1da177e4 LT	219	#define pte_offset_map(dir, address) \
	220	((pte_t )page_address(pmd_page((dir))) + __pte_offset(address))
	221	#define pte_offset_map_nested(dir, address) \
	222	((pte_t )page_address(pmd_page((dir))) + __pte_offset(address))
	223	#define pte_unmap(pte) ((void)(pte))
	224	#define pte_unmap_nested(pte) ((void)(pte))
	225
	226	/*
	227	* Initialize a new pgd / pmd table with invalid pointers.
	228	*/
	229	extern void pgd_init(unsigned long page);
	230	extern void pmd_init(unsigned long page, unsigned long pagetable);
	231
	232	/*
	233	* Non-present pages: high 24 bits are offset, next 8 bits type,
	234	* low 32 bits zero.
	235	*/
	236	static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
	237	{ pte_t pte; pte_val(pte) = (type << 32) \| (offset << 40); return pte; }
	238
	239	#define __swp_type(x) (((x).val >> 32) & 0xff)
	240	#define __swp_offset(x) ((x).val >> 40)
21a151d8	241	#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
1da177e4 LT	242	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	243	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
	244
	245	/*
7cb710c9 SS	246	* Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to
7cb710c9 SS	247	* make things easier, and only use the upper 56 bits for the page offset...
1da177e4	248	*/
7cb710c9	249	#define PTE_FILE_MAX_BITS 56
1da177e4	250
7cb710c9 SS	251	#define pte_to_pgoff(_pte) ((_pte).pte >> 8)
7cb710c9 SS	252	#define pgoff_to_pte(off) ((pte_t) { ((off) << 8) \| _PAGE_FILE })
1da177e4 LT	253
1da177e4 LT	254	#endif /* _ASM_PGTABLE_64_H */