[deliverable/linux.git] / arch / mips / include / asm / pgtable-bits.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 - 2002 by Ralf Baechle
 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
 * Copyright (C) 2002  Maciej W. Rozycki
 */
#ifndef _ASM_PGTABLE_BITS_H
#define _ASM_PGTABLE_BITS_H


/*
 * Note that we shift the lower 32bits of each EntryLo[01] entry
 * 6 bits to the left. That way we can convert the PFN into the
 * physical address by a single 'and' operation and gain 6 additional
 * bits for storing information which isn't present in a normal
 * MIPS page table.
 *
 * Similar to the Alpha port, we need to keep track of the ref
 * and mod bits in software.  We have a software "yeah you can read
 * from this page" bit, and a hardware one which actually lets the
 * process read from the page.	On the same token we have a software
 * writable bit and the real hardware one which actually lets the
 * process write to the page, this keeps a mod bit via the hardware
 * dirty bit.
 *
 * Certain revisions of the R4000 and R5000 have a bug where if a
 * certain sequence occurs in the last 3 instructions of an executable
 * page, and the following page is not mapped, the cpu can do
 * unpredictable things.  The code (when it is written) to deal with
 * this problem will be in the update_mmu_cache() code for the r4k.
 */
#if defined(CONFIG_XPA)

/*
 * Page table bit offsets used for 64 bit physical addressing on
 * MIPS32r5 with XPA.
 */
enum pgtable_bits {
	/* Used by TLB hardware (placed in EntryLo*) */
	_PAGE_NO_EXEC_SHIFT,
	_PAGE_NO_READ_SHIFT,
	_PAGE_GLOBAL_SHIFT,
	_PAGE_VALID_SHIFT,
	_PAGE_DIRTY_SHIFT,
	_CACHE_SHIFT,

	/* Used only by software (masked out before writing EntryLo*) */
	_PAGE_PRESENT_SHIFT = 24,
	_PAGE_WRITE_SHIFT,
	_PAGE_ACCESSED_SHIFT,
	_PAGE_MODIFIED_SHIFT,
};

/*
 * Bits for extended EntryLo0/EntryLo1 registers
 */
#define _PFNX_MASK		0xffffff

#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)

/*
 * Page table bit offsets used for 36 bit physical addressing on MIPS32,
 * for example with Alchemy or Netlogic XLP/XLR.
 */
enum pgtable_bits {
	/* Used by TLB hardware (placed in EntryLo*) */
	_PAGE_GLOBAL_SHIFT,
	_PAGE_VALID_SHIFT,
	_PAGE_DIRTY_SHIFT,
	_CACHE_SHIFT,

	/* Used only by software (masked out before writing EntryLo*) */
	_PAGE_PRESENT_SHIFT = _CACHE_SHIFT + 3,
	_PAGE_NO_READ_SHIFT,
	_PAGE_WRITE_SHIFT,
	_PAGE_ACCESSED_SHIFT,
	_PAGE_MODIFIED_SHIFT,
};

#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

/* Page table bits used for r3k systems */
enum pgtable_bits {
	/* Used only by software (writes to EntryLo ignored) */
	_PAGE_PRESENT_SHIFT,
	_PAGE_NO_READ_SHIFT,
	_PAGE_WRITE_SHIFT,
	_PAGE_ACCESSED_SHIFT,
	_PAGE_MODIFIED_SHIFT,

	/* Used by TLB hardware (placed in EntryLo) */
	_PAGE_GLOBAL_SHIFT = 8,
	_PAGE_VALID_SHIFT,
	_PAGE_DIRTY_SHIFT,
	_CACHE_UNCACHED_SHIFT,
};

#else

/* Page table bits used for r4k systems */
enum pgtable_bits {
	/* Used only by software (masked out before writing EntryLo*) */
	_PAGE_PRESENT_SHIFT,
#if !defined(CONFIG_CPU_HAS_RIXI)
	_PAGE_NO_READ_SHIFT,
#endif
	_PAGE_WRITE_SHIFT,
	_PAGE_ACCESSED_SHIFT,
	_PAGE_MODIFIED_SHIFT,
#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
	_PAGE_HUGE_SHIFT,
#endif

	/* Used by TLB hardware (placed in EntryLo*) */
#if defined(CONFIG_CPU_HAS_RIXI)
	_PAGE_NO_EXEC_SHIFT,
	_PAGE_NO_READ_SHIFT,
#endif
	_PAGE_GLOBAL_SHIFT,
	_PAGE_VALID_SHIFT,
	_PAGE_DIRTY_SHIFT,
	_CACHE_SHIFT,
};

#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */

/* Used only by software */
#define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)
#define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
#define _PAGE_ACCESSED		(1 << _PAGE_ACCESSED_SHIFT)
#define _PAGE_MODIFIED		(1 << _PAGE_MODIFIED_SHIFT)
#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
# define _PAGE_HUGE		(1 << _PAGE_HUGE_SHIFT)
#endif

/* Used by TLB hardware (placed in EntryLo*) */
#if defined(CONFIG_XPA)
# define _PAGE_NO_EXEC		(1 << _PAGE_NO_EXEC_SHIFT)
#elif defined(CONFIG_CPU_HAS_RIXI)
# define _PAGE_NO_EXEC		(cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
#endif
#define _PAGE_NO_READ		(1 << _PAGE_NO_READ_SHIFT)
#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)
#define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
#define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
# define _CACHE_UNCACHED	(1 << _CACHE_UNCACHED_SHIFT)
# define _CACHE_MASK		_CACHE_UNCACHED
# define _PFN_SHIFT		PAGE_SHIFT
#else
# define _CACHE_MASK		(7 << _CACHE_SHIFT)
# define _PFN_SHIFT		(PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
#endif

#ifndef _PAGE_NO_EXEC
#define _PAGE_NO_EXEC		0
#endif

#define _PAGE_SILENT_READ	_PAGE_VALID
#define _PAGE_SILENT_WRITE	_PAGE_DIRTY

#define _PFN_MASK		(~((1 << (_PFN_SHIFT)) - 1))

/*
 * The final layouts of the PTE bits are:
 *
 *   64-bit, R1 or earlier:     CCC D V G [S H] M A W R P
 *   32-bit, R1 or earler:      CCC D V G M A W R P
 *   64-bit, R2 or later:       CCC D V G RI/R XI [S H] M A W P
 *   32-bit, R2 or later:       CCC D V G RI/R XI M A W P
 */


/*
 * pte_to_entrylo converts a page table entry (PTE) into a Mips
 * entrylo0/1 value.
 */
static inline uint64_t pte_to_entrylo(unsigned long pte_val)
{
#ifdef CONFIG_CPU_HAS_RIXI
	if (cpu_has_rixi) {
		int sa;
#ifdef CONFIG_32BIT
		sa = 31 - _PAGE_NO_READ_SHIFT;
#else
		sa = 63 - _PAGE_NO_READ_SHIFT;
#endif
		/*
		 * C has no way to express that this is a DSRL
		 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2.  Luckily
		 * in the fast path this is done in assembly
		 */
		return (pte_val >> _PAGE_GLOBAL_SHIFT) |
			((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
	}
#endif

	return pte_val >> _PAGE_GLOBAL_SHIFT;
}

/*
 * Cache attributes
 */
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

#define _CACHE_CACHABLE_NONCOHERENT 0
#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED

#elif defined(CONFIG_CPU_SB1)

/* No penalty for being coherent on the SB1, so just
   use it for "noncoherent" spaces, too.  Shouldn't hurt. */

#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)

#elif defined(CONFIG_CPU_LOONGSON3)

/* Using COHERENT flag for NONCOHERENT doesn't hurt. */

#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
#define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */

#elif defined(CONFIG_MACH_INGENIC)

/* Ingenic uses the WA bit to achieve write-combine memory writes */
#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)

#endif

#ifndef _CACHE_CACHABLE_NO_WA
#define _CACHE_CACHABLE_NO_WA		(0<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_WA
#define _CACHE_CACHABLE_WA		(1<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_UNCACHED
#define _CACHE_UNCACHED			(2<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_NONCOHERENT
#define _CACHE_CACHABLE_NONCOHERENT	(3<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_CE
#define _CACHE_CACHABLE_CE		(4<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_COW
#define _CACHE_CACHABLE_COW		(5<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_CUW
#define _CACHE_CACHABLE_CUW		(6<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_UNCACHED_ACCELERATED
#define _CACHE_UNCACHED_ACCELERATED	(7<<_CACHE_SHIFT)
#endif

#define __READABLE	(_PAGE_SILENT_READ | _PAGE_ACCESSED)
#define __WRITEABLE	(_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)

#define _PAGE_CHG_MASK	(_PAGE_ACCESSED | _PAGE_MODIFIED |	\
			 _PFN_MASK | _CACHE_MASK)

#endif /* _ASM_PGTABLE_BITS_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 - 2002 by Ralf Baechle
	7	* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
	8	* Copyright (C) 2002 Maciej W. Rozycki
	9	*/
	10	#ifndef _ASM_PGTABLE_BITS_H
	11	#define _ASM_PGTABLE_BITS_H
	12
1da177e4 LT	13
	14	/*
	15	* Note that we shift the lower 32bits of each EntryLo[01] entry
	16	* 6 bits to the left. That way we can convert the PFN into the
	17	* physical address by a single 'and' operation and gain 6 additional
	18	* bits for storing information which isn't present in a normal
	19	* MIPS page table.
	20	*
	21	* Similar to the Alpha port, we need to keep track of the ref
	22	* and mod bits in software. We have a software "yeah you can read
	23	* from this page" bit, and a hardware one which actually lets the
70342287	24	* process read from the page. On the same token we have a software
1da177e4 LT	25	* writable bit and the real hardware one which actually lets the
	26	* process write to the page, this keeps a mod bit via the hardware
	27	* dirty bit.
	28	*
	29	* Certain revisions of the R4000 and R5000 have a bug where if a
	30	* certain sequence occurs in the last 3 instructions of an executable
	31	* page, and the following page is not mapped, the cpu can do
	32	* unpredictable things. The code (when it is written) to deal with
	33	* this problem will be in the update_mmu_cache() code for the r4k.
	34	*/
7b2cb64f	35	#if defined(CONFIG_XPA)
1da177e4	36
a2c763e0	37	/*
7b2cb64f PB	38	* Page table bit offsets used for 64 bit physical addressing on
7b2cb64f PB	39	* MIPS32r5 with XPA.
a2c763e0	40	*/
69497700 PB	41	enum pgtable_bits {
	42	/* Used by TLB hardware (placed in EntryLo) /
	43	_PAGE_NO_EXEC_SHIFT,
	44	_PAGE_NO_READ_SHIFT,
	45	_PAGE_GLOBAL_SHIFT,
	46	_PAGE_VALID_SHIFT,
	47	_PAGE_DIRTY_SHIFT,
	48	_CACHE_SHIFT,
	49
	50	/* Used only by software (masked out before writing EntryLo) /
	51	_PAGE_PRESENT_SHIFT = 24,
69497700 PB	52	_PAGE_WRITE_SHIFT,
	53	_PAGE_ACCESSED_SHIFT,
	54	_PAGE_MODIFIED_SHIFT,
	55	};
1da177e4	56
c5b36783 SH	57	/*
	58	* Bits for extended EntryLo0/EntryLo1 registers
	59	*/
	60	#define _PFNX_MASK 0xffffff
	61
7b2cb64f PB	62	#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
	63
	64	/*
	65	* Page table bit offsets used for 36 bit physical addressing on MIPS32,
	66	* for example with Alchemy or Netlogic XLP/XLR.
	67	*/
	68	enum pgtable_bits {
	69	/* Used by TLB hardware (placed in EntryLo) /
	70	_PAGE_GLOBAL_SHIFT,
	71	_PAGE_VALID_SHIFT,
	72	_PAGE_DIRTY_SHIFT,
	73	_CACHE_SHIFT,
	74
	75	/* Used only by software (masked out before writing EntryLo) /
	76	_PAGE_PRESENT_SHIFT = _CACHE_SHIFT + 3,
	77	_PAGE_NO_READ_SHIFT,
	78	_PAGE_WRITE_SHIFT,
	79	_PAGE_ACCESSED_SHIFT,
	80	_PAGE_MODIFIED_SHIFT,
	81	};
	82
6dd9344c	83	#elif defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
1da177e4	84
69497700 PB	85	/* Page table bits used for r3k systems */
	86	enum pgtable_bits {
	87	/* Used only by software (writes to EntryLo ignored) */
	88	_PAGE_PRESENT_SHIFT,
780602d7	89	_PAGE_NO_READ_SHIFT,
69497700 PB	90	_PAGE_WRITE_SHIFT,
	91	_PAGE_ACCESSED_SHIFT,
	92	_PAGE_MODIFIED_SHIFT,
	93
	94	/* Used by TLB hardware (placed in EntryLo) */
	95	_PAGE_GLOBAL_SHIFT = 8,
	96	_PAGE_VALID_SHIFT,
	97	_PAGE_DIRTY_SHIFT,
	98	_CACHE_UNCACHED_SHIFT,
	99	};
1da177e4	100
69497700 PB	101	#else
	102
	103	/* Page table bits used for r4k systems */
	104	enum pgtable_bits {
	105	/* Used only by software (masked out before writing EntryLo) /
	106	_PAGE_PRESENT_SHIFT,
8256b17e	107	#if !defined(CONFIG_CPU_HAS_RIXI)
780602d7	108	_PAGE_NO_READ_SHIFT,
69497700 PB	109	#endif
	110	_PAGE_WRITE_SHIFT,
	111	_PAGE_ACCESSED_SHIFT,
	112	_PAGE_MODIFIED_SHIFT,
	113	#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
	114	_PAGE_HUGE_SHIFT,
	115	#endif
1da177e4	116
69497700	117	/* Used by TLB hardware (placed in EntryLo) /
8256b17e	118	#if defined(CONFIG_CPU_HAS_RIXI)
69497700 PB	119	_PAGE_NO_EXEC_SHIFT,
69497700 PB	120	_PAGE_NO_READ_SHIFT,
69497700 PB	121	#endif
	122	_PAGE_GLOBAL_SHIFT,
	123	_PAGE_VALID_SHIFT,
	124	_PAGE_DIRTY_SHIFT,
	125	_CACHE_SHIFT,
	126	};
1da177e4	127
69497700	128	#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
6dd9344c	129
69497700	130	/* Used only by software */
6dd9344c	131	#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
69497700	132	#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
6dd9344c	133	#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
6dd9344c	134	#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
be0c37c9	135	#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
69497700	136	# define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
be0c37c9	137	#endif
69497700 PB	138
69497700 PB	139	/* Used by TLB hardware (placed in EntryLo) /
7b2cb64f	140	#if defined(CONFIG_XPA)
69497700	141	# define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
8256b17e	142	#elif defined(CONFIG_CPU_HAS_RIXI)
69497700	143	# define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
1cfa8de2	144	#endif
780602d7	145	#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
be0c37c9	146	#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
6dd9344c	147	#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
6dd9344c	148	#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
69497700 PB	149	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
	150	# define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
	151	# define _CACHE_MASK _CACHE_UNCACHED
	152	# define _PFN_SHIFT PAGE_SHIFT
	153	#else
	154	# define _CACHE_MASK (7 << _CACHE_SHIFT)
	155	# define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
	156	#endif
bec50527	157
be0c37c9 SH	158	#ifndef _PAGE_NO_EXEC
	159	#define _PAGE_NO_EXEC 0
	160	#endif
be0c37c9	161
05f9883a SH	162	#define _PAGE_SILENT_READ _PAGE_VALID
	163	#define _PAGE_SILENT_WRITE _PAGE_DIRTY
	164
6dd9344c DD	165	#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
6dd9344c DD	166
be0c37c9 SH	167	/*
	168	* The final layouts of the PTE bits are:
	169	*
	170	* 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
	171	* 32-bit, R1 or earler: CCC D V G M A W R P
	172	* 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
	173	* 32-bit, R2 or later: CCC D V G RI/R XI M A W P
	174	*/
6dd9344c DD	175
6dd9344c DD	176
6dd9344c DD	177	/*
	178	* pte_to_entrylo converts a page table entry (PTE) into a Mips
	179	* entrylo0/1 value.
	180	*/
	181	static inline uint64_t pte_to_entrylo(unsigned long pte_val)
	182	{
8256b17e	183	#ifdef CONFIG_CPU_HAS_RIXI
05857c64	184	if (cpu_has_rixi) {
6dd9344c DD	185	int sa;
	186	#ifdef CONFIG_32BIT
	187	sa = 31 - _PAGE_NO_READ_SHIFT;
	188	#else
	189	sa = 63 - _PAGE_NO_READ_SHIFT;
	190	#endif
	191	/*
	192	* C has no way to express that this is a DSRL
	193	* _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
	194	* in the fast path this is done in assembly
	195	*/
	196	return (pte_val >> _PAGE_GLOBAL_SHIFT) \|
	197	((pte_val & (_PAGE_NO_EXEC \| _PAGE_NO_READ)) << sa);
	198	}
be0c37c9	199	#endif
6dd9344c DD	200
	201	return pte_val >> _PAGE_GLOBAL_SHIFT;
	202	}
bec50527 CD	203
	204	/*
	205	* Cache attributes
	206	*/
	207	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
	208
	209	#define _CACHE_CACHABLE_NONCOHERENT 0
fb020350	210	#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
bec50527 CD	211
bec50527 CD	212	#elif defined(CONFIG_CPU_SB1)
1da177e4 LT	213
	214	/* No penalty for being coherent on the SB1, so just
	215	use it for "noncoherent" spaces, too. Shouldn't hurt. */
	216
bec50527	217	#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
1da177e4	218
152ebb44 HC	219	#elif defined(CONFIG_CPU_LOONGSON3)
	220
	221	/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
	222
152ebb44 HC	223	#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
152ebb44 HC	224	#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
152ebb44	225
f1f5e414	226	#elif defined(CONFIG_MACH_INGENIC)
80bc94d1 MC	227
	228	/* Ingenic uses the WA bit to achieve write-combine memory writes */
	229	#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
	230
fb020350	231	#endif
1da177e4	232
fb020350 MC	233	#ifndef _CACHE_CACHABLE_NO_WA
	234	#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
	235	#endif
	236	#ifndef _CACHE_CACHABLE_WA
	237	#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
	238	#endif
	239	#ifndef _CACHE_UNCACHED
	240	#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
	241	#endif
	242	#ifndef _CACHE_CACHABLE_NONCOHERENT
	243	#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
	244	#endif
	245	#ifndef _CACHE_CACHABLE_CE
	246	#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
	247	#endif
	248	#ifndef _CACHE_CACHABLE_COW
	249	#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
	250	#endif
	251	#ifndef _CACHE_CACHABLE_CUW
	252	#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
	253	#endif
	254	#ifndef _CACHE_UNCACHED_ACCELERATED
	255	#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
1da177e4	256	#endif
1da177e4	257
780602d7	258	#define __READABLE (_PAGE_SILENT_READ \| _PAGE_ACCESSED)
05f9883a	259	#define __WRITEABLE (_PAGE_SILENT_WRITE \| _PAGE_WRITE \| _PAGE_MODIFIED)
1da177e4	260
05f9883a SH	261	#define _PAGE_CHG_MASK (_PAGE_ACCESSED \| _PAGE_MODIFIED \| \
05f9883a SH	262	_PFN_MASK \| _CACHE_MASK)
1da177e4	263
1da177e4	264	#endif /* _ASM_PGTABLE_BITS_H */