[deliverable/linux.git] / arch / mips / include / asm / pgtable-bits.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 - 2002 by Ralf Baechle
 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
 * Copyright (C) 2002  Maciej W. Rozycki
 */
#ifndef _ASM_PGTABLE_BITS_H
#define _ASM_PGTABLE_BITS_H


/*
 * Note that we shift the lower 32bits of each EntryLo[01] entry
 * 6 bits to the left. That way we can convert the PFN into the
 * physical address by a single 'and' operation and gain 6 additional
 * bits for storing information which isn't present in a normal
 * MIPS page table.
 *
 * Similar to the Alpha port, we need to keep track of the ref
 * and mod bits in software.  We have a software "yeah you can read
 * from this page" bit, and a hardware one which actually lets the
 * process read from the page.	On the same token we have a software
 * writable bit and the real hardware one which actually lets the
 * process write to the page, this keeps a mod bit via the hardware
 * dirty bit.
 *
 * Certain revisions of the R4000 and R5000 have a bug where if a
 * certain sequence occurs in the last 3 instructions of an executable
 * page, and the following page is not mapped, the cpu can do
 * unpredictable things.  The code (when it is written) to deal with
 * this problem will be in the update_mmu_cache() code for the r4k.
 */
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)

/*
 * The following bits are implemented by the TLB hardware
 */
#define _PAGE_NO_EXEC_SHIFT	0
#define _PAGE_NO_EXEC		(1 << _PAGE_NO_EXEC_SHIFT)
#define _PAGE_NO_READ_SHIFT	(_PAGE_NO_EXEC_SHIFT + 1)
#define _PAGE_NO_READ		(1 << _PAGE_NO_READ_SHIFT)
#define _PAGE_GLOBAL_SHIFT	(_PAGE_NO_READ_SHIFT + 1)
#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)
#define _PAGE_VALID_SHIFT	(_PAGE_GLOBAL_SHIFT + 1)
#define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
#define _PAGE_DIRTY_SHIFT	(_PAGE_VALID_SHIFT + 1)
#define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)
#define _CACHE_SHIFT		(_PAGE_DIRTY_SHIFT + 1)
#define _CACHE_MASK		(7 << _CACHE_SHIFT)

/*
 * The following bits are implemented in software
 */
#define _PAGE_PRESENT_SHIFT	(24)
#define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)
#define _PAGE_READ_SHIFT	(_PAGE_PRESENT_SHIFT + 1)
#define _PAGE_READ		(1 << _PAGE_READ_SHIFT)
#define _PAGE_WRITE_SHIFT	(_PAGE_READ_SHIFT + 1)
#define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
#define _PAGE_ACCESSED_SHIFT	(_PAGE_WRITE_SHIFT + 1)
#define _PAGE_ACCESSED		(1 << _PAGE_ACCESSED_SHIFT)
#define _PAGE_MODIFIED_SHIFT	(_PAGE_ACCESSED_SHIFT + 1)
#define _PAGE_MODIFIED		(1 << _PAGE_MODIFIED_SHIFT)

#define _PFN_SHIFT		(PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)

/*
 * Bits for extended EntryLo0/EntryLo1 registers
 */
#define _PFNX_MASK		0xffffff

#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

/*
 * The following bits are implemented in software
 */
#define _PAGE_PRESENT_SHIFT	(0)
#define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)
#define _PAGE_READ_SHIFT	(_PAGE_PRESENT_SHIFT + 1)
#define _PAGE_READ		(1 << _PAGE_READ_SHIFT)
#define _PAGE_WRITE_SHIFT	(_PAGE_READ_SHIFT + 1)
#define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
#define _PAGE_ACCESSED_SHIFT	(_PAGE_WRITE_SHIFT + 1)
#define _PAGE_ACCESSED		(1 << _PAGE_ACCESSED_SHIFT)
#define _PAGE_MODIFIED_SHIFT	(_PAGE_ACCESSED_SHIFT + 1)
#define _PAGE_MODIFIED		(1 << _PAGE_MODIFIED_SHIFT)

/*
 * The following bits are implemented by the TLB hardware
 */
#define _PAGE_GLOBAL_SHIFT	(_PAGE_MODIFIED_SHIFT + 4)
#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)
#define _PAGE_VALID_SHIFT	(_PAGE_GLOBAL_SHIFT + 1)
#define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
#define _PAGE_DIRTY_SHIFT	(_PAGE_VALID_SHIFT + 1)
#define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)
#define _CACHE_UNCACHED_SHIFT	(_PAGE_DIRTY_SHIFT + 1)
#define _CACHE_UNCACHED		(1 << _CACHE_UNCACHED_SHIFT)
#define _CACHE_MASK		_CACHE_UNCACHED

#define _PFN_SHIFT		PAGE_SHIFT

#else
/*
 * Below are the "Normal" R4K cases
 */

/*
 * The following bits are implemented in software
 */
#define _PAGE_PRESENT_SHIFT	0
#define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)
/* R2 or later cores check for RI/XI support to determine _PAGE_READ */
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
#define _PAGE_WRITE_SHIFT	(_PAGE_PRESENT_SHIFT + 1)
#define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
#else
#define _PAGE_READ_SHIFT	(_PAGE_PRESENT_SHIFT + 1)
#define _PAGE_READ		(1 << _PAGE_READ_SHIFT)
#define _PAGE_WRITE_SHIFT	(_PAGE_READ_SHIFT + 1)
#define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
#endif
#define _PAGE_ACCESSED_SHIFT	(_PAGE_WRITE_SHIFT + 1)
#define _PAGE_ACCESSED		(1 << _PAGE_ACCESSED_SHIFT)
#define _PAGE_MODIFIED_SHIFT	(_PAGE_ACCESSED_SHIFT + 1)
#define _PAGE_MODIFIED		(1 << _PAGE_MODIFIED_SHIFT)

#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
/* Huge TLB page */
#define _PAGE_HUGE_SHIFT	(_PAGE_MODIFIED_SHIFT + 1)
#define _PAGE_HUGE		(1 << _PAGE_HUGE_SHIFT)
#define _PAGE_SPLITTING_SHIFT	(_PAGE_HUGE_SHIFT + 1)
#define _PAGE_SPLITTING		(1 << _PAGE_SPLITTING_SHIFT)
#endif	/* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
/* XI - page cannot be executed */
#ifdef _PAGE_SPLITTING_SHIFT
#define _PAGE_NO_EXEC_SHIFT	(_PAGE_SPLITTING_SHIFT + 1)
#else
#define _PAGE_NO_EXEC_SHIFT	(_PAGE_MODIFIED_SHIFT + 1)
#endif
#define _PAGE_NO_EXEC		(cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)

/* RI - page cannot be read */
#define _PAGE_READ_SHIFT	(_PAGE_NO_EXEC_SHIFT + 1)
#define _PAGE_READ		(cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
#define _PAGE_NO_READ_SHIFT	_PAGE_READ_SHIFT
#define _PAGE_NO_READ		(cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
#endif	/* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */

#if defined(_PAGE_NO_READ_SHIFT)
#define _PAGE_GLOBAL_SHIFT	(_PAGE_NO_READ_SHIFT + 1)
#elif defined(_PAGE_SPLITTING_SHIFT)
#define _PAGE_GLOBAL_SHIFT	(_PAGE_SPLITTING_SHIFT + 1)
#else
#define _PAGE_GLOBAL_SHIFT	(_PAGE_MODIFIED_SHIFT + 1)
#endif
#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)

#define _PAGE_VALID_SHIFT	(_PAGE_GLOBAL_SHIFT + 1)
#define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
#define _PAGE_DIRTY_SHIFT	(_PAGE_VALID_SHIFT + 1)
#define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)
#define _CACHE_SHIFT		(_PAGE_DIRTY_SHIFT + 1)
#define _CACHE_MASK		(7 << _CACHE_SHIFT)

#define _PFN_SHIFT		(PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)

#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */

#ifndef _PAGE_NO_EXEC
#define _PAGE_NO_EXEC		0
#endif
#ifndef _PAGE_NO_READ
#define _PAGE_NO_READ		0
#endif

#define _PAGE_SILENT_READ	_PAGE_VALID
#define _PAGE_SILENT_WRITE	_PAGE_DIRTY

#define _PFN_MASK		(~((1 << (_PFN_SHIFT)) - 1))

/*
 * The final layouts of the PTE bits are:
 *
 *   64-bit, R1 or earlier:     CCC D V G [S H] M A W R P
 *   32-bit, R1 or earler:      CCC D V G M A W R P
 *   64-bit, R2 or later:       CCC D V G RI/R XI [S H] M A W P
 *   32-bit, R2 or later:       CCC D V G RI/R XI M A W P
 */


#ifndef __ASSEMBLY__
/*
 * pte_to_entrylo converts a page table entry (PTE) into a Mips
 * entrylo0/1 value.
 */
static inline uint64_t pte_to_entrylo(unsigned long pte_val)
{
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
	if (cpu_has_rixi) {
		int sa;
#ifdef CONFIG_32BIT
		sa = 31 - _PAGE_NO_READ_SHIFT;
#else
		sa = 63 - _PAGE_NO_READ_SHIFT;
#endif
		/*
		 * C has no way to express that this is a DSRL
		 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2.  Luckily
		 * in the fast path this is done in assembly
		 */
		return (pte_val >> _PAGE_GLOBAL_SHIFT) |
			((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
	}
#endif

	return pte_val >> _PAGE_GLOBAL_SHIFT;
}
#endif

/*
 * Cache attributes
 */
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

#define _CACHE_CACHABLE_NONCOHERENT 0
#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED

#elif defined(CONFIG_CPU_SB1)

/* No penalty for being coherent on the SB1, so just
   use it for "noncoherent" spaces, too.  Shouldn't hurt. */

#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)

#elif defined(CONFIG_CPU_LOONGSON3)

/* Using COHERENT flag for NONCOHERENT doesn't hurt. */

#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
#define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */

#elif defined(CONFIG_MACH_INGENIC)

/* Ingenic uses the WA bit to achieve write-combine memory writes */
#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)

#endif

#ifndef _CACHE_CACHABLE_NO_WA
#define _CACHE_CACHABLE_NO_WA		(0<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_WA
#define _CACHE_CACHABLE_WA		(1<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_UNCACHED
#define _CACHE_UNCACHED			(2<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_NONCOHERENT
#define _CACHE_CACHABLE_NONCOHERENT	(3<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_CE
#define _CACHE_CACHABLE_CE		(4<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_COW
#define _CACHE_CACHABLE_COW		(5<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_CUW
#define _CACHE_CACHABLE_CUW		(6<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_UNCACHED_ACCELERATED
#define _CACHE_UNCACHED_ACCELERATED	(7<<_CACHE_SHIFT)
#endif

#define __READABLE	(_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
#define __WRITEABLE	(_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)

#define _PAGE_CHG_MASK	(_PAGE_ACCESSED | _PAGE_MODIFIED |	\
			 _PFN_MASK | _CACHE_MASK)

#endif /* _ASM_PGTABLE_BITS_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 - 2002 by Ralf Baechle
	7	* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
	8	* Copyright (C) 2002 Maciej W. Rozycki
	9	*/
	10	#ifndef _ASM_PGTABLE_BITS_H
	11	#define _ASM_PGTABLE_BITS_H
	12
1da177e4 LT	13
	14	/*
	15	* Note that we shift the lower 32bits of each EntryLo[01] entry
	16	* 6 bits to the left. That way we can convert the PFN into the
	17	* physical address by a single 'and' operation and gain 6 additional
	18	* bits for storing information which isn't present in a normal
	19	* MIPS page table.
	20	*
	21	* Similar to the Alpha port, we need to keep track of the ref
	22	* and mod bits in software. We have a software "yeah you can read
	23	* from this page" bit, and a hardware one which actually lets the
70342287	24	* process read from the page. On the same token we have a software
1da177e4 LT	25	* writable bit and the real hardware one which actually lets the
	26	* process write to the page, this keeps a mod bit via the hardware
	27	* dirty bit.
	28	*
	29	* Certain revisions of the R4000 and R5000 have a bug where if a
	30	* certain sequence occurs in the last 3 instructions of an executable
	31	* page, and the following page is not mapped, the cpu can do
	32	* unpredictable things. The code (when it is written) to deal with
	33	* this problem will be in the update_mmu_cache() code for the r4k.
	34	*/
34adb28d	35	#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
1da177e4	36
a2c763e0	37	/*
05f9883a	38	* The following bits are implemented by the TLB hardware
a2c763e0	39	*/
c5b36783 SH	40	#define _PAGE_NO_EXEC_SHIFT 0
	41	#define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
	42	#define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
	43	#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
	44	#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
77a5c593 SH	45	#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
77a5c593 SH	46	#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
a2c763e0	47	#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
77a5c593 SH	48	#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
	49	#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
	50	#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
	51	#define _CACHE_MASK (7 << _CACHE_SHIFT)
a2c763e0 RB	52
	53	/*
	54	* The following bits are implemented in software
82de378c	55	*/
c5b36783	56	#define _PAGE_PRESENT_SHIFT (24)
a2c763e0	57	#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
77a5c593	58	#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
a2c763e0	59	#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
77a5c593	60	#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
a2c763e0	61	#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
77a5c593	62	#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
a2c763e0	63	#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
77a5c593	64	#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
a2c763e0	65	#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
1da177e4	66
77a5c593	67	#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
1da177e4	68
c5b36783 SH	69	/*
	70	* Bits for extended EntryLo0/EntryLo1 registers
	71	*/
	72	#define _PFNX_MASK 0xffffff
	73
6dd9344c	74	#elif defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
1da177e4	75
a2c763e0	76	/*
05f9883a	77	* The following bits are implemented in software
a2c763e0	78	*/
05f9883a SH	79	#define _PAGE_PRESENT_SHIFT (0)
	80	#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
	81	#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
	82	#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
	83	#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
	84	#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
	85	#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
	86	#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
	87	#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
	88	#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
1da177e4	89
a2c763e0	90	/*
05f9883a	91	* The following bits are implemented by the TLB hardware
a2c763e0	92	*/
05f9883a SH	93	#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4)
	94	#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
	95	#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
	96	#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
	97	#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
a2c763e0	98	#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
05f9883a	99	#define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1)
a2c763e0	100	#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
05f9883a	101	#define _CACHE_MASK _CACHE_UNCACHED
1da177e4	102
05f9883a	103	#define _PFN_SHIFT PAGE_SHIFT
1da177e4	104
05f9883a	105	#else
6dd9344c	106	/*
be0c37c9	107	* Below are the "Normal" R4K cases
6dd9344c DD	108	*/
6dd9344c DD	109
a2c763e0 RB	110	/*
a2c763e0 RB	111	* The following bits are implemented in software
a2c763e0	112	*/
05f9883a	113	#define _PAGE_PRESENT_SHIFT 0
6dd9344c	114	#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
be0c37c9	115	/* R2 or later cores check for RI/XI support to determine _PAGE_READ */
d7b63141	116	#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_MIPSR6)
be0c37c9 SH	117	#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
	118	#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
	119	#else
	120	#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
	121	#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
6dd9344c DD	122	#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
6dd9344c DD	123	#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
be0c37c9	124	#endif
6dd9344c DD	125	#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
6dd9344c DD	126	#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
6dd9344c DD	127	#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
6dd9344c DD	128	#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
6dd9344c	129
be0c37c9 SH	130	#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
be0c37c9 SH	131	/* Huge TLB page */
6dd9344c DD	132	#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
6dd9344c DD	133	#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
970d032f RB	134	#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
970d032f RB	135	#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
be0c37c9	136	#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
970d032f	137
d7b63141	138	#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_MIPSR6)
be0c37c9	139	/* XI - page cannot be executed */
1cfa8de2 MR	140	#ifdef _PAGE_SPLITTING_SHIFT
	141	#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
	142	#else
be0c37c9 SH	143	#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
	144	#endif
	145	#define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
6dd9344c	146
be0c37c9 SH	147	/* RI - page cannot be read */
	148	#define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
	149	#define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
	150	#define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
	151	#define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
1cfa8de2	152	#endif /* defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_MIPSR6) */
6dd9344c	153
1cfa8de2	154	#if defined(_PAGE_NO_READ_SHIFT)
6dd9344c	155	#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
1cfa8de2 MR	156	#elif defined(_PAGE_SPLITTING_SHIFT)
	157	#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
	158	#else
be0c37c9	159	#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
1cfa8de2	160	#endif
be0c37c9	161	#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
be0c37c9	162
6dd9344c DD	163	#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
6dd9344c DD	164	#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
6dd9344c DD	165	#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
6dd9344c DD	166	#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
6dd9344c DD	167	#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
	168	#define _CACHE_MASK (7 << _CACHE_SHIFT)
	169
	170	#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
1da177e4	171
34adb28d	172	#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
bec50527	173
be0c37c9 SH	174	#ifndef _PAGE_NO_EXEC
	175	#define _PAGE_NO_EXEC 0
	176	#endif
	177	#ifndef _PAGE_NO_READ
	178	#define _PAGE_NO_READ 0
	179	#endif
	180
05f9883a SH	181	#define _PAGE_SILENT_READ _PAGE_VALID
	182	#define _PAGE_SILENT_WRITE _PAGE_DIRTY
	183
6dd9344c DD	184	#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
6dd9344c DD	185
be0c37c9 SH	186	/*
	187	* The final layouts of the PTE bits are:
	188	*
	189	* 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
	190	* 32-bit, R1 or earler: CCC D V G M A W R P
	191	* 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
	192	* 32-bit, R2 or later: CCC D V G RI/R XI M A W P
	193	*/
6dd9344c DD	194
	195
	196	#ifndef __ASSEMBLY__
	197	/*
	198	* pte_to_entrylo converts a page table entry (PTE) into a Mips
	199	* entrylo0/1 value.
	200	*/
	201	static inline uint64_t pte_to_entrylo(unsigned long pte_val)
	202	{
d7b63141	203	#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_MIPSR6)
05857c64	204	if (cpu_has_rixi) {
6dd9344c DD	205	int sa;
	206	#ifdef CONFIG_32BIT
	207	sa = 31 - _PAGE_NO_READ_SHIFT;
	208	#else
	209	sa = 63 - _PAGE_NO_READ_SHIFT;
	210	#endif
	211	/*
	212	* C has no way to express that this is a DSRL
	213	* _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
	214	* in the fast path this is done in assembly
	215	*/
	216	return (pte_val >> _PAGE_GLOBAL_SHIFT) \|
	217	((pte_val & (_PAGE_NO_EXEC \| _PAGE_NO_READ)) << sa);
	218	}
be0c37c9	219	#endif
6dd9344c DD	220
	221	return pte_val >> _PAGE_GLOBAL_SHIFT;
	222	}
	223	#endif
bec50527 CD	224
	225	/*
	226	* Cache attributes
	227	*/
	228	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
	229
	230	#define _CACHE_CACHABLE_NONCOHERENT 0
fb020350	231	#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
bec50527 CD	232
bec50527 CD	233	#elif defined(CONFIG_CPU_SB1)
1da177e4 LT	234
	235	/* No penalty for being coherent on the SB1, so just
	236	use it for "noncoherent" spaces, too. Shouldn't hurt. */
	237
bec50527	238	#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
1da177e4	239
152ebb44 HC	240	#elif defined(CONFIG_CPU_LOONGSON3)
	241
	242	/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
	243
152ebb44 HC	244	#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
152ebb44 HC	245	#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
152ebb44	246
f1f5e414	247	#elif defined(CONFIG_MACH_INGENIC)
80bc94d1 MC	248
	249	/* Ingenic uses the WA bit to achieve write-combine memory writes */
	250	#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
	251
fb020350	252	#endif
1da177e4	253
fb020350 MC	254	#ifndef _CACHE_CACHABLE_NO_WA
	255	#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
	256	#endif
	257	#ifndef _CACHE_CACHABLE_WA
	258	#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
	259	#endif
	260	#ifndef _CACHE_UNCACHED
	261	#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
	262	#endif
	263	#ifndef _CACHE_CACHABLE_NONCOHERENT
	264	#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
	265	#endif
	266	#ifndef _CACHE_CACHABLE_CE
	267	#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
	268	#endif
	269	#ifndef _CACHE_CACHABLE_COW
	270	#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
	271	#endif
	272	#ifndef _CACHE_CACHABLE_CUW
	273	#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
	274	#endif
	275	#ifndef _CACHE_UNCACHED_ACCELERATED
	276	#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
1da177e4	277	#endif
1da177e4	278
be0c37c9	279	#define __READABLE (_PAGE_SILENT_READ \| _PAGE_READ \| _PAGE_ACCESSED)
05f9883a	280	#define __WRITEABLE (_PAGE_SILENT_WRITE \| _PAGE_WRITE \| _PAGE_MODIFIED)
1da177e4	281
05f9883a SH	282	#define _PAGE_CHG_MASK (_PAGE_ACCESSED \| _PAGE_MODIFIED \| \
05f9883a SH	283	_PFN_MASK \| _CACHE_MASK)
1da177e4	284
1da177e4	285	#endif /* _ASM_PGTABLE_BITS_H */