[deliverable/linux.git] / arch / mips / include / asm / pgtable-bits.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 - 2002 by Ralf Baechle
 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
 * Copyright (C) 2002  Maciej W. Rozycki
 */
#ifndef _ASM_PGTABLE_BITS_H
#define _ASM_PGTABLE_BITS_H


/*
 * Note that we shift the lower 32bits of each EntryLo[01] entry
 * 6 bits to the left. That way we can convert the PFN into the
 * physical address by a single 'and' operation and gain 6 additional
 * bits for storing information which isn't present in a normal
 * MIPS page table.
 *
 * Similar to the Alpha port, we need to keep track of the ref
 * and mod bits in software.  We have a software "yeah you can read
 * from this page" bit, and a hardware one which actually lets the
 * process read from the page.  On the same token we have a software
 * writable bit and the real hardware one which actually lets the
 * process write to the page, this keeps a mod bit via the hardware
 * dirty bit.
 *
 * Certain revisions of the R4000 and R5000 have a bug where if a
 * certain sequence occurs in the last 3 instructions of an executable
 * page, and the following page is not mapped, the cpu can do
 * unpredictable things.  The code (when it is written) to deal with
 * this problem will be in the update_mmu_cache() code for the r4k.
 */
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)

/*
 * The following bits are directly used by the TLB hardware
 */
#define _PAGE_R4KBUG		(1 << 0)  /* workaround for r4k bug  */
#define _PAGE_GLOBAL		(1 << 0)
#define _PAGE_VALID_SHIFT	1
#define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
#define _PAGE_SILENT_READ	(1 << 1)  /* synonym                 */
#define _PAGE_DIRTY_SHIFT	2
#define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)  /* The MIPS dirty bit      */
#define _PAGE_SILENT_WRITE	(1 << 2)
#define _CACHE_SHIFT		3
#define _CACHE_MASK		(7 << 3)

/*
 * The following bits are implemented in software
 *
 * _PAGE_FILE semantics: set:pagecache unset:swap
 */ 
#define _PAGE_PRESENT_SHIFT	6
#define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)
#define _PAGE_READ_SHIFT	7
#define _PAGE_READ		(1 << _PAGE_READ_SHIFT)
#define _PAGE_WRITE_SHIFT	8
#define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
#define _PAGE_ACCESSED_SHIFT	9
#define _PAGE_ACCESSED		(1 << _PAGE_ACCESSED_SHIFT)
#define _PAGE_MODIFIED_SHIFT	10
#define _PAGE_MODIFIED		(1 << _PAGE_MODIFIED_SHIFT)

#define _PAGE_FILE		(1 << 10)

#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

/*
 * The following are implemented by software
 *
 * _PAGE_FILE semantics: set:pagecache unset:swap
 */
#define _PAGE_PRESENT_SHIFT	0
#define _PAGE_PRESENT		(1 <<  _PAGE_PRESENT_SHIFT)
#define _PAGE_READ_SHIFT	1
#define _PAGE_READ		(1 <<  _PAGE_READ_SHIFT)
#define _PAGE_WRITE_SHIFT	2
#define _PAGE_WRITE		(1 <<  _PAGE_WRITE_SHIFT)
#define _PAGE_ACCESSED_SHIFT	3
#define _PAGE_ACCESSED		(1 <<  _PAGE_ACCESSED_SHIFT)
#define _PAGE_MODIFIED_SHIFT	4
#define _PAGE_MODIFIED		(1 <<  _PAGE_MODIFIED_SHIFT)
#define _PAGE_FILE_SHIFT	4
#define _PAGE_FILE		(1 <<  _PAGE_FILE_SHIFT)

/*
 * And these are the hardware TLB bits
 */
#define _PAGE_GLOBAL_SHIFT	8
#define _PAGE_GLOBAL		(1 <<  _PAGE_GLOBAL_SHIFT)
#define _PAGE_VALID_SHIFT	9
#define _PAGE_VALID		(1 <<  _PAGE_VALID_SHIFT)
#define _PAGE_SILENT_READ	(1 <<  _PAGE_VALID_SHIFT)	/* synonym  */
#define _PAGE_DIRTY_SHIFT	10
#define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)
#define _PAGE_SILENT_WRITE	(1 << _PAGE_DIRTY_SHIFT)
#define _CACHE_UNCACHED_SHIFT	11
#define _CACHE_UNCACHED		(1 << _CACHE_UNCACHED_SHIFT)
#define _CACHE_MASK		(1 << _CACHE_UNCACHED_SHIFT)

#else /* 'Normal' r4K case */
/*
 * When using the RI/XI bit support, we have 13 bits of flags below
 * the physical address. The RI/XI bits are placed such that a SRL 5
 * can strip off the software bits, then a ROTR 2 can move the RI/XI
 * into bits [63:62]. This also limits physical address to 56 bits,
 * which is more than we need right now.
 */

/*
 * The following bits are implemented in software
 *
 * _PAGE_READ / _PAGE_READ_SHIFT should be unused if cpu_has_rixi.
 * _PAGE_FILE semantics: set:pagecache unset:swap
 */
#define _PAGE_PRESENT_SHIFT	(0)
#define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)
#define _PAGE_READ_SHIFT	(cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; })
#define _PAGE_WRITE_SHIFT	(_PAGE_READ_SHIFT + 1)
#define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
#define _PAGE_ACCESSED_SHIFT	(_PAGE_WRITE_SHIFT + 1)
#define _PAGE_ACCESSED		(1 << _PAGE_ACCESSED_SHIFT)
#define _PAGE_MODIFIED_SHIFT	(_PAGE_ACCESSED_SHIFT + 1)
#define _PAGE_MODIFIED		(1 << _PAGE_MODIFIED_SHIFT)
#define _PAGE_FILE		(_PAGE_MODIFIED)

#ifdef CONFIG_HUGETLB_PAGE
/* huge tlb page */
#define _PAGE_HUGE_SHIFT	(_PAGE_MODIFIED_SHIFT + 1)
#define _PAGE_HUGE		(1 << _PAGE_HUGE_SHIFT)
#else
#define _PAGE_HUGE_SHIFT	(_PAGE_MODIFIED_SHIFT)
#define _PAGE_HUGE		({BUG(); 1; })  /* Dummy value */
#endif

/* Page cannot be executed */
#define _PAGE_NO_EXEC_SHIFT	(cpu_has_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
#define _PAGE_NO_EXEC		({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; })

/* Page cannot be read */
#define _PAGE_NO_READ_SHIFT	(cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
#define _PAGE_NO_READ		({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; })

#define _PAGE_GLOBAL_SHIFT	(_PAGE_NO_READ_SHIFT + 1)
#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)

#define _PAGE_VALID_SHIFT	(_PAGE_GLOBAL_SHIFT + 1)
#define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
/* synonym                 */
#define _PAGE_SILENT_READ	(_PAGE_VALID)

/* The MIPS dirty bit      */
#define _PAGE_DIRTY_SHIFT	(_PAGE_VALID_SHIFT + 1)
#define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)
#define _PAGE_SILENT_WRITE	(_PAGE_DIRTY)

#define _CACHE_SHIFT		(_PAGE_DIRTY_SHIFT + 1)
#define _CACHE_MASK		(7 << _CACHE_SHIFT)

#define _PFN_SHIFT		(PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)

#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */

#ifndef _PFN_SHIFT
#define _PFN_SHIFT                  PAGE_SHIFT
#endif
#define _PFN_MASK		(~((1 << (_PFN_SHIFT)) - 1))

#ifndef _PAGE_NO_READ
#define _PAGE_NO_READ ({BUG(); 0; })
#define _PAGE_NO_READ_SHIFT ({BUG(); 0; })
#endif
#ifndef _PAGE_NO_EXEC
#define _PAGE_NO_EXEC ({BUG(); 0; })
#endif
#ifndef _PAGE_GLOBAL_SHIFT
#define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL)
#endif


#ifndef __ASSEMBLY__
/*
 * pte_to_entrylo converts a page table entry (PTE) into a Mips
 * entrylo0/1 value.
 */
static inline uint64_t pte_to_entrylo(unsigned long pte_val)
{
	if (cpu_has_rixi) {
		int sa;
#ifdef CONFIG_32BIT
		sa = 31 - _PAGE_NO_READ_SHIFT;
#else
		sa = 63 - _PAGE_NO_READ_SHIFT;
#endif
		/*
		 * C has no way to express that this is a DSRL
		 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2.  Luckily
		 * in the fast path this is done in assembly
		 */
		return (pte_val >> _PAGE_GLOBAL_SHIFT) |
			((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
	}

	return pte_val >> _PAGE_GLOBAL_SHIFT;
}
#endif

/*
 * Cache attributes
 */
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

#define _CACHE_CACHABLE_NONCOHERENT 0

#elif defined(CONFIG_CPU_SB1)

/* No penalty for being coherent on the SB1, so just
   use it for "noncoherent" spaces, too.  Shouldn't hurt. */

#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_COW         (5<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)

#elif defined(CONFIG_CPU_RM9000)

#define _CACHE_WT		    (0<<_CACHE_SHIFT)
#define _CACHE_WTWA		    (1<<_CACHE_SHIFT)
#define _CACHE_UC_B		    (2<<_CACHE_SHIFT)
#define _CACHE_WB		    (3<<_CACHE_SHIFT)
#define _CACHE_CWBEA		    (4<<_CACHE_SHIFT)
#define _CACHE_CWB		    (5<<_CACHE_SHIFT)
#define _CACHE_UCNB		    (6<<_CACHE_SHIFT)
#define _CACHE_FPC		    (7<<_CACHE_SHIFT)

#define _CACHE_UNCACHED		    _CACHE_UC_B
#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB

#else

#define _CACHE_CACHABLE_NO_WA	    (0<<_CACHE_SHIFT)  /* R4600 only      */
#define _CACHE_CACHABLE_WA	    (1<<_CACHE_SHIFT)  /* R4600 only      */
#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)  /* R4[0246]00      */
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* R4[0246]00      */
#define _CACHE_CACHABLE_CE          (4<<_CACHE_SHIFT)  /* R4[04]00MC only */
#define _CACHE_CACHABLE_COW         (5<<_CACHE_SHIFT)  /* R4[04]00MC only */
#define _CACHE_CACHABLE_COHERENT    (5<<_CACHE_SHIFT)  /* MIPS32R2 CMP    */
#define _CACHE_CACHABLE_CUW         (6<<_CACHE_SHIFT)  /* R4[04]00MC only */
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* R10000 only     */

#endif

#define __READABLE	(_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
#define __WRITEABLE	(_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)

#define _PAGE_CHG_MASK  (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)

#endif /* _ASM_PGTABLE_BITS_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 - 2002 by Ralf Baechle
	7	* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
	8	* Copyright (C) 2002 Maciej W. Rozycki
	9	*/
	10	#ifndef _ASM_PGTABLE_BITS_H
	11	#define _ASM_PGTABLE_BITS_H
	12
1da177e4 LT	13
	14	/*
	15	* Note that we shift the lower 32bits of each EntryLo[01] entry
	16	* 6 bits to the left. That way we can convert the PFN into the
	17	* physical address by a single 'and' operation and gain 6 additional
	18	* bits for storing information which isn't present in a normal
	19	* MIPS page table.
	20	*
	21	* Similar to the Alpha port, we need to keep track of the ref
	22	* and mod bits in software. We have a software "yeah you can read
	23	* from this page" bit, and a hardware one which actually lets the
	24	* process read from the page. On the same token we have a software
	25	* writable bit and the real hardware one which actually lets the
	26	* process write to the page, this keeps a mod bit via the hardware
	27	* dirty bit.
	28	*
	29	* Certain revisions of the R4000 and R5000 have a bug where if a
	30	* certain sequence occurs in the last 3 instructions of an executable
	31	* page, and the following page is not mapped, the cpu can do
	32	* unpredictable things. The code (when it is written) to deal with
	33	* this problem will be in the update_mmu_cache() code for the r4k.
	34	*/
962f480e	35	#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
1da177e4	36
a2c763e0 RB	37	/*
	38	* The following bits are directly used by the TLB hardware
	39	*/
	40	#define _PAGE_R4KBUG (1 << 0) /* workaround for r4k bug */
	41	#define _PAGE_GLOBAL (1 << 0)
	42	#define _PAGE_VALID_SHIFT 1
	43	#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
	44	#define _PAGE_SILENT_READ (1 << 1) /* synonym */
	45	#define _PAGE_DIRTY_SHIFT 2
	46	#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) /* The MIPS dirty bit */
	47	#define _PAGE_SILENT_WRITE (1 << 2)
	48	#define _CACHE_SHIFT 3
	49	#define _CACHE_MASK (7 << 3)
	50
	51	/*
	52	* The following bits are implemented in software
	53	*
	54	* _PAGE_FILE semantics: set:pagecache unset:swap
	55	*/
	56	#define _PAGE_PRESENT_SHIFT 6
	57	#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
	58	#define _PAGE_READ_SHIFT 7
	59	#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
	60	#define _PAGE_WRITE_SHIFT 8
	61	#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
	62	#define _PAGE_ACCESSED_SHIFT 9
	63	#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
	64	#define _PAGE_MODIFIED_SHIFT 10
	65	#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
1da177e4	66
a2c763e0	67	#define _PAGE_FILE (1 << 10)
1da177e4	68
6dd9344c	69	#elif defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
1da177e4	70
a2c763e0 RB	71	/*
	72	* The following are implemented by software
	73	*
	74	* _PAGE_FILE semantics: set:pagecache unset:swap
	75	*/
	76	#define _PAGE_PRESENT_SHIFT 0
	77	#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
	78	#define _PAGE_READ_SHIFT 1
	79	#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
	80	#define _PAGE_WRITE_SHIFT 2
	81	#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
	82	#define _PAGE_ACCESSED_SHIFT 3
	83	#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
	84	#define _PAGE_MODIFIED_SHIFT 4
	85	#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
	86	#define _PAGE_FILE_SHIFT 4
	87	#define _PAGE_FILE (1 << _PAGE_FILE_SHIFT)
1da177e4	88
a2c763e0 RB	89	/*
	90	* And these are the hardware TLB bits
	91	*/
	92	#define _PAGE_GLOBAL_SHIFT 8
	93	#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
	94	#define _PAGE_VALID_SHIFT 9
	95	#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
	96	#define _PAGE_SILENT_READ (1 << _PAGE_VALID_SHIFT) /* synonym */
	97	#define _PAGE_DIRTY_SHIFT 10
	98	#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
	99	#define _PAGE_SILENT_WRITE (1 << _PAGE_DIRTY_SHIFT)
	100	#define _CACHE_UNCACHED_SHIFT 11
	101	#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
	102	#define _CACHE_MASK (1 << _CACHE_UNCACHED_SHIFT)
1da177e4	103
6dd9344c DD	104	#else /* 'Normal' r4K case */
	105	/*
	106	* When using the RI/XI bit support, we have 13 bits of flags below
	107	* the physical address. The RI/XI bits are placed such that a SRL 5
	108	* can strip off the software bits, then a ROTR 2 can move the RI/XI
	109	* into bits [63:62]. This also limits physical address to 56 bits,
	110	* which is more than we need right now.
	111	*/
	112
a2c763e0 RB	113	/*
	114	* The following bits are implemented in software
	115	*
	116	* _PAGE_READ / _PAGE_READ_SHIFT should be unused if cpu_has_rixi.
	117	* _PAGE_FILE semantics: set:pagecache unset:swap
	118	*/
6dd9344c DD	119	#define _PAGE_PRESENT_SHIFT (0)
6dd9344c DD	120	#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
05857c64 SH	121	#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
05857c64 SH	122	#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; })
6dd9344c DD	123	#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
6dd9344c DD	124	#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
6dd9344c DD	125	#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
6dd9344c DD	126	#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
6dd9344c DD	127	#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
6dd9344c DD	128	#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
6dd9344c DD	129	#define _PAGE_FILE (_PAGE_MODIFIED)
	130
	131	#ifdef CONFIG_HUGETLB_PAGE
	132	/* huge tlb page */
	133	#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
	134	#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
1da177e4	135	#else
6dd9344c DD	136	#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT)
	137	#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */
	138	#endif
bec50527	139
6dd9344c	140	/* Page cannot be executed */
05857c64 SH	141	#define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
05857c64 SH	142	#define _PAGE_NO_EXEC ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; })
6dd9344c DD	143
6dd9344c DD	144	/* Page cannot be read */
05857c64 SH	145	#define _PAGE_NO_READ_SHIFT (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
05857c64 SH	146	#define _PAGE_NO_READ ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; })
6dd9344c DD	147
	148	#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
	149	#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
	150
	151	#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
	152	#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
	153	/* synonym */
	154	#define _PAGE_SILENT_READ (_PAGE_VALID)
	155
	156	/* The MIPS dirty bit */
	157	#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
	158	#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
	159	#define _PAGE_SILENT_WRITE (_PAGE_DIRTY)
	160
	161	#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
	162	#define _CACHE_MASK (7 << _CACHE_SHIFT)
	163
	164	#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
1da177e4	165
bec50527 CD	166	#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
bec50527 CD	167
6dd9344c DD	168	#ifndef _PFN_SHIFT
	169	#define _PFN_SHIFT PAGE_SHIFT
	170	#endif
	171	#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
	172
	173	#ifndef _PAGE_NO_READ
	174	#define _PAGE_NO_READ ({BUG(); 0; })
	175	#define _PAGE_NO_READ_SHIFT ({BUG(); 0; })
	176	#endif
	177	#ifndef _PAGE_NO_EXEC
	178	#define _PAGE_NO_EXEC ({BUG(); 0; })
	179	#endif
	180	#ifndef _PAGE_GLOBAL_SHIFT
	181	#define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL)
	182	#endif
	183
	184
	185	#ifndef __ASSEMBLY__
	186	/*
	187	* pte_to_entrylo converts a page table entry (PTE) into a Mips
	188	* entrylo0/1 value.
	189	*/
	190	static inline uint64_t pte_to_entrylo(unsigned long pte_val)
	191	{
05857c64	192	if (cpu_has_rixi) {
6dd9344c DD	193	int sa;
	194	#ifdef CONFIG_32BIT
	195	sa = 31 - _PAGE_NO_READ_SHIFT;
	196	#else
	197	sa = 63 - _PAGE_NO_READ_SHIFT;
	198	#endif
	199	/*
	200	* C has no way to express that this is a DSRL
	201	* _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
	202	* in the fast path this is done in assembly
	203	*/
	204	return (pte_val >> _PAGE_GLOBAL_SHIFT) \|
	205	((pte_val & (_PAGE_NO_EXEC \| _PAGE_NO_READ)) << sa);
	206	}
	207
	208	return pte_val >> _PAGE_GLOBAL_SHIFT;
	209	}
	210	#endif
bec50527 CD	211
	212	/*
	213	* Cache attributes
	214	*/
	215	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
	216
	217	#define _CACHE_CACHABLE_NONCOHERENT 0
	218
	219	#elif defined(CONFIG_CPU_SB1)
1da177e4 LT	220
	221	/* No penalty for being coherent on the SB1, so just
	222	use it for "noncoherent" spaces, too. Shouldn't hurt. */
	223
bec50527 CD	224	#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
	225	#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
	226	#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
	227	#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
1da177e4 LT	228
	229	#elif defined(CONFIG_CPU_RM9000)
	230
bec50527 CD	231	#define _CACHE_WT (0<<_CACHE_SHIFT)
	232	#define _CACHE_WTWA (1<<_CACHE_SHIFT)
	233	#define _CACHE_UC_B (2<<_CACHE_SHIFT)
	234	#define _CACHE_WB (3<<_CACHE_SHIFT)
	235	#define _CACHE_CWBEA (4<<_CACHE_SHIFT)
	236	#define _CACHE_CWB (5<<_CACHE_SHIFT)
	237	#define _CACHE_UCNB (6<<_CACHE_SHIFT)
	238	#define _CACHE_FPC (7<<_CACHE_SHIFT)
1da177e4	239
bec50527 CD	240	#define _CACHE_UNCACHED _CACHE_UC_B
bec50527 CD	241	#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
1da177e4 LT	242
	243	#else
	244
bec50527 CD	245	#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
	246	#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */
	247	#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */
	248	#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */
	249	#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */
	250	#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */
	251	#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */
	252	#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */
	253	#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */
1da177e4 LT	254
1da177e4 LT	255	#endif
1da177e4	256
05857c64	257	#define __READABLE (_PAGE_SILENT_READ \| _PAGE_ACCESSED \| (cpu_has_rixi ? 0 : _PAGE_READ))
1da177e4 LT	258	#define __WRITEABLE (_PAGE_WRITE \| _PAGE_SILENT_WRITE \| _PAGE_MODIFIED)
1da177e4 LT	259
6dd9344c	260	#define _PAGE_CHG_MASK (_PFN_MASK \| _PAGE_ACCESSED \| _PAGE_MODIFIED \| _CACHE_MASK)
1da177e4	261
1da177e4	262	#endif /* _ASM_PGTABLE_BITS_H */