[deliverable/linux.git] / arch / mips / include / asm / processor.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 Waldorf GMBH
 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 Paul M. Antoine
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 */
#ifndef _ASM_PROCESSOR_H
#define _ASM_PROCESSOR_H

#include <linux/atomic.h>
#include <linux/cpumask.h>
#include <linux/threads.h>

#include <asm/cachectl.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <asm/dsemul.h>
#include <asm/mipsregs.h>
#include <asm/prefetch.h>

/*
 * Return current * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

/*
 * System setup and hardware flags..
 */

extern unsigned int vced_count, vcei_count;

/*
 * MIPS does have an arch_pick_mmap_layout()
 */
#define HAVE_ARCH_PICK_MMAP_LAYOUT 1

#ifdef CONFIG_32BIT
#ifdef CONFIG_KVM_GUEST
/* User space process size is limited to 1GB in KVM Guest Mode */
#define TASK_SIZE	0x3fff8000UL
#else
/*
 * User space process size: 2GB. This is hardcoded into a few places,
 * so don't change it unless you know what you are doing.
 */
#define TASK_SIZE	0x80000000UL
#endif

#define STACK_TOP_MAX	TASK_SIZE

#define TASK_IS_32BIT_ADDR 1

#endif

#ifdef CONFIG_64BIT
/*
 * User space process size: 1TB. This is hardcoded into a few places,
 * so don't change it unless you know what you are doing.  TASK_SIZE
 * is limited to 1TB by the R4000 architecture; R10000 and better can
 * support 16TB; the architectural reserve for future expansion is
 * 8192EB ...
 */
#define TASK_SIZE32	0x7fff8000UL
#ifdef CONFIG_MIPS_VA_BITS_48
#define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
#else
#define TASK_SIZE64     0x10000000000UL
#endif
#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
#define STACK_TOP_MAX	TASK_SIZE64

#define TASK_SIZE_OF(tsk)						\
	(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)

#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)

#endif

/*
 * One page above the stack is used for branch delay slot "emulation".
 * See dsemul.c for details.
 */
#define STACK_TOP	((TASK_SIZE & PAGE_MASK) - PAGE_SIZE)

/*
 * This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)


#define NUM_FPU_REGS	32

#ifdef CONFIG_CPU_HAS_MSA
# define FPU_REG_WIDTH	128
#else
# define FPU_REG_WIDTH	64
#endif

union fpureg {
	__u32	val32[FPU_REG_WIDTH / 32];
	__u64	val64[FPU_REG_WIDTH / 64];
};

#ifdef CONFIG_CPU_LITTLE_ENDIAN
# define FPR_IDX(width, idx)	(idx)
#else
# define FPR_IDX(width, idx)	((idx) ^ ((64 / (width)) - 1))
#endif

#define BUILD_FPR_ACCESS(width) \
static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)	\
{									\
	return fpr->val##width[FPR_IDX(width, idx)];			\
}									\
									\
static inline void set_fpr##width(union fpureg *fpr, unsigned idx,	\
				  u##width val)				\
{									\
	fpr->val##width[FPR_IDX(width, idx)] = val;			\
}

BUILD_FPR_ACCESS(32)
BUILD_FPR_ACCESS(64)

/*
 * It would be nice to add some more fields for emulator statistics,
 * the additional information is private to the FPU emulator for now.
 * See arch/mips/include/asm/fpu_emulator.h.
 */

struct mips_fpu_struct {
	union fpureg	fpr[NUM_FPU_REGS];
	unsigned int	fcr31;
	unsigned int	msacsr;
};

#define NUM_DSP_REGS   6

typedef __u32 dspreg_t;

struct mips_dsp_state {
	dspreg_t	dspr[NUM_DSP_REGS];
	unsigned int	dspcontrol;
};

#define INIT_CPUMASK { \
	{0,} \
}

struct mips3264_watch_reg_state {
	/* The width of watchlo is 32 in a 32 bit kernel and 64 in a
	   64 bit kernel.  We use unsigned long as it has the same
	   property. */
	unsigned long watchlo[NUM_WATCH_REGS];
	/* Only the mask and IRW bits from watchhi. */
	u16 watchhi[NUM_WATCH_REGS];
};

union mips_watch_reg_state {
	struct mips3264_watch_reg_state mips3264;
};

#if defined(CONFIG_CPU_CAVIUM_OCTEON)

struct octeon_cop2_state {
	/* DMFC2 rt, 0x0201 */
	unsigned long	cop2_crc_iv;
	/* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
	unsigned long	cop2_crc_length;
	/* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
	unsigned long	cop2_crc_poly;
	/* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
	unsigned long	cop2_llm_dat[2];
       /* DMFC2 rt, 0x0084 */
	unsigned long	cop2_3des_iv;
	/* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
	unsigned long	cop2_3des_key[3];
	/* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
	unsigned long	cop2_3des_result;
	/* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
	unsigned long	cop2_aes_inp0;
	/* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
	unsigned long	cop2_aes_iv[2];
	/* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
	 * rt, 0x0107 */
	unsigned long	cop2_aes_key[4];
	/* DMFC2 rt, 0x0110 */
	unsigned long	cop2_aes_keylen;
	/* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
	unsigned long	cop2_aes_result[2];
	/* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
	 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
	 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
	 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
	 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
	unsigned long	cop2_hsh_datw[15];
	/* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
	 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
	 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
	unsigned long	cop2_hsh_ivw[8];
	/* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
	unsigned long	cop2_gfm_mult[2];
	/* DMFC2 rt, 0x025E - Pass2 */
	unsigned long	cop2_gfm_poly;
	/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
	unsigned long	cop2_gfm_result[2];
	/* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
	unsigned long	cop2_sha3[2];
};
#define COP2_INIT						\
	.cp2			= {0,},

struct octeon_cvmseg_state {
	unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
			    [cpu_dcache_line_size() / sizeof(unsigned long)];
};

#elif defined(CONFIG_CPU_XLP)
struct nlm_cop2_state {
	u64	rx[4];
	u64	tx[4];
	u32	tx_msg_status;
	u32	rx_msg_status;
};

#define COP2_INIT						\
	.cp2			= {{0}, {0}, 0, 0},
#else
#define COP2_INIT
#endif

typedef struct {
	unsigned long seg;
} mm_segment_t;

#ifdef CONFIG_CPU_HAS_MSA
# define ARCH_MIN_TASKALIGN	16
# define FPU_ALIGN		__aligned(16)
#else
# define ARCH_MIN_TASKALIGN	8
# define FPU_ALIGN
#endif

struct mips_abi;

/*
 * If you change thread_struct remember to change the #defines below too!
 */
struct thread_struct {
	/* Saved main processor registers. */
	unsigned long reg16;
	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
	unsigned long reg29, reg30, reg31;

	/* Saved cp0 stuff. */
	unsigned long cp0_status;

	/* Saved fpu/fpu emulator stuff. */
	struct mips_fpu_struct fpu FPU_ALIGN;
	/* Assigned branch delay slot 'emulation' frame */
	atomic_t bd_emu_frame;
	/* PC of the branch from a branch delay slot 'emulation' */
	unsigned long bd_emu_branch_pc;
	/* PC to continue from following a branch delay slot 'emulation' */
	unsigned long bd_emu_cont_pc;
#ifdef CONFIG_MIPS_MT_FPAFF
	/* Emulated instruction count */
	unsigned long emulated_fp;
	/* Saved per-thread scheduler affinity mask */
	cpumask_t user_cpus_allowed;
#endif /* CONFIG_MIPS_MT_FPAFF */

	/* Saved state of the DSP ASE, if available. */
	struct mips_dsp_state dsp;

	/* Saved watch register state, if available. */
	union mips_watch_reg_state watch;

	/* Other stuff associated with the thread. */
	unsigned long cp0_badvaddr;	/* Last user fault */
	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
	unsigned long error_code;
	unsigned long trap_nr;
#ifdef CONFIG_CPU_CAVIUM_OCTEON
	struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
	struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
#endif
#ifdef CONFIG_CPU_XLP
	struct nlm_cop2_state cp2;
#endif
	struct mips_abi *abi;
};

#ifdef CONFIG_MIPS_MT_FPAFF
#define FPAFF_INIT						\
	.emulated_fp			= 0,			\
	.user_cpus_allowed		= INIT_CPUMASK,
#else
#define FPAFF_INIT
#endif /* CONFIG_MIPS_MT_FPAFF */

#define INIT_THREAD  {						\
	/*							\
	 * Saved main processor registers			\
	 */							\
	.reg16			= 0,				\
	.reg17			= 0,				\
	.reg18			= 0,				\
	.reg19			= 0,				\
	.reg20			= 0,				\
	.reg21			= 0,				\
	.reg22			= 0,				\
	.reg23			= 0,				\
	.reg29			= 0,				\
	.reg30			= 0,				\
	.reg31			= 0,				\
	/*							\
	 * Saved cp0 stuff					\
	 */							\
	.cp0_status		= 0,				\
	/*							\
	 * Saved FPU/FPU emulator stuff				\
	 */							\
	.fpu			= {				\
		.fpr		= {{{0,},},},			\
		.fcr31		= 0,				\
		.msacsr		= 0,				\
	},							\
	/*							\
	 * FPU affinity state (null if not FPAFF)		\
	 */							\
	FPAFF_INIT						\
	/* Delay slot emulation */				\
	.bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE),		\
	.bd_emu_branch_pc = 0,					\
	.bd_emu_cont_pc = 0,					\
	/*							\
	 * Saved DSP stuff					\
	 */							\
	.dsp			= {				\
		.dspr		= {0, },			\
		.dspcontrol	= 0,				\
	},							\
	/*							\
	 * saved watch register stuff				\
	 */							\
	.watch = {{{0,},},},					\
	/*							\
	 * Other stuff associated with the process		\
	 */							\
	.cp0_badvaddr		= 0,				\
	.cp0_baduaddr		= 0,				\
	.error_code		= 0,				\
	.trap_nr		= 0,				\
	/*							\
	 * Platform specific cop2 registers(null if no COP2)	\
	 */							\
	COP2_INIT						\
}

struct task_struct;

/* Free all resources held by a thread. */
#define release_thread(thread) do { } while(0)

extern unsigned long thread_saved_pc(struct task_struct *tsk);

/*
 * Do necessary setup to start up a newly executed thread.
 */
extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);

static inline void flush_thread(void)
{
}

unsigned long get_wchan(struct task_struct *p);

#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
			 THREAD_SIZE - 32 - sizeof(struct pt_regs))
#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)

#define cpu_relax()	barrier()
#define cpu_relax_lowlatency() cpu_relax()

/*
 * Return_address is a replacement for __builtin_return_address(count)
 * which on certain architectures cannot reasonably be implemented in GCC
 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
 * Note that __builtin_return_address(x>=1) is forbidden because GCC
 * aborts compilation on some CPUs.  It's simply not possible to unwind
 * some CPU's stackframes.
 *
 * __builtin_return_address works only for non-leaf functions.	We avoid the
 * overhead of a function call by forcing the compiler to save the return
 * address register on the stack.
 */
#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})

#ifdef CONFIG_CPU_HAS_PREFETCH

#define ARCH_HAS_PREFETCH
#define prefetch(x) __builtin_prefetch((x), 0, 1)

#define ARCH_HAS_PREFETCHW
#define prefetchw(x) __builtin_prefetch((x), 1, 1)

#endif

/*
 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
 * to the prctl syscall.
 */
extern int mips_get_process_fp_mode(struct task_struct *task);
extern int mips_set_process_fp_mode(struct task_struct *task,
				    unsigned int value);

#define GET_FP_MODE(task)		mips_get_process_fp_mode(task)
#define SET_FP_MODE(task,value)		mips_set_process_fp_mode(task, value)

#endif /* _ASM_PROCESSOR_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 Waldorf GMBH
	7	* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
	8	* Copyright (C) 1996 Paul M. Antoine
	9	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
	10	*/
	11	#ifndef _ASM_PROCESSOR_H
	12	#define _ASM_PROCESSOR_H
	13
432c6bac	14	#include <linux/atomic.h>
41c594ab	15	#include <linux/cpumask.h>
1da177e4 LT	16	#include <linux/threads.h>
	17
	18	#include <asm/cachectl.h>
	19	#include <asm/cpu.h>
	20	#include <asm/cpu-info.h>
432c6bac	21	#include <asm/dsemul.h>
1da177e4 LT	22	#include <asm/mipsregs.h>
1da177e4 LT	23	#include <asm/prefetch.h>
1da177e4 LT	24
	25	/*
	26	* Return current * instruction pointer ("program counter").
	27	*/
	28	#define current_text_addr() ({ __label__ _l; _l: &&_l;})
	29
	30	/*
	31	* System setup and hardware flags..
	32	*/
1da177e4 LT	33
	34	extern unsigned int vced_count, vcei_count;
	35
1091458d DD	36	/*
	37	* MIPS does have an arch_pick_mmap_layout()
	38	*/
	39	#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
	40
875d43e7	41	#ifdef CONFIG_32BIT
9843b030 SL	42	#ifdef CONFIG_KVM_GUEST
	43	/* User space process size is limited to 1GB in KVM Guest Mode */
	44	#define TASK_SIZE 0x3fff8000UL
	45	#else
1da177e4 LT	46	/*
	47	* User space process size: 2GB. This is hardcoded into a few places,
	48	* so don't change it unless you know what you are doing.
	49	*/
d7de4134	50	#define TASK_SIZE 0x80000000UL
9843b030	51	#endif
1da177e4	52
949e51be	53	#define STACK_TOP_MAX TASK_SIZE
1091458d DD	54
	55	#define TASK_IS_32BIT_ADDR 1
	56
1da177e4 LT	57	#endif
1da177e4 LT	58
875d43e7	59	#ifdef CONFIG_64BIT
1da177e4 LT	60	/*
	61	* User space process size: 1TB. This is hardcoded into a few places,
	62	* so don't change it unless you know what you are doing. TASK_SIZE
	63	* is limited to 1TB by the R4000 architecture; R10000 and better can
	64	* support 16TB; the architectural reserve for future expansion is
	65	* 8192EB ...
	66	*/
	67	#define TASK_SIZE32 0x7fff8000UL
1e321fa9 LY	68	#ifdef CONFIG_MIPS_VA_BITS_48
	69	#define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
	70	#else
	71	#define TASK_SIZE64 0x10000000000UL
	72	#endif
949e51be	73	#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
949e51be	74	#define STACK_TOP_MAX TASK_SIZE64
1da177e4	75
82455257	76	#define TASK_SIZE_OF(tsk) \
949e51be	77	(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
1091458d DD	78
	79	#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
	80
1da177e4 LT	81	#endif
1da177e4 LT	82
432c6bac PB	83	/*
	84	* One page above the stack is used for branch delay slot "emulation".
	85	* See dsemul.c for details.
	86	*/
	87	#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - PAGE_SIZE)
949e51be DD	88
	89	/*
	90	* This decides where the kernel will search for a free chunk of vm
	91	* space during mmap's.
	92	*/
	93	#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
	94
922a70d3	95
1da177e4	96	#define NUM_FPU_REGS 32
1db1af84 PB	97
	98	#ifdef CONFIG_CPU_HAS_MSA
	99	# define FPU_REG_WIDTH 128
	100	#else
	101	# define FPU_REG_WIDTH 64
	102	#endif
1da177e4	103
bbd426f5 PB	104	union fpureg {
	105	__u32 val32[FPU_REG_WIDTH / 32];
	106	__u64 val64[FPU_REG_WIDTH / 64];
	107	};
	108
	109	#ifdef CONFIG_CPU_LITTLE_ENDIAN
	110	# define FPR_IDX(width, idx) (idx)
	111	#else
1f3a2c6e	112	# define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1))
bbd426f5 PB	113	#endif
	114
	115	#define BUILD_FPR_ACCESS(width) \
	116	static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \
	117	{ \
	118	return fpr->val##width[FPR_IDX(width, idx)]; \
	119	} \
	120	\
	121	static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \
	122	u##width val) \
	123	{ \
	124	fpr->val##width[FPR_IDX(width, idx)] = val; \
	125	}
	126
	127	BUILD_FPR_ACCESS(32)
	128	BUILD_FPR_ACCESS(64)
1da177e4	129
1da177e4	130	/*
e87ce948 PB	131	* It would be nice to add some more fields for emulator statistics,
	132	* the additional information is private to the FPU emulator for now.
	133	* See arch/mips/include/asm/fpu_emulator.h.
1da177e4 LT	134	*/
1da177e4 LT	135
eae89076	136	struct mips_fpu_struct {
bbd426f5	137	union fpureg fpr[NUM_FPU_REGS];
1da177e4	138	unsigned int fcr31;
1db1af84	139	unsigned int msacsr;
1da177e4 LT	140	};
1da177e4 LT	141
e50c0a8f RB	142	#define NUM_DSP_REGS 6
	143
	144	typedef __u32 dspreg_t;
	145
	146	struct mips_dsp_state {
70342287 RB	147	dspreg_t dspr[NUM_DSP_REGS];
70342287 RB	148	unsigned int dspcontrol;
e50c0a8f RB	149	};
e50c0a8f RB	150
41c594ab RB	151	#define INIT_CPUMASK { \
	152	{0,} \
	153	}
	154
6aa3524c DD	155	struct mips3264_watch_reg_state {
	156	/* The width of watchlo is 32 in a 32 bit kernel and 64 in a
	157	64 bit kernel. We use unsigned long as it has the same
	158	property. */
	159	unsigned long watchlo[NUM_WATCH_REGS];
	160	/* Only the mask and IRW bits from watchhi. */
	161	u16 watchhi[NUM_WATCH_REGS];
	162	};
	163
	164	union mips_watch_reg_state {
	165	struct mips3264_watch_reg_state mips3264;
	166	};
	167
2c952e06	168	#if defined(CONFIG_CPU_CAVIUM_OCTEON)
b5e00af8 DD	169
	170	struct octeon_cop2_state {
	171	/* DMFC2 rt, 0x0201 */
70342287	172	unsigned long cop2_crc_iv;
b5e00af8	173	/* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
70342287	174	unsigned long cop2_crc_length;
b5e00af8	175	/* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
70342287	176	unsigned long cop2_crc_poly;
b5e00af8	177	/* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
70342287	178	unsigned long cop2_llm_dat[2];
b5e00af8	179	/* DMFC2 rt, 0x0084 */
70342287	180	unsigned long cop2_3des_iv;
b5e00af8	181	/* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
70342287	182	unsigned long cop2_3des_key[3];
b5e00af8	183	/* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
70342287	184	unsigned long cop2_3des_result;
b5e00af8	185	/* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
70342287	186	unsigned long cop2_aes_inp0;
b5e00af8	187	/* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
70342287	188	unsigned long cop2_aes_iv[2];
b5e00af8 DD	189	/* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
b5e00af8 DD	190	* rt, 0x0107 */
70342287	191	unsigned long cop2_aes_key[4];
b5e00af8	192	/* DMFC2 rt, 0x0110 */
70342287	193	unsigned long cop2_aes_keylen;
b5e00af8	194	/* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
70342287	195	unsigned long cop2_aes_result[2];
b5e00af8 DD	196	/* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
	197	* rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
	198	* 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
	199	* 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
	200	* 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
70342287	201	unsigned long cop2_hsh_datw[15];
b5e00af8 DD	202	/* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
	203	* rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
	204	* 0x0256; DMFC2 rt, 0x0257 - Pass2 */
70342287	205	unsigned long cop2_hsh_ivw[8];
b5e00af8	206	/* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
70342287	207	unsigned long cop2_gfm_mult[2];
b5e00af8	208	/* DMFC2 rt, 0x025E - Pass2 */
70342287	209	unsigned long cop2_gfm_poly;
b5e00af8	210	/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
70342287	211	unsigned long cop2_gfm_result[2];
6b3a287e DD	212	/* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
6b3a287e DD	213	unsigned long cop2_sha3[2];
b5e00af8	214	};
2c952e06 J	215	#define COP2_INIT \
2c952e06 J	216	.cp2 = {0,},
b5e00af8 DD	217
	218	struct octeon_cvmseg_state {
	219	unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
	220	[cpu_dcache_line_size() / sizeof(unsigned long)];
	221	};
	222
5649d37c J	223	#elif defined(CONFIG_CPU_XLP)
	224	struct nlm_cop2_state {
	225	u64 rx[4];
	226	u64 tx[4];
	227	u32 tx_msg_status;
	228	u32 rx_msg_status;
	229	};
	230
	231	#define COP2_INIT \
	232	.cp2 = {{0}, {0}, 0, 0},
2c952e06 J	233	#else
2c952e06 J	234	#define COP2_INIT
b5e00af8 DD	235	#endif
b5e00af8 DD	236
1da177e4 LT	237	typedef struct {
	238	unsigned long seg;
	239	} mm_segment_t;
	240
37cddff8 PB	241	#ifdef CONFIG_CPU_HAS_MSA
	242	# define ARCH_MIN_TASKALIGN 16
	243	# define FPU_ALIGN __aligned(16)
	244	#else
	245	# define ARCH_MIN_TASKALIGN 8
	246	# define FPU_ALIGN
	247	#endif
1da177e4	248
e50c0a8f RB	249	struct mips_abi;
e50c0a8f RB	250
1da177e4 LT	251	/*
	252	* If you change thread_struct remember to change the #defines below too!
	253	*/
	254	struct thread_struct {
	255	/* Saved main processor registers. */
	256	unsigned long reg16;
	257	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
	258	unsigned long reg29, reg30, reg31;
	259
	260	/* Saved cp0 stuff. */
	261	unsigned long cp0_status;
	262
	263	/* Saved fpu/fpu emulator stuff. */
37cddff8	264	struct mips_fpu_struct fpu FPU_ALIGN;
432c6bac PB	265	/* Assigned branch delay slot 'emulation' frame */
	266	atomic_t bd_emu_frame;
	267	/* PC of the branch from a branch delay slot 'emulation' */
	268	unsigned long bd_emu_branch_pc;
	269	/* PC to continue from following a branch delay slot 'emulation' */
	270	unsigned long bd_emu_cont_pc;
f088fc84 RB	271	#ifdef CONFIG_MIPS_MT_FPAFF
	272	/* Emulated instruction count */
	273	unsigned long emulated_fp;
	274	/* Saved per-thread scheduler affinity mask */
	275	cpumask_t user_cpus_allowed;
	276	#endif /* CONFIG_MIPS_MT_FPAFF */
1da177e4	277
e50c0a8f RB	278	/* Saved state of the DSP ASE, if available. */
	279	struct mips_dsp_state dsp;
	280
6aa3524c DD	281	/* Saved watch register state, if available. */
	282	union mips_watch_reg_state watch;
	283
1da177e4 LT	284	/* Other stuff associated with the thread. */
	285	unsigned long cp0_badvaddr; /* Last user fault */
	286	unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
	287	unsigned long error_code;
e3b28831	288	unsigned long trap_nr;
b5e00af8	289	#ifdef CONFIG_CPU_CAVIUM_OCTEON
fc192e50 TW	290	struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
fc192e50 TW	291	struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
5649d37c J	292	#endif
	293	#ifdef CONFIG_CPU_XLP
	294	struct nlm_cop2_state cp2;
b5e00af8	295	#endif
e50c0a8f	296	struct mips_abi *abi;
1da177e4 LT	297	};
1da177e4 LT	298
f088fc84	299	#ifdef CONFIG_MIPS_MT_FPAFF
fee578fa RB	300	#define FPAFF_INIT \
	301	.emulated_fp = 0, \
	302	.user_cpus_allowed = INIT_CPUMASK,
f088fc84 RB	303	#else
	304	#define FPAFF_INIT
	305	#endif /* CONFIG_MIPS_MT_FPAFF */
	306
fee578fa	307	#define INIT_THREAD { \
70342287 RB	308	/* \
	309	* Saved main processor registers \
	310	*/ \
fee578fa RB	311	.reg16 = 0, \
	312	.reg17 = 0, \
	313	.reg18 = 0, \
	314	.reg19 = 0, \
	315	.reg20 = 0, \
	316	.reg21 = 0, \
	317	.reg22 = 0, \
	318	.reg23 = 0, \
	319	.reg29 = 0, \
	320	.reg30 = 0, \
	321	.reg31 = 0, \
	322	/* \
	323	* Saved cp0 stuff \
	324	*/ \
	325	.cp0_status = 0, \
	326	/* \
	327	* Saved FPU/FPU emulator stuff \
	328	*/ \
	329	.fpu = { \
bbd426f5	330	.fpr = {{{0,},},}, \
fee578fa	331	.fcr31 = 0, \
1db1af84	332	.msacsr = 0, \
fee578fa RB	333	}, \
	334	/* \
	335	* FPU affinity state (null if not FPAFF) \
	336	*/ \
	337	FPAFF_INIT \
432c6bac PB	338	/* Delay slot emulation */ \
	339	.bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \
	340	.bd_emu_branch_pc = 0, \
	341	.bd_emu_cont_pc = 0, \
fee578fa RB	342	/* \
	343	* Saved DSP stuff \
	344	*/ \
	345	.dsp = { \
	346	.dspr = {0, }, \
	347	.dspcontrol = 0, \
	348	}, \
6aa3524c DD	349	/* \
	350	* saved watch register stuff \
	351	*/ \
	352	.watch = {{{0,},},}, \
fee578fa RB	353	/* \
	354	* Other stuff associated with the process \
	355	*/ \
	356	.cp0_badvaddr = 0, \
	357	.cp0_baduaddr = 0, \
	358	.error_code = 0, \
e3b28831	359	.trap_nr = 0, \
b5e00af8	360	/* \
2c952e06	361	* Platform specific cop2 registers(null if no COP2) \
b5e00af8	362	*/ \
2c952e06	363	COP2_INIT \
1da177e4 LT	364	}
	365
	366	struct task_struct;
	367
	368	/* Free all resources held by a thread. */
	369	#define release_thread(thread) do { } while(0)
	370
1da177e4 LT	371	extern unsigned long thread_saved_pc(struct task_struct *tsk);
	372
	373	/*
	374	* Do necessary setup to start up a newly executed thread.
	375	*/
	376	extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
	377
04cc89d1 RB	378	static inline void flush_thread(void)
	379	{
	380	}
	381
1da177e4 LT	382	unsigned long get_wchan(struct task_struct *p);
1da177e4 LT	383
484889fc DD	384	#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
	385	THREAD_SIZE - 32 - sizeof(struct pt_regs))
	386	#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
40bc9c67 AV	387	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
	388	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
	389	#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
1da177e4 LT	390
1da177e4 LT	391	#define cpu_relax() barrier()
3a6bfbc9	392	#define cpu_relax_lowlatency() cpu_relax()
1da177e4 LT	393
	394	/*
	395	* Return_address is a replacement for __builtin_return_address(count)
	396	* which on certain architectures cannot reasonably be implemented in GCC
25985edc	397	* (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
1da177e4 LT	398	* Note that __builtin_return_address(x>=1) is forbidden because GCC
	399	* aborts compilation on some CPUs. It's simply not possible to unwind
	400	* some CPU's stackframes.
	401	*
70342287	402	* __builtin_return_address works only for non-leaf functions. We avoid the
1da177e4 LT	403	* overhead of a function call by forcing the compiler to save the return
	404	* address register on the stack.
	405	*/
	406	#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
	407
	408	#ifdef CONFIG_CPU_HAS_PREFETCH
	409
	410	#define ARCH_HAS_PREFETCH
0453fb3c	411	#define prefetch(x) __builtin_prefetch((x), 0, 1)
1da177e4	412
0453fb3c DD	413	#define ARCH_HAS_PREFETCHW
0453fb3c DD	414	#define prefetchw(x) __builtin_prefetch((x), 1, 1)
1da177e4 LT	415
	416	#endif
	417
9791554b PB	418	/*
	419	* Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
	420	* to the prctl syscall.
	421	*/
	422	extern int mips_get_process_fp_mode(struct task_struct *task);
	423	extern int mips_set_process_fp_mode(struct task_struct *task,
	424	unsigned int value);
	425
	426	#define GET_FP_MODE(task) mips_get_process_fp_mode(task)
	427	#define SET_FP_MODE(task,value) mips_set_process_fp_mode(task, value)
	428
1da177e4	429	#endif /* _ASM_PROCESSOR_H */