[deliverable/linux.git] / arch / mips / include / asm / tlb.h

#ifndef __ASM_TLB_H
#define __ASM_TLB_H

/*
 * MIPS doesn't need any special per-pte or per-vma handling, except
 * we need to flush cache for area to be unmapped.
 */
#define tlb_start_vma(tlb, vma)					\
	do {							\
		if (!tlb->fullmm)				\
			flush_cache_range(vma, vma->vm_start, vma->vm_end); \
	}  while (0)
#define tlb_end_vma(tlb, vma) do { } while (0)
#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)

/*
 * .. because we flush the whole mm when it fills up.
 */
#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)

#define UNIQUE_ENTRYHI(idx)						\
		((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) |		\
		 (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))

#include <asm-generic/tlb.h>

#endif /* __ASM_TLB_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_TLB_H
	2	#define __ASM_TLB_H
	3
	4	/*
	5	* MIPS doesn't need any special per-pte or per-vma handling, except
	6	* we need to flush cache for area to be unmapped.
	7	*/
70342287	8	#define tlb_start_vma(tlb, vma) \
1da177e4 LT	9	do { \
	10	if (!tlb->fullmm) \
	11	flush_cache_range(vma, vma->vm_start, vma->vm_end); \
	12	} while (0)
	13	#define tlb_end_vma(tlb, vma) do { } while (0)
	14	#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
	15
	16	/*
	17	* .. because we flush the whole mm when it fills up.
	18	*/
	19	#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
	20
6e7f8b8e LY	21	#define UNIQUE_ENTRYHI(idx) \
	22	((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) \| \
	23	(cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
c01905ee	24
1da177e4 LT	25	#include <asm-generic/tlb.h>
	26
	27	#endif /* __ASM_TLB_H */