[deliverable/linux.git] / arch / mips / jz4740 / gpio.c

/*
 *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
 *  JZ4740 platform GPIO support
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under  the terms of the GNU General	 Public License as published by the
 *  Free Software Foundation;  either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>

#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irqchip/ingenic.h>
#include <linux/bitops.h>

#include <linux/debugfs.h>
#include <linux/seq_file.h>

#include <asm/mach-jz4740/base.h>

#define JZ4740_GPIO_BASE_A (32*0)
#define JZ4740_GPIO_BASE_B (32*1)
#define JZ4740_GPIO_BASE_C (32*2)
#define JZ4740_GPIO_BASE_D (32*3)

#define JZ4740_GPIO_NUM_A 32
#define JZ4740_GPIO_NUM_B 32
#define JZ4740_GPIO_NUM_C 31
#define JZ4740_GPIO_NUM_D 32

#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)

#define JZ_REG_GPIO_PIN			0x00
#define JZ_REG_GPIO_DATA		0x10
#define JZ_REG_GPIO_DATA_SET		0x14
#define JZ_REG_GPIO_DATA_CLEAR		0x18
#define JZ_REG_GPIO_MASK		0x20
#define JZ_REG_GPIO_MASK_SET		0x24
#define JZ_REG_GPIO_MASK_CLEAR		0x28
#define JZ_REG_GPIO_PULL		0x30
#define JZ_REG_GPIO_PULL_SET		0x34
#define JZ_REG_GPIO_PULL_CLEAR		0x38
#define JZ_REG_GPIO_FUNC		0x40
#define JZ_REG_GPIO_FUNC_SET		0x44
#define JZ_REG_GPIO_FUNC_CLEAR		0x48
#define JZ_REG_GPIO_SELECT		0x50
#define JZ_REG_GPIO_SELECT_SET		0x54
#define JZ_REG_GPIO_SELECT_CLEAR	0x58
#define JZ_REG_GPIO_DIRECTION		0x60
#define JZ_REG_GPIO_DIRECTION_SET	0x64
#define JZ_REG_GPIO_DIRECTION_CLEAR	0x68
#define JZ_REG_GPIO_TRIGGER		0x70
#define JZ_REG_GPIO_TRIGGER_SET		0x74
#define JZ_REG_GPIO_TRIGGER_CLEAR	0x78
#define JZ_REG_GPIO_FLAG		0x80
#define JZ_REG_GPIO_FLAG_CLEAR		0x14

#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))

struct jz_gpio_chip {
	unsigned int irq;
	unsigned int irq_base;
	uint32_t edge_trigger_both;

	void __iomem *base;

	struct gpio_chip gpio_chip;
};

static struct jz_gpio_chip jz4740_gpio_chips[];

static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
{
	return &jz4740_gpio_chips[gpio >> 5];
}

static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip)
{
	return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
}

static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	return gc->private;
}

static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
{
	writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
}

int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
{
	if (function == JZ_GPIO_FUNC_NONE) {
		jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
		jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
		jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
	} else {
		jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
		jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
		switch (function) {
		case JZ_GPIO_FUNC1:
			jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
			break;
		case JZ_GPIO_FUNC3:
			jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
		case JZ_GPIO_FUNC2: /* Falltrough */
			jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
			break;
		default:
			BUG();
			break;
		}
	}

	return 0;
}
EXPORT_SYMBOL_GPL(jz_gpio_set_function);

int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
{
	size_t i;
	int ret;

	for (i = 0; i < num; ++i, ++request) {
		ret = gpio_request(request->gpio, request->name);
		if (ret)
			goto err;
		jz_gpio_set_function(request->gpio, request->function);
	}

	return 0;

err:
	for (--request; i > 0; --i, --request) {
		gpio_free(request->gpio);
		jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
	}

	return ret;
}
EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);

void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
{
	size_t i;

	for (i = 0; i < num; ++i, ++request) {
		gpio_free(request->gpio);
		jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
	}

}
EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);

void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
{
	size_t i;

	for (i = 0; i < num; ++i, ++request) {
		jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
		jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
		jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
	}
}
EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);

void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
{
	size_t i;

	for (i = 0; i < num; ++i, ++request)
		jz_gpio_set_function(request->gpio, request->function);
}
EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);

void jz_gpio_enable_pullup(unsigned gpio)
{
	jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
}
EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);

void jz_gpio_disable_pullup(unsigned gpio)
{
	jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
}
EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);

static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
{
	return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
}

static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
{
	uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
	reg += !value;
	writel(BIT(gpio), reg);
}

static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
	int value)
{
	writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
	jz_gpio_set_value(chip, gpio, value);

	return 0;
}

static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
	writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));

	return 0;
}

int jz_gpio_port_direction_input(int port, uint32_t mask)
{
	writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));

	return 0;
}
EXPORT_SYMBOL(jz_gpio_port_direction_input);

int jz_gpio_port_direction_output(int port, uint32_t mask)
{
	writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));

	return 0;
}
EXPORT_SYMBOL(jz_gpio_port_direction_output);

void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
{
	writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
	writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
}
EXPORT_SYMBOL(jz_gpio_port_set_value);

uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
{
	uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));

	return value & mask;
}
EXPORT_SYMBOL(jz_gpio_port_get_value);

int gpio_to_irq(unsigned gpio)
{
	return JZ4740_IRQ_GPIO(0) + gpio;
}
EXPORT_SYMBOL_GPL(gpio_to_irq);

int irq_to_gpio(unsigned irq)
{
	return irq - JZ4740_IRQ_GPIO(0);
}
EXPORT_SYMBOL_GPL(irq_to_gpio);

#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)

static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
{
	uint32_t value;
	void __iomem *reg;
	uint32_t mask = IRQ_TO_BIT(irq);

	if (!(chip->edge_trigger_both & mask))
		return;

	reg = chip->base;

	value = readl(chip->base + JZ_REG_GPIO_PIN);
	if (value & mask)
		reg += JZ_REG_GPIO_DIRECTION_CLEAR;
	else
		reg += JZ_REG_GPIO_DIRECTION_SET;

	writel(mask, reg);
}

static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
{
	uint32_t flag;
	unsigned int gpio_irq;
	struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);

	flag = readl(chip->base + JZ_REG_GPIO_FLAG);
	if (!flag)
		return;

	gpio_irq = chip->irq_base + __fls(flag);

	jz_gpio_check_trigger_both(chip, gpio_irq);

	generic_handle_irq(gpio_irq);
};

static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
{
	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
	writel(IRQ_TO_BIT(data->irq), chip->base + reg);
}

static void jz_gpio_irq_unmask(struct irq_data *data)
{
	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);

	jz_gpio_check_trigger_both(chip, data->irq);
	irq_gc_unmask_enable_reg(data);
};

/* TODO: Check if function is gpio */
static unsigned int jz_gpio_irq_startup(struct irq_data *data)
{
	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
	jz_gpio_irq_unmask(data);
	return 0;
}

static void jz_gpio_irq_shutdown(struct irq_data *data)
{
	irq_gc_mask_disable_reg(data);

	/* Set direction to input */
	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
}

static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
{
	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
	unsigned int irq = data->irq;

	if (flow_type == IRQ_TYPE_EDGE_BOTH) {
		uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
		if (value & IRQ_TO_BIT(irq))
			flow_type = IRQ_TYPE_EDGE_FALLING;
		else
			flow_type = IRQ_TYPE_EDGE_RISING;
		chip->edge_trigger_both |= IRQ_TO_BIT(irq);
	} else {
		chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
	}

	switch (flow_type) {
	case IRQ_TYPE_EDGE_RISING:
		jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
		jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
		jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
		jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
		jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
{
	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);

	irq_gc_set_wake(data, on);
	irq_set_irq_wake(chip->irq, on);

	return 0;
}

#define JZ4740_GPIO_CHIP(_bank) { \
	.irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
	.gpio_chip = { \
		.label = "Bank " # _bank, \
		.owner = THIS_MODULE, \
		.set = jz_gpio_set_value, \
		.get = jz_gpio_get_value, \
		.direction_output = jz_gpio_direction_output, \
		.direction_input = jz_gpio_direction_input, \
		.base = JZ4740_GPIO_BASE_ ## _bank, \
		.ngpio = JZ4740_GPIO_NUM_ ## _bank, \
	}, \
}

static struct jz_gpio_chip jz4740_gpio_chips[] = {
	JZ4740_GPIO_CHIP(A),
	JZ4740_GPIO_CHIP(B),
	JZ4740_GPIO_CHIP(C),
	JZ4740_GPIO_CHIP(D),
};

static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);

	chip->irq = JZ4740_IRQ_INTC_GPIO(id);
	irq_set_handler_data(chip->irq, chip);
	irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);

	gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base,
		chip->base, handle_level_irq);

	gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio);
	gc->private = chip;

	ct = gc->chip_types;
	ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR;
	ct->regs.disable = JZ_REG_GPIO_MASK_SET;
	ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR;

	ct->chip.name = "GPIO";
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = jz_gpio_irq_unmask;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_suspend = ingenic_intc_irq_suspend;
	ct->chip.irq_resume = ingenic_intc_irq_resume;
	ct->chip.irq_startup = jz_gpio_irq_startup;
	ct->chip.irq_shutdown = jz_gpio_irq_shutdown;
	ct->chip.irq_set_type = jz_gpio_irq_set_type;
	ct->chip.irq_set_wake = jz_gpio_irq_set_wake;
	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;

	irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio),
		IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE | IRQ_LEVEL);

	gpiochip_add(&chip->gpio_chip);
}

static int __init jz4740_gpio_init(void)
{
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
		jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);

	printk(KERN_INFO "JZ4740 GPIO initialized\n");

	return 0;
}
arch_initcall(jz4740_gpio_init);

#ifdef CONFIG_DEBUG_FS

static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
	const char *name, unsigned int reg)
{
	seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
}

static int gpio_regs_show(struct seq_file *s, void *unused)
{
	struct jz_gpio_chip *chip = jz4740_gpio_chips;
	int i;

	for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
		seq_printf(s, "==GPIO %d==\n", i);
		gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
		gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
		gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
		gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
		gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
		gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
		gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
		gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
		gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
	}

	return 0;
}

static int gpio_regs_open(struct inode *inode, struct file *file)
{
	return single_open(file, gpio_regs_show, NULL);
}

static const struct file_operations gpio_regs_operations = {
	.open		= gpio_regs_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init gpio_debugfs_init(void)
{
	(void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
				NULL, NULL, &gpio_regs_operations);
	return 0;
}
subsys_initcall(gpio_debugfs_init);

#endif
Commit	Line	Data
a55f4506 LPC	1	/*
	2	* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
	3	* JZ4740 platform GPIO support
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
70342287	6	* under the terms of the GNU General Public License as published by the
a55f4506 LPC	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* You should have received a copy of the GNU General Public License along
	11	* with this program; if not, write to the Free Software Foundation, Inc.,
	12	* 675 Mass Ave, Cambridge, MA 02139, USA.
	13	*
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19
a55f4506 LPC	20	#include <linux/io.h>
	21	#include <linux/gpio.h>
	22	#include <linux/delay.h>
	23	#include <linux/interrupt.h>
44e08e70	24	#include <linux/irqchip/ingenic.h>
a55f4506 LPC	25	#include <linux/bitops.h>
	26
	27	#include <linux/debugfs.h>
	28	#include <linux/seq_file.h>
	29
	30	#include <asm/mach-jz4740/base.h>
	31
	32	#define JZ4740_GPIO_BASE_A (32*0)
	33	#define JZ4740_GPIO_BASE_B (32*1)
	34	#define JZ4740_GPIO_BASE_C (32*2)
	35	#define JZ4740_GPIO_BASE_D (32*3)
	36
	37	#define JZ4740_GPIO_NUM_A 32
	38	#define JZ4740_GPIO_NUM_B 32
	39	#define JZ4740_GPIO_NUM_C 31
	40	#define JZ4740_GPIO_NUM_D 32
	41
	42	#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
	43	#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
	44	#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
	45	#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
	46
	47	#define JZ_REG_GPIO_PIN 0x00
	48	#define JZ_REG_GPIO_DATA 0x10
	49	#define JZ_REG_GPIO_DATA_SET 0x14
	50	#define JZ_REG_GPIO_DATA_CLEAR 0x18
	51	#define JZ_REG_GPIO_MASK 0x20
	52	#define JZ_REG_GPIO_MASK_SET 0x24
	53	#define JZ_REG_GPIO_MASK_CLEAR 0x28
	54	#define JZ_REG_GPIO_PULL 0x30
	55	#define JZ_REG_GPIO_PULL_SET 0x34
	56	#define JZ_REG_GPIO_PULL_CLEAR 0x38
	57	#define JZ_REG_GPIO_FUNC 0x40
	58	#define JZ_REG_GPIO_FUNC_SET 0x44
	59	#define JZ_REG_GPIO_FUNC_CLEAR 0x48
	60	#define JZ_REG_GPIO_SELECT 0x50
	61	#define JZ_REG_GPIO_SELECT_SET 0x54
	62	#define JZ_REG_GPIO_SELECT_CLEAR 0x58
	63	#define JZ_REG_GPIO_DIRECTION 0x60
	64	#define JZ_REG_GPIO_DIRECTION_SET 0x64
	65	#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
	66	#define JZ_REG_GPIO_TRIGGER 0x70
	67	#define JZ_REG_GPIO_TRIGGER_SET 0x74
	68	#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
	69	#define JZ_REG_GPIO_FLAG 0x80
	70	#define JZ_REG_GPIO_FLAG_CLEAR 0x14
	71
	72	#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
	73	#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
	74	#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
	75
	76	struct jz_gpio_chip {
	77	unsigned int irq;
	78	unsigned int irq_base;
a55f4506 LPC	79	uint32_t edge_trigger_both;
	80
	81	void __iomem *base;
	82
a55f4506	83	struct gpio_chip gpio_chip;
a55f4506 LPC	84	};
	85
	86	static struct jz_gpio_chip jz4740_gpio_chips[];
	87
	88	static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
	89	{
	90	return &jz4740_gpio_chips[gpio >> 5];
	91	}
	92
	93	static inline struct jz_gpio_chip gpio_chip_to_jz_gpio_chip(struct gpio_chip gpio_chip)
	94	{
	95	return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
	96	}
	97
42b64f38	98	static inline struct jz_gpio_chip irq_to_jz_gpio_chip(struct irq_data data)
a55f4506	99	{
83bc7692 LPC	100	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
83bc7692 LPC	101	return gc->private;
a55f4506 LPC	102	}
	103
	104	static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
	105	{
	106	writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
	107	}
	108
	109	int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
	110	{
	111	if (function == JZ_GPIO_FUNC_NONE) {
	112	jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
	113	jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
	114	jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
	115	} else {
	116	jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
	117	jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
	118	switch (function) {
	119	case JZ_GPIO_FUNC1:
	120	jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
	121	break;
	122	case JZ_GPIO_FUNC3:
	123	jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
	124	case JZ_GPIO_FUNC2: /* Falltrough */
	125	jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
	126	break;
	127	default:
	128	BUG();
	129	break;
	130	}
	131	}
	132
	133	return 0;
	134	}
	135	EXPORT_SYMBOL_GPL(jz_gpio_set_function);
	136
	137	int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
	138	{
	139	size_t i;
	140	int ret;
	141
	142	for (i = 0; i < num; ++i, ++request) {
	143	ret = gpio_request(request->gpio, request->name);
	144	if (ret)
	145	goto err;
	146	jz_gpio_set_function(request->gpio, request->function);
	147	}
	148
	149	return 0;
	150
	151	err:
	152	for (--request; i > 0; --i, --request) {
	153	gpio_free(request->gpio);
	154	jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
	155	}
	156
	157	return ret;
	158	}
	159	EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
	160
	161	void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
	162	{
	163	size_t i;
	164
	165	for (i = 0; i < num; ++i, ++request) {
166	gpio_free(request->gpio);
167	jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
168	}
169
170	}
171	EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
172
173	void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
174	{
175	size_t i;
176
177	for (i = 0; i < num; ++i, ++request) {
178	jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
179	jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
180	jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
181	}
182	}
183	EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
184
185	void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
186	{
187	size_t i;
188
189	for (i = 0; i < num; ++i, ++request)
190	jz_gpio_set_function(request->gpio, request->function);
191	}
192	EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
193
194	void jz_gpio_enable_pullup(unsigned gpio)
195	{
196	jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
197	}
198	EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
199
200	void jz_gpio_disable_pullup(unsigned gpio)
201	{
202	jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
203	}
204	EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
205
206	static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
207	{
208	return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
209	}
210
211	static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
212	{
213	uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
214	reg += !value;
215	writel(BIT(gpio), reg);
216	}
217
218	static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
219	int value)
220	{
221	writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
222	jz_gpio_set_value(chip, gpio, value);
223
224	return 0;
225	}
226
227	static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
228	{
229	writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
230
231	return 0;
232	}
233
234	int jz_gpio_port_direction_input(int port, uint32_t mask)
235	{
236	writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
237
238	return 0;
239	}
240	EXPORT_SYMBOL(jz_gpio_port_direction_input);
241
242	int jz_gpio_port_direction_output(int port, uint32_t mask)
243	{
244	writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
245
246	return 0;
247	}
248	EXPORT_SYMBOL(jz_gpio_port_direction_output);
249
250	void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
251	{
252	writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
253	writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
254	}
255	EXPORT_SYMBOL(jz_gpio_port_set_value);
256
257	uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
258	{
259	uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
260
261	return value & mask;
262	}
263	EXPORT_SYMBOL(jz_gpio_port_get_value);
264
265	int gpio_to_irq(unsigned gpio)
266	{
267	return JZ4740_IRQ_GPIO(0) + gpio;
268	}
269	EXPORT_SYMBOL_GPL(gpio_to_irq);
270
271	int irq_to_gpio(unsigned irq)
272	{
273	return irq - JZ4740_IRQ_GPIO(0);
274	}
275	EXPORT_SYMBOL_GPL(irq_to_gpio);
276
277	#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
278
279	static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
280	{
281	uint32_t value;
282	void __iomem *reg;
283	uint32_t mask = IRQ_TO_BIT(irq);
284
285	if (!(chip->edge_trigger_both & mask))
286	return;
287
288	reg = chip->base;
289
290	value = readl(chip->base + JZ_REG_GPIO_PIN);
291	if (value & mask)
292	reg += JZ_REG_GPIO_DIRECTION_CLEAR;
293	else
294	reg += JZ_REG_GPIO_DIRECTION_SET;
295
296	writel(mask, reg);
297	}
298
299	static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
300	{
301	uint32_t flag;
302	unsigned int gpio_irq;
e4ec7989	303	struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
a55f4506	304
a55f4506	305	flag = readl(chip->base + JZ_REG_GPIO_FLAG);
a55f4506 LPC	306	if (!flag)
	307	return;
	308
fe5a8b7f	309	gpio_irq = chip->irq_base + __fls(flag);
a55f4506	310
93303638	311	jz_gpio_check_trigger_both(chip, gpio_irq);
a55f4506	312
a55f4506 LPC	313	generic_handle_irq(gpio_irq);
	314	};
	315
42b64f38	316	static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
a55f4506	317	{
42b64f38 TG	318	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
42b64f38 TG	319	writel(IRQ_TO_BIT(data->irq), chip->base + reg);
a55f4506 LPC	320	}
a55f4506 LPC	321
42b64f38	322	static void jz_gpio_irq_unmask(struct irq_data *data)
a55f4506	323	{
42b64f38	324	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
a55f4506	325
42b64f38	326	jz_gpio_check_trigger_both(chip, data->irq);
83bc7692	327	irq_gc_unmask_enable_reg(data);
a55f4506 LPC	328	};
	329
	330	/* TODO: Check if function is gpio */
42b64f38	331	static unsigned int jz_gpio_irq_startup(struct irq_data *data)
a55f4506	332	{
42b64f38	333	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
42b64f38	334	jz_gpio_irq_unmask(data);
a55f4506 LPC	335	return 0;
	336	}
	337
42b64f38	338	static void jz_gpio_irq_shutdown(struct irq_data *data)
a55f4506	339	{
83bc7692	340	irq_gc_mask_disable_reg(data);
a55f4506 LPC	341
a55f4506 LPC	342	/* Set direction to input */
42b64f38 TG	343	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
42b64f38 TG	344	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
a55f4506 LPC	345	}
a55f4506 LPC	346
42b64f38	347	static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
a55f4506	348	{
42b64f38	349	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
42b64f38	350	unsigned int irq = data->irq;
a55f4506	351
a55f4506 LPC	352	if (flow_type == IRQ_TYPE_EDGE_BOTH) {
	353	uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
	354	if (value & IRQ_TO_BIT(irq))
	355	flow_type = IRQ_TYPE_EDGE_FALLING;
	356	else
	357	flow_type = IRQ_TYPE_EDGE_RISING;
	358	chip->edge_trigger_both \|= IRQ_TO_BIT(irq);
	359	} else {
	360	chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
	361	}
	362
	363	switch (flow_type) {
	364	case IRQ_TYPE_EDGE_RISING:
42b64f38 TG	365	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
42b64f38 TG	366	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
a55f4506 LPC	367	break;
a55f4506 LPC	368	case IRQ_TYPE_EDGE_FALLING:
42b64f38 TG	369	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
42b64f38 TG	370	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
a55f4506 LPC	371	break;
a55f4506 LPC	372	case IRQ_TYPE_LEVEL_HIGH:
42b64f38 TG	373	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
42b64f38 TG	374	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
a55f4506 LPC	375	break;
a55f4506 LPC	376	case IRQ_TYPE_LEVEL_LOW:
42b64f38 TG	377	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
42b64f38 TG	378	jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
a55f4506 LPC	379	break;
	380	default:
	381	return -EINVAL;
	382	}
	383
a55f4506 LPC	384	return 0;
	385	}
	386
42b64f38	387	static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
a55f4506	388	{
42b64f38	389	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
a55f4506	390
83bc7692	391	irq_gc_set_wake(data, on);
e4ec7989	392	irq_set_irq_wake(chip->irq, on);
83bc7692	393
a55f4506 LPC	394	return 0;
	395	}
	396
a55f4506 LPC	397	#define JZ4740_GPIO_CHIP(_bank) { \
	398	.irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
	399	.gpio_chip = { \
	400	.label = "Bank " # _bank, \
	401	.owner = THIS_MODULE, \
	402	.set = jz_gpio_set_value, \
	403	.get = jz_gpio_get_value, \
	404	.direction_output = jz_gpio_direction_output, \
	405	.direction_input = jz_gpio_direction_input, \
	406	.base = JZ4740_GPIO_BASE_ ## _bank, \
	407	.ngpio = JZ4740_GPIO_NUM_ ## _bank, \
	408	}, \
a55f4506 LPC	409	}
	410
	411	static struct jz_gpio_chip jz4740_gpio_chips[] = {
	412	JZ4740_GPIO_CHIP(A),
	413	JZ4740_GPIO_CHIP(B),
	414	JZ4740_GPIO_CHIP(C),
	415	JZ4740_GPIO_CHIP(D),
	416	};
	417
83bc7692	418	static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
a55f4506	419	{
83bc7692 LPC	420	struct irq_chip_generic *gc;
83bc7692 LPC	421	struct irq_chip_type *ct;
a55f4506	422
83bc7692	423	chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
a55f4506	424
83bc7692 LPC	425	chip->irq = JZ4740_IRQ_INTC_GPIO(id);
	426	irq_set_handler_data(chip->irq, chip);
	427	irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
bd710009	428
83bc7692 LPC	429	gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base,
83bc7692 LPC	430	chip->base, handle_level_irq);
a55f4506	431
83bc7692 LPC	432	gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio);
83bc7692 LPC	433	gc->private = chip;
a55f4506	434
83bc7692 LPC	435	ct = gc->chip_types;
	436	ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR;
	437	ct->regs.disable = JZ_REG_GPIO_MASK_SET;
	438	ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR;
a55f4506	439
83bc7692 LPC	440	ct->chip.name = "GPIO";
	441	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	442	ct->chip.irq_unmask = jz_gpio_irq_unmask;
	443	ct->chip.irq_ack = irq_gc_ack_set_bit;
2da01884 PB	444	ct->chip.irq_suspend = ingenic_intc_irq_suspend;
2da01884 PB	445	ct->chip.irq_resume = ingenic_intc_irq_resume;
83bc7692 LPC	446	ct->chip.irq_startup = jz_gpio_irq_startup;
	447	ct->chip.irq_shutdown = jz_gpio_irq_shutdown;
	448	ct->chip.irq_set_type = jz_gpio_irq_set_type;
	449	ct->chip.irq_set_wake = jz_gpio_irq_set_wake;
	450	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
a55f4506	451
83bc7692 LPC	452	irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio),
83bc7692 LPC	453	IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE \| IRQ_LEVEL);
a55f4506 LPC	454
a55f4506 LPC	455	gpiochip_add(&chip->gpio_chip);
a55f4506 LPC	456	}
	457
	458	static int __init jz4740_gpio_init(void)
	459	{
	460	unsigned int i;
a55f4506 LPC	461
	462	for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
	463	jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
	464
b595076a	465	printk(KERN_INFO "JZ4740 GPIO initialized\n");
a55f4506 LPC	466
	467	return 0;
	468	}
	469	arch_initcall(jz4740_gpio_init);
	470
	471	#ifdef CONFIG_DEBUG_FS
	472
	473	static inline void gpio_seq_reg(struct seq_file s, struct jz_gpio_chip chip,
	474	const char *name, unsigned int reg)
	475	{
	476	seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
	477	}
	478
	479	static int gpio_regs_show(struct seq_file s, void unused)
	480	{
	481	struct jz_gpio_chip *chip = jz4740_gpio_chips;
	482	int i;
	483
	484	for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
	485	seq_printf(s, "==GPIO %d==\n", i);
	486	gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
	487	gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
	488	gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
	489	gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
	490	gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
	491	gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
	492	gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
	493	gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
	494	gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
	495	}
	496
	497	return 0;
	498	}
	499
	500	static int gpio_regs_open(struct inode inode, struct file file)
	501	{
	502	return single_open(file, gpio_regs_show, NULL);
	503	}
	504
	505	static const struct file_operations gpio_regs_operations = {
	506	.open = gpio_regs_open,
	507	.read = seq_read,
	508	.llseek = seq_lseek,
	509	.release = single_release,
	510	};
	511
	512	static int __init gpio_debugfs_init(void)
	513	{
	514	(void) debugfs_create_file("jz_regs_gpio", S_IFREG \| S_IRUGO,
	515	NULL, NULL, &gpio_regs_operations);
	516	return 0;
	517	}
	518	subsys_initcall(gpio_debugfs_init);
	519
	520	#endif