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9869848d LPC |
1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> | |
3 | * JZ4740 platform IRQ support | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
70342287 | 6 | * under the terms of the GNU General Public License as published by the |
9869848d LPC |
7 | * Free Software Foundation; either version 2 of the License, or (at your |
8 | * option) any later version. | |
9 | * | |
10 | * You should have received a copy of the GNU General Public License along | |
11 | * with this program; if not, write to the Free Software Foundation, Inc., | |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/errno.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/ioport.h> | |
adbdce77 | 21 | #include <linux/of_irq.h> |
9869848d LPC |
22 | #include <linux/timex.h> |
23 | #include <linux/slab.h> | |
24 | #include <linux/delay.h> | |
25 | ||
9869848d | 26 | #include <asm/io.h> |
9869848d LPC |
27 | |
28 | #include <asm/mach-jz4740/base.h> | |
942e22df BN |
29 | #include <asm/mach-jz4740/irq.h> |
30 | ||
31 | #include "irq.h" | |
9869848d | 32 | |
adbdce77 PB |
33 | #include "../../drivers/irqchip/irqchip.h" |
34 | ||
fe778ece PB |
35 | struct ingenic_intc_data { |
36 | void __iomem *base; | |
37 | }; | |
9869848d LPC |
38 | |
39 | #define JZ_REG_INTC_STATUS 0x00 | |
40 | #define JZ_REG_INTC_MASK 0x04 | |
41 | #define JZ_REG_INTC_SET_MASK 0x08 | |
42 | #define JZ_REG_INTC_CLEAR_MASK 0x0c | |
43 | #define JZ_REG_INTC_PENDING 0x10 | |
44 | ||
83bc7692 | 45 | static irqreturn_t jz4740_cascade(int irq, void *data) |
9869848d | 46 | { |
fe778ece | 47 | struct ingenic_intc_data *intc = irq_get_handler_data(irq); |
83bc7692 | 48 | uint32_t irq_reg; |
9869848d | 49 | |
fe778ece | 50 | irq_reg = readl(intc->base + JZ_REG_INTC_PENDING); |
9869848d | 51 | |
83bc7692 LPC |
52 | if (irq_reg) |
53 | generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE); | |
54 | ||
55 | return IRQ_HANDLED; | |
42b64f38 TG |
56 | } |
57 | ||
83bc7692 | 58 | static void jz4740_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask) |
9869848d | 59 | { |
83bc7692 | 60 | struct irq_chip_regs *regs = &gc->chip_types->regs; |
9869848d | 61 | |
83bc7692 LPC |
62 | writel(mask, gc->reg_base + regs->enable); |
63 | writel(~mask, gc->reg_base + regs->disable); | |
9869848d LPC |
64 | } |
65 | ||
83bc7692 | 66 | void jz4740_irq_suspend(struct irq_data *data) |
9869848d | 67 | { |
83bc7692 LPC |
68 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); |
69 | jz4740_irq_set_mask(gc, gc->wake_active); | |
70 | } | |
9869848d | 71 | |
83bc7692 LPC |
72 | void jz4740_irq_resume(struct irq_data *data) |
73 | { | |
74 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); | |
75 | jz4740_irq_set_mask(gc, gc->mask_cache); | |
9869848d LPC |
76 | } |
77 | ||
78 | static struct irqaction jz4740_cascade_action = { | |
79 | .handler = jz4740_cascade, | |
80 | .name = "JZ4740 cascade interrupt", | |
81 | }; | |
82 | ||
adbdce77 PB |
83 | static int __init jz4740_intc_of_init(struct device_node *node, |
84 | struct device_node *parent) | |
9869848d | 85 | { |
fe778ece | 86 | struct ingenic_intc_data *intc; |
83bc7692 LPC |
87 | struct irq_chip_generic *gc; |
88 | struct irq_chip_type *ct; | |
638c8851 | 89 | struct irq_domain *domain; |
fe778ece PB |
90 | int parent_irq, err = 0; |
91 | ||
92 | intc = kzalloc(sizeof(*intc), GFP_KERNEL); | |
93 | if (!intc) { | |
94 | err = -ENOMEM; | |
95 | goto out_err; | |
96 | } | |
69ce4b22 PB |
97 | |
98 | parent_irq = irq_of_parse_and_map(node, 0); | |
fe778ece PB |
99 | if (!parent_irq) { |
100 | err = -EINVAL; | |
101 | goto out_free; | |
102 | } | |
83bc7692 | 103 | |
fe778ece PB |
104 | err = irq_set_handler_data(parent_irq, intc); |
105 | if (err) | |
106 | goto out_unmap_irq; | |
107 | ||
108 | intc->base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14); | |
9869848d | 109 | |
42b64f38 | 110 | /* Mask all irqs */ |
fe778ece | 111 | writel(0xffffffff, intc->base + JZ_REG_INTC_SET_MASK); |
42b64f38 | 112 | |
fe778ece | 113 | gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, intc->base, |
83bc7692 LPC |
114 | handle_level_irq); |
115 | ||
116 | gc->wake_enabled = IRQ_MSK(32); | |
117 | ||
118 | ct = gc->chip_types; | |
119 | ct->regs.enable = JZ_REG_INTC_CLEAR_MASK; | |
120 | ct->regs.disable = JZ_REG_INTC_SET_MASK; | |
121 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
122 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | |
123 | ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; | |
124 | ct->chip.irq_set_wake = irq_gc_set_wake; | |
125 | ct->chip.irq_suspend = jz4740_irq_suspend; | |
126 | ct->chip.irq_resume = jz4740_irq_resume; | |
127 | ||
128 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL); | |
9869848d | 129 | |
638c8851 PB |
130 | domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0, |
131 | &irq_domain_simple_ops, NULL); | |
132 | if (!domain) | |
133 | pr_warn("unable to register IRQ domain\n"); | |
134 | ||
69ce4b22 | 135 | setup_irq(parent_irq, &jz4740_cascade_action); |
adbdce77 | 136 | return 0; |
fe778ece PB |
137 | |
138 | out_unmap_irq: | |
139 | irq_dispose_mapping(parent_irq); | |
140 | out_free: | |
141 | kfree(intc); | |
142 | out_err: | |
143 | return err; | |
9869848d | 144 | } |
adbdce77 | 145 | IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", jz4740_intc_of_init); |