Commit | Line | Data |
---|---|---|
713233fb LPC |
1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> | |
6edde024 | 3 | * Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org> |
713233fb LPC |
4 | * JZ4740 setup code |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
70342287 | 7 | * under the terms of the GNU General Public License as published by the |
713233fb LPC |
8 | * Free Software Foundation; either version 2 of the License, or (at your |
9 | * option) any later version. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License along | |
12 | * with this program; if not, write to the Free Software Foundation, Inc., | |
13 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
6edde024 | 18 | #include <linux/io.h> |
0e81db8f | 19 | #include <linux/irqchip.h> |
713233fb | 20 | #include <linux/kernel.h> |
6ec127fb | 21 | #include <linux/libfdt.h> |
ffb1843d | 22 | #include <linux/of_fdt.h> |
713233fb | 23 | |
6edde024 | 24 | #include <asm/bootinfo.h> |
ffb1843d | 25 | #include <asm/prom.h> |
6edde024 MH |
26 | |
27 | #include <asm/mach-jz4740/base.h> | |
28 | ||
713233fb LPC |
29 | #include "reset.h" |
30 | ||
6edde024 MH |
31 | |
32 | #define JZ4740_EMC_SDRAM_CTRL 0x80 | |
33 | ||
34 | ||
35 | static void __init jz4740_detect_mem(void) | |
36 | { | |
37 | void __iomem *jz_emc_base; | |
38 | u32 ctrl, bus, bank, rows, cols; | |
15d45cce | 39 | phys_addr_t size; |
6edde024 MH |
40 | |
41 | jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100); | |
42 | ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL); | |
43 | bus = 2 - ((ctrl >> 31) & 1); | |
44 | bank = 1 + ((ctrl >> 19) & 1); | |
45 | cols = 8 + ((ctrl >> 26) & 7); | |
46 | rows = 11 + ((ctrl >> 20) & 3); | |
47 | printk(KERN_DEBUG | |
48 | "SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n", | |
49 | bus, bank, rows, cols); | |
50 | iounmap(jz_emc_base); | |
51 | ||
52 | size = 1 << (bus + bank + cols + rows); | |
53 | add_memory_region(0, size, BOOT_MEM_RAM); | |
54 | } | |
55 | ||
713233fb LPC |
56 | void __init plat_mem_setup(void) |
57 | { | |
6ec127fb PB |
58 | int offset; |
59 | ||
713233fb | 60 | jz4740_reset_init(); |
ffb1843d | 61 | __dt_setup_arch(__dtb_start); |
6ec127fb PB |
62 | |
63 | offset = fdt_path_offset(__dtb_start, "/memory"); | |
64 | if (offset < 0) | |
65 | jz4740_detect_mem(); | |
713233fb LPC |
66 | } |
67 | ||
ffb1843d PB |
68 | void __init device_tree_init(void) |
69 | { | |
70 | if (!initial_boot_params) | |
71 | return; | |
72 | ||
73 | unflatten_and_copy_device_tree(); | |
74 | } | |
75 | ||
713233fb LPC |
76 | const char *get_system_type(void) |
77 | { | |
97f2645f | 78 | if (IS_ENABLED(CONFIG_MACH_JZ4780)) |
5b9cdd24 PB |
79 | return "JZ4780"; |
80 | ||
713233fb LPC |
81 | return "JZ4740"; |
82 | } | |
0e81db8f PB |
83 | |
84 | void __init arch_init_irq(void) | |
85 | { | |
86 | irqchip_init(); | |
0e81db8f | 87 | } |