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all arches, signal: move restart_block to struct task_struct
[deliverable/linux.git] / arch / mips / kernel / asm-offsets.c
CommitLineData
1da177e4
LT		 1/*
2 * offset.c: Calculate pt_regs and task_struct offsets.
3 *
4 * Copyright (C) 1996 David S. Miller
5 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
6 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
7 *
8 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc.
10 */
1da177e4
LT		 11#include <linux/compat.h>
12#include <linux/types.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
fd04d206 15#include <linux/kbuild.h>
363c55ca 16#include <linux/suspend.h>
74e91335 17#include <asm/pm.h>
1da177e4
LT		 18#include <asm/ptrace.h>
19#include <asm/processor.h>
0ee958e1 20#include <asm/smp-cps.h>
1da177e4 21
12e25f8e
SL		 22#include <linux/kvm_host.h>
23
1da177e4
LT		 24void output_ptreg_defines(void)
25{
fd04d206
CL		 26 COMMENT("MIPS pt_regs offsets.");
27 OFFSET(PT_R0, pt_regs, regs[0]);
28 OFFSET(PT_R1, pt_regs, regs[1]);
29 OFFSET(PT_R2, pt_regs, regs[2]);
30 OFFSET(PT_R3, pt_regs, regs[3]);
31 OFFSET(PT_R4, pt_regs, regs[4]);
32 OFFSET(PT_R5, pt_regs, regs[5]);
33 OFFSET(PT_R6, pt_regs, regs[6]);
34 OFFSET(PT_R7, pt_regs, regs[7]);
35 OFFSET(PT_R8, pt_regs, regs[8]);
36 OFFSET(PT_R9, pt_regs, regs[9]);
37 OFFSET(PT_R10, pt_regs, regs[10]);
38 OFFSET(PT_R11, pt_regs, regs[11]);
39 OFFSET(PT_R12, pt_regs, regs[12]);
40 OFFSET(PT_R13, pt_regs, regs[13]);
41 OFFSET(PT_R14, pt_regs, regs[14]);
42 OFFSET(PT_R15, pt_regs, regs[15]);
43 OFFSET(PT_R16, pt_regs, regs[16]);
44 OFFSET(PT_R17, pt_regs, regs[17]);
45 OFFSET(PT_R18, pt_regs, regs[18]);
46 OFFSET(PT_R19, pt_regs, regs[19]);
47 OFFSET(PT_R20, pt_regs, regs[20]);
48 OFFSET(PT_R21, pt_regs, regs[21]);
49 OFFSET(PT_R22, pt_regs, regs[22]);
50 OFFSET(PT_R23, pt_regs, regs[23]);
51 OFFSET(PT_R24, pt_regs, regs[24]);
52 OFFSET(PT_R25, pt_regs, regs[25]);
53 OFFSET(PT_R26, pt_regs, regs[26]);
54 OFFSET(PT_R27, pt_regs, regs[27]);
55 OFFSET(PT_R28, pt_regs, regs[28]);
56 OFFSET(PT_R29, pt_regs, regs[29]);
57 OFFSET(PT_R30, pt_regs, regs[30]);
58 OFFSET(PT_R31, pt_regs, regs[31]);
59 OFFSET(PT_LO, pt_regs, lo);
60 OFFSET(PT_HI, pt_regs, hi);
9693a853 61#ifdef CONFIG_CPU_HAS_SMARTMIPS
fd04d206 62 OFFSET(PT_ACX, pt_regs, acx);
9693a853 63#endif
fd04d206
CL		 64 OFFSET(PT_EPC, pt_regs, cp0_epc);
65 OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
66 OFFSET(PT_STATUS, pt_regs, cp0_status);
67 OFFSET(PT_CAUSE, pt_regs, cp0_cause);
babed555
DD		 68#ifdef CONFIG_CPU_CAVIUM_OCTEON
69 OFFSET(PT_MPL, pt_regs, mpl);
70 OFFSET(PT_MTP, pt_regs, mtp);
71#endif /* CONFIG_CPU_CAVIUM_OCTEON */
fd04d206
CL		 72 DEFINE(PT_SIZE, sizeof(struct pt_regs));
73 BLANK();
1da177e4
LT		 74}
75
76void output_task_defines(void)
77{
fd04d206
CL		 78 COMMENT("MIPS task_struct offsets.");
79 OFFSET(TASK_STATE, task_struct, state);
80 OFFSET(TASK_THREAD_INFO, task_struct, stack);
81 OFFSET(TASK_FLAGS, task_struct, flags);
82 OFFSET(TASK_MM, task_struct, mm);
83 OFFSET(TASK_PID, task_struct, pid);
1400eb65
GF		 84#if defined(CONFIG_CC_STACKPROTECTOR)
85 OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
86#endif
fd04d206
CL		 87 DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
88 BLANK();
1da177e4
LT		 89}
90
91void output_thread_info_defines(void)
92{
fd04d206
CL		 93 COMMENT("MIPS thread_info offsets.");
94 OFFSET(TI_TASK, thread_info, task);
95 OFFSET(TI_EXEC_DOMAIN, thread_info, exec_domain);
96 OFFSET(TI_FLAGS, thread_info, flags);
97 OFFSET(TI_TP_VALUE, thread_info, tp_value);
98 OFFSET(TI_CPU, thread_info, cpu);
99 OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
100 OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
fd04d206
CL		 101 OFFSET(TI_REGS, thread_info, regs);
102 DEFINE(_THREAD_SIZE, THREAD_SIZE);
103 DEFINE(_THREAD_MASK, THREAD_MASK);
104 BLANK();
1da177e4
LT		 105}
106
107void output_thread_defines(void)
108{
fd04d206
CL		 109 COMMENT("MIPS specific thread_struct offsets.");
110 OFFSET(THREAD_REG16, task_struct, thread.reg16);
111 OFFSET(THREAD_REG17, task_struct, thread.reg17);
112 OFFSET(THREAD_REG18, task_struct, thread.reg18);
113 OFFSET(THREAD_REG19, task_struct, thread.reg19);
114 OFFSET(THREAD_REG20, task_struct, thread.reg20);
115 OFFSET(THREAD_REG21, task_struct, thread.reg21);
116 OFFSET(THREAD_REG22, task_struct, thread.reg22);
117 OFFSET(THREAD_REG23, task_struct, thread.reg23);
118 OFFSET(THREAD_REG29, task_struct, thread.reg29);
119 OFFSET(THREAD_REG30, task_struct, thread.reg30);
120 OFFSET(THREAD_REG31, task_struct, thread.reg31);
121 OFFSET(THREAD_STATUS, task_struct,
1da177e4 122 thread.cp0_status);
fd04d206 123 OFFSET(THREAD_FPU, task_struct, thread.fpu);
1da177e4 124
fd04d206 125 OFFSET(THREAD_BVADDR, task_struct, \
1da177e4 126 thread.cp0_badvaddr);
fd04d206 127 OFFSET(THREAD_BUADDR, task_struct, \
1da177e4 128 thread.cp0_baduaddr);
fd04d206 129 OFFSET(THREAD_ECODE, task_struct, \
1da177e4 130 thread.error_code);
fd04d206 131 BLANK();
1da177e4
LT		 132}
133
134void output_thread_fpu_defines(void)
135{
fd04d206
CL		 136 OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
137 OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
138 OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
139 OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
140 OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
141 OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
142 OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
143 OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
144 OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
145 OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
146 OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
147 OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
148 OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
149 OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
150 OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
151 OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
152 OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
153 OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
154 OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
155 OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
156 OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
157 OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
158 OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
159 OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
160 OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
161 OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
162 OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
163 OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
164 OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
165 OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
166 OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
167 OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
1da177e4 168
02987633
PB		 169 /* the least significant 64 bits of each FP register */
170 OFFSET(THREAD_FPR0_LS64, task_struct,
171 thread.fpu.fpr[0].val64[FPR_IDX(64, 0)]);
172 OFFSET(THREAD_FPR1_LS64, task_struct,
173 thread.fpu.fpr[1].val64[FPR_IDX(64, 0)]);
174 OFFSET(THREAD_FPR2_LS64, task_struct,
175 thread.fpu.fpr[2].val64[FPR_IDX(64, 0)]);
176 OFFSET(THREAD_FPR3_LS64, task_struct,
177 thread.fpu.fpr[3].val64[FPR_IDX(64, 0)]);
178 OFFSET(THREAD_FPR4_LS64, task_struct,
179 thread.fpu.fpr[4].val64[FPR_IDX(64, 0)]);
180 OFFSET(THREAD_FPR5_LS64, task_struct,
181 thread.fpu.fpr[5].val64[FPR_IDX(64, 0)]);
182 OFFSET(THREAD_FPR6_LS64, task_struct,
183 thread.fpu.fpr[6].val64[FPR_IDX(64, 0)]);
184 OFFSET(THREAD_FPR7_LS64, task_struct,
185 thread.fpu.fpr[7].val64[FPR_IDX(64, 0)]);
186 OFFSET(THREAD_FPR8_LS64, task_struct,
187 thread.fpu.fpr[8].val64[FPR_IDX(64, 0)]);
188 OFFSET(THREAD_FPR9_LS64, task_struct,
189 thread.fpu.fpr[9].val64[FPR_IDX(64, 0)]);
190 OFFSET(THREAD_FPR10_LS64, task_struct,
191 thread.fpu.fpr[10].val64[FPR_IDX(64, 0)]);
192 OFFSET(THREAD_FPR11_LS64, task_struct,
193 thread.fpu.fpr[11].val64[FPR_IDX(64, 0)]);
194 OFFSET(THREAD_FPR12_LS64, task_struct,
195 thread.fpu.fpr[12].val64[FPR_IDX(64, 0)]);
196 OFFSET(THREAD_FPR13_LS64, task_struct,
197 thread.fpu.fpr[13].val64[FPR_IDX(64, 0)]);
198 OFFSET(THREAD_FPR14_LS64, task_struct,
199 thread.fpu.fpr[14].val64[FPR_IDX(64, 0)]);
200 OFFSET(THREAD_FPR15_LS64, task_struct,
201 thread.fpu.fpr[15].val64[FPR_IDX(64, 0)]);
202 OFFSET(THREAD_FPR16_LS64, task_struct,
203 thread.fpu.fpr[16].val64[FPR_IDX(64, 0)]);
204 OFFSET(THREAD_FPR17_LS64, task_struct,
205 thread.fpu.fpr[17].val64[FPR_IDX(64, 0)]);
206 OFFSET(THREAD_FPR18_LS64, task_struct,
207 thread.fpu.fpr[18].val64[FPR_IDX(64, 0)]);
208 OFFSET(THREAD_FPR19_LS64, task_struct,
209 thread.fpu.fpr[19].val64[FPR_IDX(64, 0)]);
210 OFFSET(THREAD_FPR20_LS64, task_struct,
211 thread.fpu.fpr[20].val64[FPR_IDX(64, 0)]);
212 OFFSET(THREAD_FPR21_LS64, task_struct,
213 thread.fpu.fpr[21].val64[FPR_IDX(64, 0)]);
214 OFFSET(THREAD_FPR22_LS64, task_struct,
215 thread.fpu.fpr[22].val64[FPR_IDX(64, 0)]);
216 OFFSET(THREAD_FPR23_LS64, task_struct,
217 thread.fpu.fpr[23].val64[FPR_IDX(64, 0)]);
218 OFFSET(THREAD_FPR24_LS64, task_struct,
219 thread.fpu.fpr[24].val64[FPR_IDX(64, 0)]);
220 OFFSET(THREAD_FPR25_LS64, task_struct,
221 thread.fpu.fpr[25].val64[FPR_IDX(64, 0)]);
222 OFFSET(THREAD_FPR26_LS64, task_struct,
223 thread.fpu.fpr[26].val64[FPR_IDX(64, 0)]);
224 OFFSET(THREAD_FPR27_LS64, task_struct,
225 thread.fpu.fpr[27].val64[FPR_IDX(64, 0)]);
226 OFFSET(THREAD_FPR28_LS64, task_struct,
227 thread.fpu.fpr[28].val64[FPR_IDX(64, 0)]);
228 OFFSET(THREAD_FPR29_LS64, task_struct,
229 thread.fpu.fpr[29].val64[FPR_IDX(64, 0)]);
230 OFFSET(THREAD_FPR30_LS64, task_struct,
231 thread.fpu.fpr[30].val64[FPR_IDX(64, 0)]);
232 OFFSET(THREAD_FPR31_LS64, task_struct,
233 thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]);
234
fd04d206 235 OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
f7a46fa7 236 OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
fd04d206 237 BLANK();
1da177e4
LT		 238}
239
240void output_mm_defines(void)
241{
fd04d206
CL		 242 COMMENT("Size of struct page");
243 DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
244 BLANK();
245 COMMENT("Linux mm_struct offsets.");
246 OFFSET(MM_USERS, mm_struct, mm_users);
247 OFFSET(MM_PGD, mm_struct, pgd);
248 OFFSET(MM_CONTEXT, mm_struct, context);
249 BLANK();
fd04d206
CL		 250 DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
251 DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
252 DEFINE(_PTE_T_SIZE, sizeof(pte_t));
253 BLANK();
254 DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
325f8a0a 255#ifndef __PAGETABLE_PMD_FOLDED
fd04d206 256 DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
325f8a0a 257#endif
fd04d206
CL		 258 DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
259 BLANK();
260 DEFINE(_PGD_ORDER, PGD_ORDER);
325f8a0a 261#ifndef __PAGETABLE_PMD_FOLDED
fd04d206 262 DEFINE(_PMD_ORDER, PMD_ORDER);
325f8a0a 263#endif
fd04d206
CL		 264 DEFINE(_PTE_ORDER, PTE_ORDER);
265 BLANK();
266 DEFINE(_PMD_SHIFT, PMD_SHIFT);
267 DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
268 BLANK();
269 DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
270 DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
271 DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
272 BLANK();
20082595
RB		 273 DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
274 DEFINE(_PAGE_SIZE, PAGE_SIZE);
275 BLANK();
1da177e4
LT		 276}
277
e50c0a8f 278#ifdef CONFIG_32BIT
1da177e4
LT		 279void output_sc_defines(void)
280{
fd04d206
CL		 281 COMMENT("Linux sigcontext offsets.");
282 OFFSET(SC_REGS, sigcontext, sc_regs);
283 OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
284 OFFSET(SC_ACX, sigcontext, sc_acx);
285 OFFSET(SC_MDHI, sigcontext, sc_mdhi);
286 OFFSET(SC_MDLO, sigcontext, sc_mdlo);
287 OFFSET(SC_PC, sigcontext, sc_pc);
288 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
289 OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
290 OFFSET(SC_HI1, sigcontext, sc_hi1);
291 OFFSET(SC_LO1, sigcontext, sc_lo1);
292 OFFSET(SC_HI2, sigcontext, sc_hi2);
293 OFFSET(SC_LO2, sigcontext, sc_lo2);
294 OFFSET(SC_HI3, sigcontext, sc_hi3);
295 OFFSET(SC_LO3, sigcontext, sc_lo3);
296 BLANK();
1da177e4 297}
e50c0a8f
RB		 298#endif
299
300#ifdef CONFIG_64BIT
301void output_sc_defines(void)
302{
fd04d206
CL		 303 COMMENT("Linux sigcontext offsets.");
304 OFFSET(SC_REGS, sigcontext, sc_regs);
305 OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
306 OFFSET(SC_MDHI, sigcontext, sc_mdhi);
307 OFFSET(SC_MDLO, sigcontext, sc_mdlo);
308 OFFSET(SC_PC, sigcontext, sc_pc);
309 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
310 BLANK();
e50c0a8f
RB		 311}
312#endif
1da177e4
LT		 313
314#ifdef CONFIG_MIPS32_COMPAT
315void output_sc32_defines(void)
316{
fd04d206
CL		 317 COMMENT("Linux 32-bit sigcontext offsets.");
318 OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
319 OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
320 OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
321 BLANK();
1da177e4
LT		 322}
323#endif
324
325void output_signal_defined(void)
326{
fd04d206
CL		 327 COMMENT("Linux signal numbers.");
328 DEFINE(_SIGHUP, SIGHUP);
329 DEFINE(_SIGINT, SIGINT);
330 DEFINE(_SIGQUIT, SIGQUIT);
331 DEFINE(_SIGILL, SIGILL);
332 DEFINE(_SIGTRAP, SIGTRAP);
333 DEFINE(_SIGIOT, SIGIOT);
334 DEFINE(_SIGABRT, SIGABRT);
335 DEFINE(_SIGEMT, SIGEMT);
336 DEFINE(_SIGFPE, SIGFPE);
337 DEFINE(_SIGKILL, SIGKILL);
338 DEFINE(_SIGBUS, SIGBUS);
339 DEFINE(_SIGSEGV, SIGSEGV);
340 DEFINE(_SIGSYS, SIGSYS);
341 DEFINE(_SIGPIPE, SIGPIPE);
342 DEFINE(_SIGALRM, SIGALRM);
343 DEFINE(_SIGTERM, SIGTERM);
344 DEFINE(_SIGUSR1, SIGUSR1);
345 DEFINE(_SIGUSR2, SIGUSR2);
346 DEFINE(_SIGCHLD, SIGCHLD);
347 DEFINE(_SIGPWR, SIGPWR);
348 DEFINE(_SIGWINCH, SIGWINCH);
349 DEFINE(_SIGURG, SIGURG);
350 DEFINE(_SIGIO, SIGIO);
351 DEFINE(_SIGSTOP, SIGSTOP);
352 DEFINE(_SIGTSTP, SIGTSTP);
353 DEFINE(_SIGCONT, SIGCONT);
354 DEFINE(_SIGTTIN, SIGTTIN);
355 DEFINE(_SIGTTOU, SIGTTOU);
356 DEFINE(_SIGVTALRM, SIGVTALRM);
357 DEFINE(_SIGPROF, SIGPROF);
358 DEFINE(_SIGXCPU, SIGXCPU);
359 DEFINE(_SIGXFSZ, SIGXFSZ);
360 BLANK();
1da177e4
LT		 361}
362
babed555
DD		 363#ifdef CONFIG_CPU_CAVIUM_OCTEON
364void output_octeon_cop2_state_defines(void)
365{
366 COMMENT("Octeon specific octeon_cop2_state offsets.");
367 OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv);
368 OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length);
369 OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
370 OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat);
371 OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv);
372 OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
373 OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result);
374 OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
375 OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv);
376 OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key);
377 OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen);
378 OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result);
379 OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
380 OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
381 OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result);
382 OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
383 OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
384 OFFSET(THREAD_CP2, task_struct, thread.cp2);
385 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
386 BLANK();
387}
388#endif
363c55ca
WZ		 389
390#ifdef CONFIG_HIBERNATION
391void output_pbe_defines(void)
392{
393 COMMENT(" Linux struct pbe offsets. ");
394 OFFSET(PBE_ADDRESS, pbe, address);
395 OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
396 OFFSET(PBE_NEXT, pbe, next);
397 DEFINE(PBE_SIZE, sizeof(struct pbe));
398 BLANK();
399}
400#endif
12e25f8e 401
74e91335
JH		 402#ifdef CONFIG_CPU_PM
403void output_pm_defines(void)
404{
405 COMMENT(" PM offsets. ");
406#ifdef CONFIG_EVA
407 OFFSET(SSS_SEGCTL0, mips_static_suspend_state, segctl[0]);
408 OFFSET(SSS_SEGCTL1, mips_static_suspend_state, segctl[1]);
409 OFFSET(SSS_SEGCTL2, mips_static_suspend_state, segctl[2]);
410#endif
411 OFFSET(SSS_SP, mips_static_suspend_state, sp);
412 BLANK();
413}
414#endif
415
12e25f8e
SL		 416void output_kvm_defines(void)
417{
418 COMMENT(" KVM/MIPS Specfic offsets. ");
419 DEFINE(VCPU_ARCH_SIZE, sizeof(struct kvm_vcpu_arch));
420 OFFSET(VCPU_RUN, kvm_vcpu, run);
421 OFFSET(VCPU_HOST_ARCH, kvm_vcpu, arch);
422
423 OFFSET(VCPU_HOST_EBASE, kvm_vcpu_arch, host_ebase);
424 OFFSET(VCPU_GUEST_EBASE, kvm_vcpu_arch, guest_ebase);
425
426 OFFSET(VCPU_HOST_STACK, kvm_vcpu_arch, host_stack);
427 OFFSET(VCPU_HOST_GP, kvm_vcpu_arch, host_gp);
428
429 OFFSET(VCPU_HOST_CP0_BADVADDR, kvm_vcpu_arch, host_cp0_badvaddr);
430 OFFSET(VCPU_HOST_CP0_CAUSE, kvm_vcpu_arch, host_cp0_cause);
431 OFFSET(VCPU_HOST_EPC, kvm_vcpu_arch, host_cp0_epc);
432 OFFSET(VCPU_HOST_ENTRYHI, kvm_vcpu_arch, host_cp0_entryhi);
433
434 OFFSET(VCPU_GUEST_INST, kvm_vcpu_arch, guest_inst);
435
436 OFFSET(VCPU_R0, kvm_vcpu_arch, gprs[0]);
437 OFFSET(VCPU_R1, kvm_vcpu_arch, gprs[1]);
438 OFFSET(VCPU_R2, kvm_vcpu_arch, gprs[2]);
439 OFFSET(VCPU_R3, kvm_vcpu_arch, gprs[3]);
440 OFFSET(VCPU_R4, kvm_vcpu_arch, gprs[4]);
441 OFFSET(VCPU_R5, kvm_vcpu_arch, gprs[5]);
442 OFFSET(VCPU_R6, kvm_vcpu_arch, gprs[6]);
443 OFFSET(VCPU_R7, kvm_vcpu_arch, gprs[7]);
444 OFFSET(VCPU_R8, kvm_vcpu_arch, gprs[8]);
445 OFFSET(VCPU_R9, kvm_vcpu_arch, gprs[9]);
446 OFFSET(VCPU_R10, kvm_vcpu_arch, gprs[10]);
447 OFFSET(VCPU_R11, kvm_vcpu_arch, gprs[11]);
448 OFFSET(VCPU_R12, kvm_vcpu_arch, gprs[12]);
449 OFFSET(VCPU_R13, kvm_vcpu_arch, gprs[13]);
450 OFFSET(VCPU_R14, kvm_vcpu_arch, gprs[14]);
451 OFFSET(VCPU_R15, kvm_vcpu_arch, gprs[15]);
452 OFFSET(VCPU_R16, kvm_vcpu_arch, gprs[16]);
453 OFFSET(VCPU_R17, kvm_vcpu_arch, gprs[17]);
454 OFFSET(VCPU_R18, kvm_vcpu_arch, gprs[18]);
455 OFFSET(VCPU_R19, kvm_vcpu_arch, gprs[19]);
456 OFFSET(VCPU_R20, kvm_vcpu_arch, gprs[20]);
457 OFFSET(VCPU_R21, kvm_vcpu_arch, gprs[21]);
458 OFFSET(VCPU_R22, kvm_vcpu_arch, gprs[22]);
459 OFFSET(VCPU_R23, kvm_vcpu_arch, gprs[23]);
460 OFFSET(VCPU_R24, kvm_vcpu_arch, gprs[24]);
461 OFFSET(VCPU_R25, kvm_vcpu_arch, gprs[25]);
462 OFFSET(VCPU_R26, kvm_vcpu_arch, gprs[26]);
463 OFFSET(VCPU_R27, kvm_vcpu_arch, gprs[27]);
464 OFFSET(VCPU_R28, kvm_vcpu_arch, gprs[28]);
465 OFFSET(VCPU_R29, kvm_vcpu_arch, gprs[29]);
466 OFFSET(VCPU_R30, kvm_vcpu_arch, gprs[30]);
467 OFFSET(VCPU_R31, kvm_vcpu_arch, gprs[31]);
468 OFFSET(VCPU_LO, kvm_vcpu_arch, lo);
469 OFFSET(VCPU_HI, kvm_vcpu_arch, hi);
470 OFFSET(VCPU_PC, kvm_vcpu_arch, pc);
471 OFFSET(VCPU_COP0, kvm_vcpu_arch, cop0);
472 OFFSET(VCPU_GUEST_KERNEL_ASID, kvm_vcpu_arch, guest_kernel_asid);
473 OFFSET(VCPU_GUEST_USER_ASID, kvm_vcpu_arch, guest_user_asid);
474
475 OFFSET(COP0_TLB_HI, mips_coproc, reg[MIPS_CP0_TLB_HI][0]);
476 OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
477 BLANK();
478}
0ee958e1
PB		 479
480#ifdef CONFIG_MIPS_CPS
481void output_cps_defines(void)
482{
483 COMMENT(" MIPS CPS offsets. ");
245a7868
PB		 484
485 OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
486 OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
487 DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
488
489 OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
490 OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
491 OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
492 DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
0ee958e1
PB		 493}
494#endif
Linux kernel - Deliverables
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