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217dd11e RB |
1 | /* |
2 | * Copyright (C) 2000,2001,2004 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | */ | |
18 | #include <linux/clockchips.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/percpu.h> | |
631330f5 | 21 | #include <linux/smp.h> |
ca4d3e67 | 22 | #include <linux/irq.h> |
217dd11e RB |
23 | |
24 | #include <asm/addrspace.h> | |
25 | #include <asm/io.h> | |
26 | #include <asm/time.h> | |
27 | ||
28 | #include <asm/sibyte/bcm1480_regs.h> | |
29 | #include <asm/sibyte/sb1250_regs.h> | |
30 | #include <asm/sibyte/bcm1480_int.h> | |
31 | #include <asm/sibyte/bcm1480_scd.h> | |
32 | ||
33 | #include <asm/sibyte/sb1250.h> | |
34 | ||
35 | #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 | |
36 | #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 | |
37 | #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 | |
38 | ||
39 | /* | |
40 | * The general purpose timer ticks at 1MHz independent if | |
41 | * the rest of the system | |
42 | */ | |
1edf907a VK |
43 | |
44 | static int sibyte_set_periodic(struct clock_event_device *evt) | |
217dd11e RB |
45 | { |
46 | unsigned int cpu = smp_processor_id(); | |
47 | void __iomem *cfg, *init; | |
48 | ||
49 | cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); | |
50 | init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); | |
51 | ||
1edf907a VK |
52 | __raw_writeq(0, cfg); |
53 | __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); | |
54 | __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); | |
55 | return 0; | |
56 | } | |
57 | ||
58 | static int sibyte_shutdown(struct clock_event_device *evt) | |
59 | { | |
60 | unsigned int cpu = smp_processor_id(); | |
61 | void __iomem *cfg; | |
62 | ||
63 | cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); | |
64 | ||
65 | /* Stop the timer until we actually program a shot */ | |
66 | __raw_writeq(0, cfg); | |
67 | return 0; | |
217dd11e RB |
68 | } |
69 | ||
70 | static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd) | |
71 | { | |
72 | unsigned int cpu = smp_processor_id(); | |
73 | void __iomem *cfg, *init; | |
74 | ||
75 | cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); | |
76 | init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); | |
77 | ||
8dfa741f | 78 | __raw_writeq(0, cfg); |
217dd11e RB |
79 | __raw_writeq(delta - 1, init); |
80 | __raw_writeq(M_SCD_TIMER_ENABLE, cfg); | |
81 | ||
82 | return 0; | |
83 | } | |
84 | ||
85 | static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) | |
86 | { | |
87 | unsigned int cpu = smp_processor_id(); | |
88 | struct clock_event_device *cd = dev_id; | |
89 | void __iomem *cfg; | |
90 | unsigned long tmode; | |
91 | ||
1edf907a | 92 | if (clockevent_state_periodic(cd)) |
217dd11e RB |
93 | tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS; |
94 | else | |
95 | tmode = 0; | |
96 | ||
97 | /* ACK interrupt */ | |
98 | cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); | |
99 | ____raw_writeq(tmode, cfg); | |
100 | ||
101 | cd->event_handler(cd); | |
102 | ||
103 | return IRQ_HANDLED; | |
104 | } | |
105 | ||
106 | static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent); | |
107 | static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction); | |
108 | static DEFINE_PER_CPU(char [18], sibyte_hpt_name); | |
109 | ||
078a55fc | 110 | void sb1480_clockevent_init(void) |
217dd11e RB |
111 | { |
112 | unsigned int cpu = smp_processor_id(); | |
113 | unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; | |
114 | struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu); | |
115 | struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); | |
116 | unsigned char *name = per_cpu(sibyte_hpt_name, cpu); | |
117 | ||
118 | BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ | |
119 | ||
120 | sprintf(name, "bcm1480-counter-%d", cpu); | |
121 | cd->name = name; | |
122 | cd->features = CLOCK_EVT_FEAT_PERIODIC | | |
123 | CLOCK_EVT_FEAT_ONESHOT; | |
124 | clockevent_set_clock(cd, V_SCD_TIMER_FREQ); | |
125 | cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); | |
62247753 | 126 | cd->min_delta_ns = clockevent_delta2ns(2, cd); |
217dd11e RB |
127 | cd->rating = 200; |
128 | cd->irq = irq; | |
320ab2b0 | 129 | cd->cpumask = cpumask_of(cpu); |
217dd11e | 130 | cd->set_next_event = sibyte_next_event; |
1edf907a VK |
131 | cd->set_state_shutdown = sibyte_shutdown; |
132 | cd->set_state_periodic = sibyte_set_periodic; | |
133 | cd->set_state_oneshot = sibyte_shutdown; | |
217dd11e RB |
134 | clockevents_register_device(cd); |
135 | ||
136 | bcm1480_mask_irq(cpu, irq); | |
137 | ||
138 | /* | |
139 | * Map the timer interrupt to IP[4] of this cpu | |
140 | */ | |
141 | __raw_writeq(IMR_IP4_VAL, | |
142 | IOADDR(A_BCM1480_IMR_REGISTER(cpu, | |
143 | R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3))); | |
144 | ||
145 | bcm1480_unmask_irq(cpu, irq); | |
146 | ||
70342287 | 147 | action->handler = sibyte_counter_handler; |
8b5690f8 | 148 | action->flags = IRQF_PERCPU | IRQF_TIMER; |
217dd11e RB |
149 | action->name = name; |
150 | action->dev_id = cd; | |
07a80e49 | 151 | |
0de26520 | 152 | irq_set_affinity(irq, cpumask_of(cpu)); |
217dd11e RB |
153 | setup_irq(irq, action); |
154 | } |