[MIPS] Lasat: Fix overlap of interrupt number ranges.
[deliverable/linux.git] / arch / mips / kernel / cevt-bcm1480.c
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1/*
2 * Copyright (C) 2000,2001,2004 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#include <linux/clockchips.h>
19#include <linux/interrupt.h>
20#include <linux/percpu.h>
21
22#include <asm/addrspace.h>
23#include <asm/io.h>
24#include <asm/time.h>
25
26#include <asm/sibyte/bcm1480_regs.h>
27#include <asm/sibyte/sb1250_regs.h>
28#include <asm/sibyte/bcm1480_int.h>
29#include <asm/sibyte/bcm1480_scd.h>
30
31#include <asm/sibyte/sb1250.h>
32
33#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
34#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
35#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
36
37/*
38 * The general purpose timer ticks at 1MHz independent if
39 * the rest of the system
40 */
41static void sibyte_set_mode(enum clock_event_mode mode,
42 struct clock_event_device *evt)
43{
44 unsigned int cpu = smp_processor_id();
45 void __iomem *cfg, *init;
46
47 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
48 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
49
50 switch (mode) {
51 case CLOCK_EVT_MODE_PERIODIC:
52 __raw_writeq(0, cfg);
53 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
54 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
55 cfg);
56 break;
57
58 case CLOCK_EVT_MODE_ONESHOT:
59 /* Stop the timer until we actually program a shot */
60 case CLOCK_EVT_MODE_SHUTDOWN:
61 __raw_writeq(0, cfg);
62 break;
63
64 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
65 case CLOCK_EVT_MODE_RESUME:
66 ;
67 }
68}
69
70static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
71{
72 unsigned int cpu = smp_processor_id();
73 void __iomem *cfg, *init;
74
75 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
76 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
77
78 __raw_writeq(delta - 1, init);
79 __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
80
81 return 0;
82}
83
84static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
85{
86 unsigned int cpu = smp_processor_id();
87 struct clock_event_device *cd = dev_id;
88 void __iomem *cfg;
89 unsigned long tmode;
90
91 if (cd->mode == CLOCK_EVT_MODE_PERIODIC)
92 tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
93 else
94 tmode = 0;
95
96 /* ACK interrupt */
97 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
98 ____raw_writeq(tmode, cfg);
99
100 cd->event_handler(cd);
101
102 return IRQ_HANDLED;
103}
104
105static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
106static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
107static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
108
109void __cpuinit sb1480_clockevent_init(void)
110{
111 unsigned int cpu = smp_processor_id();
112 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
113 struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
114 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
115 unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
116
117 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
118
119 sprintf(name, "bcm1480-counter-%d", cpu);
120 cd->name = name;
121 cd->features = CLOCK_EVT_FEAT_PERIODIC |
122 CLOCK_EVT_FEAT_ONESHOT;
123 clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
124 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
125 cd->min_delta_ns = clockevent_delta2ns(1, cd);
126 cd->rating = 200;
127 cd->irq = irq;
128 cd->cpumask = cpumask_of_cpu(cpu);
129 cd->set_next_event = sibyte_next_event;
130 cd->set_mode = sibyte_set_mode;
131 clockevents_register_device(cd);
132
133 bcm1480_mask_irq(cpu, irq);
134
135 /*
136 * Map the timer interrupt to IP[4] of this cpu
137 */
138 __raw_writeq(IMR_IP4_VAL,
139 IOADDR(A_BCM1480_IMR_REGISTER(cpu,
140 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3)));
141
142 bcm1480_unmask_irq(cpu, irq);
143
144 action->handler = sibyte_counter_handler;
145 action->flags = IRQF_DISABLED | IRQF_PERCPU;
07a80e49 146 action->mask = cpumask_of_cpu(cpu);
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147 action->name = name;
148 action->dev_id = cd;
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149
150 irq_set_affinity(irq, cpumask_of_cpu(cpu));
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151 setup_irq(irq, action);
152}
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