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lib/string_helpers.c: make arrays static
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
4194318c 7 * Copyright (C) 2001, 2004 MIPS Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4
LT		 22#include <asm/cpu.h>
23#include <asm/fpu.h>
24#include <asm/mipsregs.h>
654f57bf 25#include <asm/watch.h>
06372a63 26#include <asm/elf.h>
a074f0e8 27#include <asm/spram.h>
949e51be
DD		 28#include <asm/uaccess.h>
29
1da177e4
LT		 30/*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
982f6ffe 37void (*cpu_wait)(void);
f8ede0f7 38EXPORT_SYMBOL(cpu_wait);
1da177e4
LT		 39
40static void r3081_wait(void)
41{
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44}
45
46static void r39xx_wait(void)
47{
60a6c377
AN		 48 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
1da177e4
LT		 52}
53
c65a5480 54extern void r4k_wait(void);
60a6c377
AN		 55
56/*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
8531a35e 63void r4k_wait_irqoff(void)
60a6c377
AN		 64{
65 local_irq_disable();
66 if (!need_resched())
8531a35e
KK		 67 __asm__(" .set push \n"
68 " .set mips3 \n"
60a6c377 69 " wait \n"
8531a35e 70 " .set pop \n");
60a6c377 71 local_irq_enable();
8531a35e
KK		 72 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n");
1da177e4
LT		 74}
75
5a812999
RB		 76/*
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
79 */
80static void rm7k_wait_irqoff(void)
81{
82 local_irq_disable();
83 if (!need_resched())
84 __asm__(
85 " .set push \n"
86 " .set mips3 \n"
87 " .set noat \n"
88 " mfc0 $1, $12 \n"
89 " sync \n"
90 " mtc0 $1, $12 # stalls until W stage \n"
91 " wait \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
93 " .set pop \n");
94 local_irq_enable();
95}
96
2882b0c6
ML		 97/*
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
101 */
494900af 102static void au1k_wait(void)
1da177e4 103{
60a6c377
AN		 104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
107 " sync \n"
108 " nop \n"
109 " wait \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " .set mips0 \n"
10f650db 115 : : "r" (au1k_wait));
1da177e4
LT		 116}
117
982f6ffe 118static int __initdata nowait;
55d04dff 119
f49a747c 120static int __init wait_disable(char *s)
55d04dff
RB		 121{
122 nowait = 1;
123
124 return 1;
125}
126
127__setup("nowait", wait_disable);
128
0103d23f
KC		 129static int __cpuinitdata mips_fpu_disabled;
130
131static int __init fpu_disable(char *s)
132{
133 cpu_data[0].options &= ~MIPS_CPU_FPU;
134 mips_fpu_disabled = 1;
135
136 return 1;
137}
138
139__setup("nofpu", fpu_disable);
140
141int __cpuinitdata mips_dsp_disabled;
142
143static int __init dsp_disable(char *s)
144{
145 cpu_data[0].ases &= ~MIPS_ASE_DSP;
146 mips_dsp_disabled = 1;
147
148 return 1;
149}
150
151__setup("nodsp", dsp_disable);
152
c65a5480 153void __init check_wait(void)
1da177e4
LT		 154{
155 struct cpuinfo_mips *c = &current_cpu_data;
156
55d04dff 157 if (nowait) {
c2379230 158 printk("Wait instruction disabled.\n");
55d04dff
RB		 159 return;
160 }
161
1da177e4
LT		 162 switch (c->cputype) {
163 case CPU_R3081:
164 case CPU_R3081E:
165 cpu_wait = r3081_wait;
1da177e4
LT		 166 break;
167 case CPU_TX3927:
168 cpu_wait = r39xx_wait;
1da177e4
LT		 169 break;
170 case CPU_R4200:
171/* case CPU_R4300: */
172 case CPU_R4600:
173 case CPU_R4640:
174 case CPU_R4650:
175 case CPU_R4700:
176 case CPU_R5000:
a644b277 177 case CPU_R5500:
1da177e4 178 case CPU_NEVADA:
1da177e4
LT		 179 case CPU_4KC:
180 case CPU_4KEC:
181 case CPU_4KSC:
182 case CPU_5KC:
1da177e4 183 case CPU_25KF:
4b3e975e 184 case CPU_PR4450:
602977b0
KC		 185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
0dd4781b 189 case CPU_CAVIUM_OCTEON:
6f329468 190 case CPU_CAVIUM_OCTEON_PLUS:
0e56b385 191 case CPU_CAVIUM_OCTEON2:
83ccf69d 192 case CPU_JZRISC:
11d48aac 193 case CPU_XLR:
a3d4fb2d 194 case CPU_XLP:
4b3e975e
RB		 195 cpu_wait = r4k_wait;
196 break;
197
5a812999
RB		 198 case CPU_RM7000:
199 cpu_wait = rm7k_wait_irqoff;
200 break;
201
4b3e975e 202 case CPU_24K:
bbc7f22f 203 case CPU_34K:
39b8d525 204 case CPU_1004K:
4b3e975e
RB		 205 cpu_wait = r4k_wait;
206 if (read_c0_config7() & MIPS_CONF7_WII)
207 cpu_wait = r4k_wait_irqoff;
208 break;
209
c620953c 210 case CPU_74K:
1da177e4 211 cpu_wait = r4k_wait;
4b3e975e
RB		 212 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
213 cpu_wait = r4k_wait_irqoff;
1da177e4 214 break;
4b3e975e 215
60a6c377
AN		 216 case CPU_TX49XX:
217 cpu_wait = r4k_wait_irqoff;
60a6c377 218 break;
270717a8 219 case CPU_ALCHEMY:
0c694de1 220 cpu_wait = au1k_wait;
1da177e4 221 break;
c8eae71d
RB		 222 case CPU_20KC:
223 /*
224 * WAIT on Rev1.0 has E1, E2, E3 and E16.
225 * WAIT on Rev2.0 and Rev3.0 has E16.
226 * Rev3.1 WAIT is nop, why bother
227 */
228 if ((c->processor_id & 0xff) <= 0x64)
229 break;
230
50da469a
RB		 231 /*
232 * Another rev is incremeting c0_count at a reduced clock
233 * rate while in WAIT mode. So we basically have the choice
234 * between using the cp0 timer as clocksource or avoiding
235 * the WAIT instruction. Until more details are known,
236 * disable the use of WAIT for 20Kc entirely.
237 cpu_wait = r4k_wait;
238 */
c8eae71d 239 break;
441ee341 240 case CPU_RM9000:
c2379230 241 if ((c->processor_id & 0x00ff) >= 0x40)
441ee341 242 cpu_wait = r4k_wait;
441ee341 243 break;
1da177e4 244 default:
1da177e4
LT		 245 break;
246 }
247}
248
9267a30d
MSJ		 249static inline void check_errata(void)
250{
251 struct cpuinfo_mips *c = &current_cpu_data;
252
253 switch (c->cputype) {
254 case CPU_34K:
255 /*
256 * Erratum "RPS May Cause Incorrect Instruction Execution"
257 * This code only handles VPE0, any SMP/SMTC/RTOS code
258 * making use of VPE1 will be responsable for that VPE.
259 */
260 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
261 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
262 break;
263 default:
264 break;
265 }
266}
267
1da177e4
LT		 268void __init check_bugs32(void)
269{
9267a30d 270 check_errata();
1da177e4
LT		 271}
272
273/*
274 * Probe whether cpu has config register by trying to play with
275 * alternate cache bit and see whether it matters.
276 * It's used by cpu_probe to distinguish between R3000A and R3081.
277 */
278static inline int cpu_has_confreg(void)
279{
280#ifdef CONFIG_CPU_R3000
281 extern unsigned long r3k_cache_size(unsigned long);
282 unsigned long size1, size2;
283 unsigned long cfg = read_c0_conf();
284
285 size1 = r3k_cache_size(ST0_ISC);
286 write_c0_conf(cfg ^ R30XX_CONF_AC);
287 size2 = r3k_cache_size(ST0_ISC);
288 write_c0_conf(cfg);
289 return size1 != size2;
290#else
291 return 0;
292#endif
293}
294
c094c99e
RM		 295static inline void set_elf_platform(int cpu, const char *plat)
296{
297 if (cpu == 0)
298 __elf_platform = plat;
299}
300
1da177e4
LT		 301/*
302 * Get the FPU Implementation/Revision.
303 */
304static inline unsigned long cpu_get_fpu_id(void)
305{
306 unsigned long tmp, fpu_id;
307
308 tmp = read_c0_status();
309 __enable_fpu();
310 fpu_id = read_32bit_cp1_register(CP1_REVISION);
311 write_c0_status(tmp);
312 return fpu_id;
313}
314
315/*
316 * Check the CPU has an FPU the official way.
317 */
318static inline int __cpu_has_fpu(void)
319{
320 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
321}
322
91dfc423
GR		 323static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
324{
325#ifdef __NEED_VMBITS_PROBE
5b7efa89 326 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 327 back_to_back_c0_hazard();
5b7efa89 328 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 329#endif
330}
331
02cf2119 332#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 333 | MIPS_CPU_COUNTER)
334
cea7e2df 335static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4
LT		 336{
337 switch (c->processor_id & 0xff00) {
338 case PRID_IMP_R2000:
339 c->cputype = CPU_R2000;
cea7e2df 340 __cpu_name[cpu] = "R2000";
1da177e4 341 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 342 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
343 MIPS_CPU_NOFPUEX;
1da177e4
LT		 344 if (__cpu_has_fpu())
345 c->options |= MIPS_CPU_FPU;
346 c->tlbsize = 64;
347 break;
348 case PRID_IMP_R3000:
cea7e2df
RB		 349 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
350 if (cpu_has_confreg()) {
1da177e4 351 c->cputype = CPU_R3081E;
cea7e2df
RB		 352 __cpu_name[cpu] = "R3081";
353 } else {
1da177e4 354 c->cputype = CPU_R3000A;
cea7e2df
RB		 355 __cpu_name[cpu] = "R3000A";
356 }
357 break;
358 } else {
1da177e4 359 c->cputype = CPU_R3000;
cea7e2df
RB		 360 __cpu_name[cpu] = "R3000";
361 }
1da177e4 362 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 363 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
364 MIPS_CPU_NOFPUEX;
1da177e4
LT		 365 if (__cpu_has_fpu())
366 c->options |= MIPS_CPU_FPU;
367 c->tlbsize = 64;
368 break;
369 case PRID_IMP_R4000:
370 if (read_c0_config() & CONF_SC) {
cea7e2df 371 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 372 c->cputype = CPU_R4400PC;
cea7e2df
RB		 373 __cpu_name[cpu] = "R4400PC";
374 } else {
1da177e4 375 c->cputype = CPU_R4000PC;
cea7e2df
RB		 376 __cpu_name[cpu] = "R4000PC";
377 }
1da177e4 378 } else {
cea7e2df 379 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 380 c->cputype = CPU_R4400SC;
cea7e2df
RB		 381 __cpu_name[cpu] = "R4400SC";
382 } else {
1da177e4 383 c->cputype = CPU_R4000SC;
cea7e2df
RB		 384 __cpu_name[cpu] = "R4000SC";
385 }
1da177e4
LT		 386 }
387
388 c->isa_level = MIPS_CPU_ISA_III;
389 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
390 MIPS_CPU_WATCH | MIPS_CPU_VCE |
391 MIPS_CPU_LLSC;
392 c->tlbsize = 48;
393 break;
394 case PRID_IMP_VR41XX:
395 switch (c->processor_id & 0xf0) {
1da177e4
LT		 396 case PRID_REV_VR4111:
397 c->cputype = CPU_VR4111;
cea7e2df 398 __cpu_name[cpu] = "NEC VR4111";
1da177e4 399 break;
1da177e4
LT		 400 case PRID_REV_VR4121:
401 c->cputype = CPU_VR4121;
cea7e2df 402 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 403 break;
404 case PRID_REV_VR4122:
cea7e2df 405 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 406 c->cputype = CPU_VR4122;
cea7e2df
RB		 407 __cpu_name[cpu] = "NEC VR4122";
408 } else {
1da177e4 409 c->cputype = CPU_VR4181A;
cea7e2df
RB		 410 __cpu_name[cpu] = "NEC VR4181A";
411 }
1da177e4
LT		 412 break;
413 case PRID_REV_VR4130:
cea7e2df 414 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 415 c->cputype = CPU_VR4131;
cea7e2df
RB		 416 __cpu_name[cpu] = "NEC VR4131";
417 } else {
1da177e4 418 c->cputype = CPU_VR4133;
cea7e2df
RB		 419 __cpu_name[cpu] = "NEC VR4133";
420 }
1da177e4
LT		 421 break;
422 default:
423 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
424 c->cputype = CPU_VR41XX;
cea7e2df 425 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 426 break;
427 }
428 c->isa_level = MIPS_CPU_ISA_III;
429 c->options = R4K_OPTS;
430 c->tlbsize = 32;
431 break;
432 case PRID_IMP_R4300:
433 c->cputype = CPU_R4300;
cea7e2df 434 __cpu_name[cpu] = "R4300";
1da177e4
LT		 435 c->isa_level = MIPS_CPU_ISA_III;
436 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
437 MIPS_CPU_LLSC;
438 c->tlbsize = 32;
439 break;
440 case PRID_IMP_R4600:
441 c->cputype = CPU_R4600;
cea7e2df 442 __cpu_name[cpu] = "R4600";
1da177e4 443 c->isa_level = MIPS_CPU_ISA_III;
075e7502
TS		 444 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
445 MIPS_CPU_LLSC;
1da177e4
LT		 446 c->tlbsize = 48;
447 break;
448 #if 0
449 case PRID_IMP_R4650:
450 /*
451 * This processor doesn't have an MMU, so it's not
452 * "real easy" to run Linux on it. It is left purely
453 * for documentation. Commented out because it shares
454 * it's c0_prid id number with the TX3900.
455 */
a3dddd56 456 c->cputype = CPU_R4650;
cea7e2df 457 __cpu_name[cpu] = "R4650";
1da177e4
LT		 458 c->isa_level = MIPS_CPU_ISA_III;
459 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
460 c->tlbsize = 48;
461 break;
462 #endif
463 case PRID_IMP_TX39:
464 c->isa_level = MIPS_CPU_ISA_I;
02cf2119 465 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 466
467 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
468 c->cputype = CPU_TX3927;
cea7e2df 469 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 470 c->tlbsize = 64;
471 } else {
472 switch (c->processor_id & 0xff) {
473 case PRID_REV_TX3912:
474 c->cputype = CPU_TX3912;
cea7e2df 475 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 476 c->tlbsize = 32;
477 break;
478 case PRID_REV_TX3922:
479 c->cputype = CPU_TX3922;
cea7e2df 480 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 481 c->tlbsize = 64;
482 break;
1da177e4
LT		 483 }
484 }
485 break;
486 case PRID_IMP_R4700:
487 c->cputype = CPU_R4700;
cea7e2df 488 __cpu_name[cpu] = "R4700";
1da177e4
LT		 489 c->isa_level = MIPS_CPU_ISA_III;
490 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
491 MIPS_CPU_LLSC;
492 c->tlbsize = 48;
493 break;
494 case PRID_IMP_TX49:
495 c->cputype = CPU_TX49XX;
cea7e2df 496 __cpu_name[cpu] = "R49XX";
1da177e4
LT		 497 c->isa_level = MIPS_CPU_ISA_III;
498 c->options = R4K_OPTS | MIPS_CPU_LLSC;
499 if (!(c->processor_id & 0x08))
500 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
501 c->tlbsize = 48;
502 break;
503 case PRID_IMP_R5000:
504 c->cputype = CPU_R5000;
cea7e2df 505 __cpu_name[cpu] = "R5000";
1da177e4
LT		 506 c->isa_level = MIPS_CPU_ISA_IV;
507 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
508 MIPS_CPU_LLSC;
509 c->tlbsize = 48;
510 break;
511 case PRID_IMP_R5432:
512 c->cputype = CPU_R5432;
cea7e2df 513 __cpu_name[cpu] = "R5432";
1da177e4
LT		 514 c->isa_level = MIPS_CPU_ISA_IV;
515 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
516 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
517 c->tlbsize = 48;
518 break;
519 case PRID_IMP_R5500:
520 c->cputype = CPU_R5500;
cea7e2df 521 __cpu_name[cpu] = "R5500";
1da177e4
LT		 522 c->isa_level = MIPS_CPU_ISA_IV;
523 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
524 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
525 c->tlbsize = 48;
526 break;
527 case PRID_IMP_NEVADA:
528 c->cputype = CPU_NEVADA;
cea7e2df 529 __cpu_name[cpu] = "Nevada";
1da177e4
LT		 530 c->isa_level = MIPS_CPU_ISA_IV;
531 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
532 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
533 c->tlbsize = 48;
534 break;
535 case PRID_IMP_R6000:
536 c->cputype = CPU_R6000;
cea7e2df 537 __cpu_name[cpu] = "R6000";
1da177e4
LT		 538 c->isa_level = MIPS_CPU_ISA_II;
539 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
540 MIPS_CPU_LLSC;
541 c->tlbsize = 32;
542 break;
543 case PRID_IMP_R6000A:
544 c->cputype = CPU_R6000A;
cea7e2df 545 __cpu_name[cpu] = "R6000A";
1da177e4
LT		 546 c->isa_level = MIPS_CPU_ISA_II;
547 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
548 MIPS_CPU_LLSC;
549 c->tlbsize = 32;
550 break;
551 case PRID_IMP_RM7000:
552 c->cputype = CPU_RM7000;
cea7e2df 553 __cpu_name[cpu] = "RM7000";
1da177e4
LT		 554 c->isa_level = MIPS_CPU_ISA_IV;
555 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
556 MIPS_CPU_LLSC;
557 /*
558 * Undocumented RM7000: Bit 29 in the info register of
559 * the RM7000 v2.0 indicates if the TLB has 48 or 64
560 * entries.
561 *
562 * 29 1 => 64 entry JTLB
563 * 0 => 48 entry JTLB
564 */
565 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
566 break;
567 case PRID_IMP_RM9000:
568 c->cputype = CPU_RM9000;
cea7e2df 569 __cpu_name[cpu] = "RM9000";
1da177e4
LT		 570 c->isa_level = MIPS_CPU_ISA_IV;
571 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
572 MIPS_CPU_LLSC;
573 /*
574 * Bit 29 in the info register of the RM9000
575 * indicates if the TLB has 48 or 64 entries.
576 *
577 * 29 1 => 64 entry JTLB
578 * 0 => 48 entry JTLB
579 */
580 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
581 break;
582 case PRID_IMP_R8000:
583 c->cputype = CPU_R8000;
cea7e2df 584 __cpu_name[cpu] = "RM8000";
1da177e4
LT		 585 c->isa_level = MIPS_CPU_ISA_IV;
586 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
587 MIPS_CPU_FPU | MIPS_CPU_32FPR |
588 MIPS_CPU_LLSC;
589 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
590 break;
591 case PRID_IMP_R10000:
592 c->cputype = CPU_R10000;
cea7e2df 593 __cpu_name[cpu] = "R10000";
1da177e4 594 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 595 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 596 MIPS_CPU_FPU | MIPS_CPU_32FPR |
597 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
598 MIPS_CPU_LLSC;
599 c->tlbsize = 64;
600 break;
601 case PRID_IMP_R12000:
602 c->cputype = CPU_R12000;
cea7e2df 603 __cpu_name[cpu] = "R12000";
1da177e4 604 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 605 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 606 MIPS_CPU_FPU | MIPS_CPU_32FPR |
607 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
608 MIPS_CPU_LLSC;
609 c->tlbsize = 64;
610 break;
44d921b2
K		 611 case PRID_IMP_R14000:
612 c->cputype = CPU_R14000;
cea7e2df 613 __cpu_name[cpu] = "R14000";
44d921b2
K		 614 c->isa_level = MIPS_CPU_ISA_IV;
615 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
616 MIPS_CPU_FPU | MIPS_CPU_32FPR |
617 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
618 MIPS_CPU_LLSC;
619 c->tlbsize = 64;
620 break;
2a21c730
FZ		 621 case PRID_IMP_LOONGSON2:
622 c->cputype = CPU_LOONGSON2;
cea7e2df 623 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 624
625 switch (c->processor_id & PRID_REV_MASK) {
626 case PRID_REV_LOONGSON2E:
627 set_elf_platform(cpu, "loongson2e");
628 break;
629 case PRID_REV_LOONGSON2F:
630 set_elf_platform(cpu, "loongson2f");
631 break;
632 }
633
2a21c730
FZ		 634 c->isa_level = MIPS_CPU_ISA_III;
635 c->options = R4K_OPTS |
636 MIPS_CPU_FPU | MIPS_CPU_LLSC |
637 MIPS_CPU_32FPR;
638 c->tlbsize = 64;
639 break;
1da177e4
LT		 640 }
641}
642
234fcd14 643static char unknown_isa[] __cpuinitdata = KERN_ERR \
b4672d37
RB		 644 "Unsupported ISA type, c0.config0: %d.";
645
4194318c 646static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4 647{
4194318c
RB		 648 unsigned int config0;
649 int isa;
1da177e4 650
4194318c
RB		 651 config0 = read_c0_config();
652
653 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
02cf2119 654 c->options |= MIPS_CPU_TLB;
4194318c
RB		 655 isa = (config0 & MIPS_CONF_AT) >> 13;
656 switch (isa) {
657 case 0:
3a01c49a 658 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 659 case 0:
660 c->isa_level = MIPS_CPU_ISA_M32R1;
661 break;
662 case 1:
663 c->isa_level = MIPS_CPU_ISA_M32R2;
664 break;
665 default:
666 goto unknown;
667 }
4194318c
RB		 668 break;
669 case 2:
3a01c49a 670 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 671 case 0:
672 c->isa_level = MIPS_CPU_ISA_M64R1;
673 break;
674 case 1:
675 c->isa_level = MIPS_CPU_ISA_M64R2;
676 break;
677 default:
678 goto unknown;
679 }
4194318c
RB		 680 break;
681 default:
b4672d37 682 goto unknown;
4194318c
RB		 683 }
684
685 return config0 & MIPS_CONF_M;
b4672d37
RB		 686
687unknown:
688 panic(unknown_isa, config0);
4194318c
RB		 689}
690
691static inline unsigned int decode_config1(struct cpuinfo_mips *c)
692{
693 unsigned int config1;
1da177e4 694
1da177e4 695 config1 = read_c0_config1();
4194318c
RB		 696
697 if (config1 & MIPS_CONF1_MD)
698 c->ases |= MIPS_ASE_MDMX;
699 if (config1 & MIPS_CONF1_WR)
1da177e4 700 c->options |= MIPS_CPU_WATCH;
4194318c
RB		 701 if (config1 & MIPS_CONF1_CA)
702 c->ases |= MIPS_ASE_MIPS16;
703 if (config1 & MIPS_CONF1_EP)
1da177e4 704 c->options |= MIPS_CPU_EJTAG;
4194318c 705 if (config1 & MIPS_CONF1_FP) {
1da177e4
LT		 706 c->options |= MIPS_CPU_FPU;
707 c->options |= MIPS_CPU_32FPR;
708 }
4194318c
RB		 709 if (cpu_has_tlb)
710 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
711
712 return config1 & MIPS_CONF_M;
713}
714
715static inline unsigned int decode_config2(struct cpuinfo_mips *c)
716{
717 unsigned int config2;
718
719 config2 = read_c0_config2();
720
721 if (config2 & MIPS_CONF2_SL)
722 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
723
724 return config2 & MIPS_CONF_M;
725}
726
727static inline unsigned int decode_config3(struct cpuinfo_mips *c)
728{
729 unsigned int config3;
730
731 config3 = read_c0_config3();
732
733 if (config3 & MIPS_CONF3_SM)
734 c->ases |= MIPS_ASE_SMARTMIPS;
e50c0a8f
RB		 735 if (config3 & MIPS_CONF3_DSP)
736 c->ases |= MIPS_ASE_DSP;
8f40611d
RB		 737 if (config3 & MIPS_CONF3_VINT)
738 c->options |= MIPS_CPU_VINT;
739 if (config3 & MIPS_CONF3_VEIC)
740 c->options |= MIPS_CPU_VEIC;
741 if (config3 & MIPS_CONF3_MT)
e0daad44 742 c->ases |= MIPS_ASE_MIPSMT;
a3692020
RB		 743 if (config3 & MIPS_CONF3_ULRI)
744 c->options |= MIPS_CPU_ULRI;
4194318c
RB		 745
746 return config3 & MIPS_CONF_M;
747}
748
1b362e3e
DD		 749static inline unsigned int decode_config4(struct cpuinfo_mips *c)
750{
751 unsigned int config4;
752
753 config4 = read_c0_config4();
754
755 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
756 && cpu_has_tlb)
757 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
758
e77c32fe
DD		 759 c->kscratch_mask = (config4 >> 16) & 0xff;
760
1b362e3e
DD		 761 return config4 & MIPS_CONF_M;
762}
763
234fcd14 764static void __cpuinit decode_configs(struct cpuinfo_mips *c)
4194318c 765{
558ce124
RB		 766 int ok;
767
4194318c 768 /* MIPS32 or MIPS64 compliant CPU. */
02cf2119
RB		 769 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
770 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
4194318c 771
1da177e4
LT		 772 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
773
558ce124
RB		 774 ok = decode_config0(c); /* Read Config registers. */
775 BUG_ON(!ok); /* Arch spec violation! */
776 if (ok)
777 ok = decode_config1(c);
778 if (ok)
779 ok = decode_config2(c);
780 if (ok)
781 ok = decode_config3(c);
1b362e3e
DD		 782 if (ok)
783 ok = decode_config4(c);
558ce124
RB		 784
785 mips_probe_watch_registers(c);
0c2f4551
DD		 786
787 if (cpu_has_mips_r2)
788 c->core = read_c0_ebase() & 0x3ff;
1da177e4
LT		 789}
790
cea7e2df 791static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 792{
4194318c 793 decode_configs(c);
1da177e4
LT		 794 switch (c->processor_id & 0xff00) {
795 case PRID_IMP_4KC:
796 c->cputype = CPU_4KC;
cea7e2df 797 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 798 break;
799 case PRID_IMP_4KEC:
2b07bd02
RB		 800 case PRID_IMP_4KECR2:
801 c->cputype = CPU_4KEC;
cea7e2df 802 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 803 break;
1da177e4 804 case PRID_IMP_4KSC:
8afcb5d8 805 case PRID_IMP_4KSD:
1da177e4 806 c->cputype = CPU_4KSC;
cea7e2df 807 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 808 break;
809 case PRID_IMP_5KC:
810 c->cputype = CPU_5KC;
cea7e2df 811 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4
LT		 812 break;
813 case PRID_IMP_20KC:
814 c->cputype = CPU_20KC;
cea7e2df 815 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 816 break;
817 case PRID_IMP_24K:
e50c0a8f 818 case PRID_IMP_24KE:
1da177e4 819 c->cputype = CPU_24K;
cea7e2df 820 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4
LT		 821 break;
822 case PRID_IMP_25KF:
823 c->cputype = CPU_25KF;
cea7e2df 824 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 825 break;
bbc7f22f
RB		 826 case PRID_IMP_34K:
827 c->cputype = CPU_34K;
cea7e2df 828 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 829 break;
c620953c
CD		 830 case PRID_IMP_74K:
831 c->cputype = CPU_74K;
cea7e2df 832 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 833 break;
39b8d525
RB		 834 case PRID_IMP_1004K:
835 c->cputype = CPU_1004K;
cea7e2df 836 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 837 break;
1da177e4 838 }
0b6d497f
CD		 839
840 spram_config();
1da177e4
LT		 841}
842
cea7e2df 843static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 844{
4194318c 845 decode_configs(c);
1da177e4
LT		 846 switch (c->processor_id & 0xff00) {
847 case PRID_IMP_AU1_REV1:
848 case PRID_IMP_AU1_REV2:
270717a8 849 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 850 switch ((c->processor_id >> 24) & 0xff) {
851 case 0:
cea7e2df 852 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 853 break;
854 case 1:
cea7e2df 855 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 856 break;
857 case 2:
cea7e2df 858 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 859 break;
860 case 3:
cea7e2df 861 __cpu_name[cpu] = "Au1550";
1da177e4 862 break;
e3ad1c23 863 case 4:
cea7e2df 864 __cpu_name[cpu] = "Au1200";
270717a8 865 if ((c->processor_id & 0xff) == 2)
cea7e2df 866 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 867 break;
868 case 5:
cea7e2df 869 __cpu_name[cpu] = "Au1210";
e3ad1c23 870 break;
1da177e4 871 default:
270717a8 872 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 873 break;
874 }
1da177e4
LT		 875 break;
876 }
877}
878
cea7e2df 879static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 880{
4194318c 881 decode_configs(c);
02cf2119 882
1da177e4
LT		 883 switch (c->processor_id & 0xff00) {
884 case PRID_IMP_SB1:
885 c->cputype = CPU_SB1;
cea7e2df 886 __cpu_name[cpu] = "SiByte SB1";
1da177e4 887 /* FPU in pass1 is known to have issues. */
aa32374a 888 if ((c->processor_id & 0xff) < 0x02)
010b853b 889 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 890 break;
93ce2f52
AI		 891 case PRID_IMP_SB1A:
892 c->cputype = CPU_SB1A;
cea7e2df 893 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 894 break;
1da177e4
LT		 895 }
896}
897
cea7e2df 898static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 899{
4194318c 900 decode_configs(c);
1da177e4
LT		 901 switch (c->processor_id & 0xff00) {
902 case PRID_IMP_SR71000:
903 c->cputype = CPU_SR71000;
cea7e2df 904 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 905 c->scache.ways = 8;
906 c->tlbsize = 64;
907 break;
908 }
909}
910
cea7e2df 911static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 912{
913 decode_configs(c);
914 switch (c->processor_id & 0xff00) {
915 case PRID_IMP_PR4450:
916 c->cputype = CPU_PR4450;
cea7e2df 917 __cpu_name[cpu] = "Philips PR4450";
e7958bb9 918 c->isa_level = MIPS_CPU_ISA_M32R1;
bdf21b18 919 break;
bdf21b18
PP		 920 }
921}
922
cea7e2df 923static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 924{
925 decode_configs(c);
926 switch (c->processor_id & 0xff00) {
190fca3e
KC		 927 case PRID_IMP_BMIPS32_REV4:
928 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 929 c->cputype = CPU_BMIPS32;
930 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 931 set_elf_platform(cpu, "bmips32");
602977b0
KC		 932 break;
933 case PRID_IMP_BMIPS3300:
934 case PRID_IMP_BMIPS3300_ALT:
935 case PRID_IMP_BMIPS3300_BUG:
936 c->cputype = CPU_BMIPS3300;
937 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 938 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 939 break;
940 case PRID_IMP_BMIPS43XX: {
941 int rev = c->processor_id & 0xff;
942
943 if (rev >= PRID_REV_BMIPS4380_LO &&
944 rev <= PRID_REV_BMIPS4380_HI) {
945 c->cputype = CPU_BMIPS4380;
946 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 947 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 948 } else {
949 c->cputype = CPU_BMIPS4350;
950 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 951 set_elf_platform(cpu, "bmips4350");
602977b0 952 }
0de663ef 953 break;
602977b0
KC		 954 }
955 case PRID_IMP_BMIPS5000:
956 c->cputype = CPU_BMIPS5000;
957 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 958 set_elf_platform(cpu, "bmips5000");
602977b0 959 c->options |= MIPS_CPU_ULRI;
0de663ef 960 break;
1c0c13eb
AJ		 961 }
962}
963
0dd4781b
DD		 964static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
965{
966 decode_configs(c);
967 switch (c->processor_id & 0xff00) {
968 case PRID_IMP_CAVIUM_CN38XX:
969 case PRID_IMP_CAVIUM_CN31XX:
970 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 971 c->cputype = CPU_CAVIUM_OCTEON;
972 __cpu_name[cpu] = "Cavium Octeon";
973 goto platform;
0dd4781b
DD		 974 case PRID_IMP_CAVIUM_CN58XX:
975 case PRID_IMP_CAVIUM_CN56XX:
976 case PRID_IMP_CAVIUM_CN50XX:
977 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 978 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
979 __cpu_name[cpu] = "Cavium Octeon+";
980platform:
c094c99e 981 set_elf_platform(cpu, "octeon");
0dd4781b 982 break;
a1431b61 983 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 984 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 985 case PRID_IMP_CAVIUM_CN66XX:
986 case PRID_IMP_CAVIUM_CN68XX:
0e56b385
DD		 987 c->cputype = CPU_CAVIUM_OCTEON2;
988 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 989 set_elf_platform(cpu, "octeon2");
0e56b385 990 break;
0dd4781b
DD		 991 default:
992 printk(KERN_INFO "Unknown Octeon chip!\n");
993 c->cputype = CPU_UNKNOWN;
994 break;
995 }
996}
997
83ccf69d
LPC		 998static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
999{
1000 decode_configs(c);
1001 /* JZRISC does not implement the CP0 counter. */
1002 c->options &= ~MIPS_CPU_COUNTER;
1003 switch (c->processor_id & 0xff00) {
1004 case PRID_IMP_JZRISC:
1005 c->cputype = CPU_JZRISC;
1006 __cpu_name[cpu] = "Ingenic JZRISC";
1007 break;
1008 default:
1009 panic("Unknown Ingenic Processor ID!");
1010 break;
1011 }
1012}
1013
a7117c6b
J		 1014static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1015{
1016 decode_configs(c);
1017
809f36c6
ML		 1018 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1019 c->cputype = CPU_ALCHEMY;
1020 __cpu_name[cpu] = "Au1300";
1021 /* following stuff is not for Alchemy */
1022 return;
1023 }
1024
a7117c6b
J		 1025 c->options = (MIPS_CPU_TLB |
1026 MIPS_CPU_4KEX |
1027 MIPS_CPU_COUNTER |
1028 MIPS_CPU_DIVEC |
1029 MIPS_CPU_WATCH |
1030 MIPS_CPU_EJTAG |
1031 MIPS_CPU_LLSC);
1032
1033 switch (c->processor_id & 0xff00) {
2aa54b20
J		 1034 case PRID_IMP_NETLOGIC_XLP8XX:
1035 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1036 c->cputype = CPU_XLP;
1037 __cpu_name[cpu] = "Netlogic XLP";
1038 break;
1039
a7117c6b
J		 1040 case PRID_IMP_NETLOGIC_XLR732:
1041 case PRID_IMP_NETLOGIC_XLR716:
1042 case PRID_IMP_NETLOGIC_XLR532:
1043 case PRID_IMP_NETLOGIC_XLR308:
1044 case PRID_IMP_NETLOGIC_XLR532C:
1045 case PRID_IMP_NETLOGIC_XLR516C:
1046 case PRID_IMP_NETLOGIC_XLR508C:
1047 case PRID_IMP_NETLOGIC_XLR308C:
1048 c->cputype = CPU_XLR;
1049 __cpu_name[cpu] = "Netlogic XLR";
1050 break;
1051
1052 case PRID_IMP_NETLOGIC_XLS608:
1053 case PRID_IMP_NETLOGIC_XLS408:
1054 case PRID_IMP_NETLOGIC_XLS404:
1055 case PRID_IMP_NETLOGIC_XLS208:
1056 case PRID_IMP_NETLOGIC_XLS204:
1057 case PRID_IMP_NETLOGIC_XLS108:
1058 case PRID_IMP_NETLOGIC_XLS104:
1059 case PRID_IMP_NETLOGIC_XLS616B:
1060 case PRID_IMP_NETLOGIC_XLS608B:
1061 case PRID_IMP_NETLOGIC_XLS416B:
1062 case PRID_IMP_NETLOGIC_XLS412B:
1063 case PRID_IMP_NETLOGIC_XLS408B:
1064 case PRID_IMP_NETLOGIC_XLS404B:
1065 c->cputype = CPU_XLR;
1066 __cpu_name[cpu] = "Netlogic XLS";
1067 break;
1068
1069 default:
a3d4fb2d 1070 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1071 c->processor_id);
1072 c->cputype = CPU_XLR;
1073 break;
1074 }
1075
a3d4fb2d
J		 1076 if (c->cputype == CPU_XLP) {
1077 c->isa_level = MIPS_CPU_ISA_M64R2;
1078 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1079 /* This will be updated again after all threads are woken up */
1080 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1081 } else {
1082 c->isa_level = MIPS_CPU_ISA_M64R1;
1083 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1084 }
a7117c6b
J		 1085}
1086
949e51be
DD		 1087#ifdef CONFIG_64BIT
1088/* For use by uaccess.h */
1089u64 __ua_limit;
1090EXPORT_SYMBOL(__ua_limit);
1091#endif
1092
9966db25 1093const char *__cpu_name[NR_CPUS];
874fd3b5 1094const char *__elf_platform;
9966db25 1095
234fcd14 1096__cpuinit void cpu_probe(void)
1da177e4
LT		 1097{
1098 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1099 unsigned int cpu = smp_processor_id();
1da177e4
LT		 1100
1101 c->processor_id = PRID_IMP_UNKNOWN;
1102 c->fpu_id = FPIR_IMP_NONE;
1103 c->cputype = CPU_UNKNOWN;
1104
1105 c->processor_id = read_c0_prid();
1106 switch (c->processor_id & 0xff0000) {
1107 case PRID_COMP_LEGACY:
cea7e2df 1108 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1109 break;
1110 case PRID_COMP_MIPS:
cea7e2df 1111 cpu_probe_mips(c, cpu);
1da177e4
LT		 1112 break;
1113 case PRID_COMP_ALCHEMY:
cea7e2df 1114 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1115 break;
1116 case PRID_COMP_SIBYTE:
cea7e2df 1117 cpu_probe_sibyte(c, cpu);
1da177e4 1118 break;
1c0c13eb 1119 case PRID_COMP_BROADCOM:
cea7e2df 1120 cpu_probe_broadcom(c, cpu);
1c0c13eb 1121 break;
1da177e4 1122 case PRID_COMP_SANDCRAFT:
cea7e2df 1123 cpu_probe_sandcraft(c, cpu);
1da177e4 1124 break;
a92b0588 1125 case PRID_COMP_NXP:
cea7e2df 1126 cpu_probe_nxp(c, cpu);
a3dddd56 1127 break;
0dd4781b
DD		 1128 case PRID_COMP_CAVIUM:
1129 cpu_probe_cavium(c, cpu);
1130 break;
83ccf69d
LPC		 1131 case PRID_COMP_INGENIC:
1132 cpu_probe_ingenic(c, cpu);
1133 break;
a7117c6b
J		 1134 case PRID_COMP_NETLOGIC:
1135 cpu_probe_netlogic(c, cpu);
1136 break;
1da177e4 1137 }
dec8b1ca 1138
cea7e2df
RB		 1139 BUG_ON(!__cpu_name[cpu]);
1140 BUG_ON(c->cputype == CPU_UNKNOWN);
1141
dec8b1ca
FBH		 1142 /*
1143 * Platform code can force the cpu type to optimize code
1144 * generation. In that case be sure the cpu type is correctly
1145 * manually setup otherwise it could trigger some nasty bugs.
1146 */
1147 BUG_ON(current_cpu_type() != c->cputype);
1148
0103d23f
KC		 1149 if (mips_fpu_disabled)
1150 c->options &= ~MIPS_CPU_FPU;
1151
1152 if (mips_dsp_disabled)
1153 c->ases &= ~MIPS_ASE_DSP;
1154
4194318c 1155 if (c->options & MIPS_CPU_FPU) {
1da177e4 1156 c->fpu_id = cpu_get_fpu_id();
4194318c 1157
e7958bb9 1158 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
b4672d37
RB		 1159 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1160 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1161 c->isa_level == MIPS_CPU_ISA_M64R2) {
4194318c
RB		 1162 if (c->fpu_id & MIPS_FPIR_3D)
1163 c->ases |= MIPS_ASE_MIPS3D;
1164 }
1165 }
9966db25 1166
f6771dbb
RB		 1167 if (cpu_has_mips_r2)
1168 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1169 else
1170 c->srsets = 1;
91dfc423
GR		 1171
1172 cpu_probe_vmbits(c);
949e51be
DD		 1173
1174#ifdef CONFIG_64BIT
1175 if (cpu == 0)
1176 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1177#endif
1da177e4
LT		 1178}
1179
234fcd14 1180__cpuinit void cpu_report(void)
1da177e4
LT		 1181{
1182 struct cpuinfo_mips *c = &current_cpu_data;
1183
9966db25
RB		 1184 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1185 c->processor_id, cpu_name_string());
1da177e4 1186 if (c->options & MIPS_CPU_FPU)
9966db25 1187 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 1188}
Linux kernel - Deliverables
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