Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Processor capabilities determination functions. | |
3 | * | |
4 | * Copyright (C) xxxx the Anonymous | |
010b853b | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
4194318c | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
70342287 | 7 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ptrace.h> | |
631330f5 | 17 | #include <linux/smp.h> |
1da177e4 | 18 | #include <linux/stddef.h> |
73bc256d | 19 | #include <linux/export.h> |
1da177e4 | 20 | |
5759906c | 21 | #include <asm/bugs.h> |
1da177e4 | 22 | #include <asm/cpu.h> |
f6843626 | 23 | #include <asm/cpu-features.h> |
69f24d17 | 24 | #include <asm/cpu-type.h> |
1da177e4 LT |
25 | #include <asm/fpu.h> |
26 | #include <asm/mipsregs.h> | |
30ee615b | 27 | #include <asm/mipsmtregs.h> |
a5e9a69e | 28 | #include <asm/msa.h> |
654f57bf | 29 | #include <asm/watch.h> |
06372a63 | 30 | #include <asm/elf.h> |
4f12b91d | 31 | #include <asm/pgtable-bits.h> |
a074f0e8 | 32 | #include <asm/spram.h> |
949e51be DD |
33 | #include <asm/uaccess.h> |
34 | ||
e14f1db7 PB |
35 | /* Hardware capabilities */ |
36 | unsigned int elf_hwcap __read_mostly; | |
37 | ||
7aecd5ca MR |
38 | /* |
39 | * Get the FPU Implementation/Revision. | |
40 | */ | |
41 | static inline unsigned long cpu_get_fpu_id(void) | |
42 | { | |
43 | unsigned long tmp, fpu_id; | |
44 | ||
45 | tmp = read_c0_status(); | |
46 | __enable_fpu(FPU_AS_IS); | |
47 | fpu_id = read_32bit_cp1_register(CP1_REVISION); | |
48 | write_c0_status(tmp); | |
49 | return fpu_id; | |
50 | } | |
51 | ||
52 | /* | |
53 | * Check if the CPU has an external FPU. | |
54 | */ | |
55 | static inline int __cpu_has_fpu(void) | |
56 | { | |
57 | return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; | |
58 | } | |
59 | ||
60 | static inline unsigned long cpu_get_msa_id(void) | |
61 | { | |
62 | unsigned long status, msa_id; | |
63 | ||
64 | status = read_c0_status(); | |
65 | __enable_fpu(FPU_64BIT); | |
66 | enable_msa(); | |
67 | msa_id = read_msa_ir(); | |
68 | disable_msa(); | |
69 | write_c0_status(status); | |
70 | return msa_id; | |
71 | } | |
72 | ||
9b26616c MR |
73 | /* |
74 | * Determine the FCSR mask for FPU hardware. | |
75 | */ | |
76 | static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) | |
77 | { | |
78 | unsigned long sr, mask, fcsr, fcsr0, fcsr1; | |
79 | ||
90b712dd | 80 | fcsr = c->fpu_csr31; |
9b26616c MR |
81 | mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; |
82 | ||
83 | sr = read_c0_status(); | |
84 | __enable_fpu(FPU_AS_IS); | |
85 | ||
9b26616c MR |
86 | fcsr0 = fcsr & mask; |
87 | write_32bit_cp1_register(CP1_STATUS, fcsr0); | |
88 | fcsr0 = read_32bit_cp1_register(CP1_STATUS); | |
89 | ||
90 | fcsr1 = fcsr | ~mask; | |
91 | write_32bit_cp1_register(CP1_STATUS, fcsr1); | |
92 | fcsr1 = read_32bit_cp1_register(CP1_STATUS); | |
93 | ||
94 | write_32bit_cp1_register(CP1_STATUS, fcsr); | |
95 | ||
96 | write_c0_status(sr); | |
97 | ||
98 | c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; | |
99 | } | |
100 | ||
93adeaf6 MR |
101 | /* |
102 | * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes | |
103 | * supported by FPU hardware. | |
104 | */ | |
105 | static void cpu_set_fpu_2008(struct cpuinfo_mips *c) | |
106 | { | |
107 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
108 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
109 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { | |
110 | unsigned long sr, fir, fcsr, fcsr0, fcsr1; | |
111 | ||
112 | sr = read_c0_status(); | |
113 | __enable_fpu(FPU_AS_IS); | |
114 | ||
115 | fir = read_32bit_cp1_register(CP1_REVISION); | |
116 | if (fir & MIPS_FPIR_HAS2008) { | |
117 | fcsr = read_32bit_cp1_register(CP1_STATUS); | |
118 | ||
119 | fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); | |
120 | write_32bit_cp1_register(CP1_STATUS, fcsr0); | |
121 | fcsr0 = read_32bit_cp1_register(CP1_STATUS); | |
122 | ||
123 | fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
124 | write_32bit_cp1_register(CP1_STATUS, fcsr1); | |
125 | fcsr1 = read_32bit_cp1_register(CP1_STATUS); | |
126 | ||
127 | write_32bit_cp1_register(CP1_STATUS, fcsr); | |
128 | ||
129 | if (!(fcsr0 & FPU_CSR_NAN2008)) | |
130 | c->options |= MIPS_CPU_NAN_LEGACY; | |
131 | if (fcsr1 & FPU_CSR_NAN2008) | |
132 | c->options |= MIPS_CPU_NAN_2008; | |
133 | ||
134 | if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008) | |
135 | c->fpu_msk31 &= ~FPU_CSR_ABS2008; | |
136 | else | |
137 | c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008; | |
138 | ||
139 | if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008) | |
140 | c->fpu_msk31 &= ~FPU_CSR_NAN2008; | |
141 | else | |
142 | c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008; | |
143 | } else { | |
144 | c->options |= MIPS_CPU_NAN_LEGACY; | |
145 | } | |
146 | ||
147 | write_c0_status(sr); | |
148 | } else { | |
149 | c->options |= MIPS_CPU_NAN_LEGACY; | |
150 | } | |
151 | } | |
152 | ||
153 | /* | |
503943e0 MR |
154 | * IEEE 754 conformance mode to use. Affects the NaN encoding and the |
155 | * ABS.fmt/NEG.fmt execution mode. | |
156 | */ | |
157 | static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT; | |
158 | ||
159 | /* | |
160 | * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes | |
161 | * to support by the FPU emulator according to the IEEE 754 conformance | |
162 | * mode selected. Note that "relaxed" straps the emulator so that it | |
163 | * allows 2008-NaN binaries even for legacy processors. | |
93adeaf6 MR |
164 | */ |
165 | static void cpu_set_nofpu_2008(struct cpuinfo_mips *c) | |
166 | { | |
503943e0 | 167 | c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY); |
93adeaf6 | 168 | c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); |
503943e0 MR |
169 | c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); |
170 | ||
171 | switch (ieee754) { | |
172 | case STRICT: | |
173 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
174 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
175 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { | |
176 | c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; | |
177 | } else { | |
178 | c->options |= MIPS_CPU_NAN_LEGACY; | |
179 | c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
180 | } | |
181 | break; | |
182 | case LEGACY: | |
93adeaf6 MR |
183 | c->options |= MIPS_CPU_NAN_LEGACY; |
184 | c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
503943e0 MR |
185 | break; |
186 | case STD2008: | |
187 | c->options |= MIPS_CPU_NAN_2008; | |
188 | c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
189 | c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
190 | break; | |
191 | case RELAXED: | |
192 | c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; | |
193 | break; | |
93adeaf6 MR |
194 | } |
195 | } | |
196 | ||
503943e0 MR |
197 | /* |
198 | * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode | |
199 | * according to the "ieee754=" parameter. | |
200 | */ | |
201 | static void cpu_set_nan_2008(struct cpuinfo_mips *c) | |
202 | { | |
203 | switch (ieee754) { | |
204 | case STRICT: | |
205 | mips_use_nan_legacy = !!cpu_has_nan_legacy; | |
206 | mips_use_nan_2008 = !!cpu_has_nan_2008; | |
207 | break; | |
208 | case LEGACY: | |
209 | mips_use_nan_legacy = !!cpu_has_nan_legacy; | |
210 | mips_use_nan_2008 = !cpu_has_nan_legacy; | |
211 | break; | |
212 | case STD2008: | |
213 | mips_use_nan_legacy = !cpu_has_nan_2008; | |
214 | mips_use_nan_2008 = !!cpu_has_nan_2008; | |
215 | break; | |
216 | case RELAXED: | |
217 | mips_use_nan_legacy = true; | |
218 | mips_use_nan_2008 = true; | |
219 | break; | |
220 | } | |
221 | } | |
222 | ||
223 | /* | |
224 | * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override | |
225 | * settings: | |
226 | * | |
227 | * strict: accept binaries that request a NaN encoding supported by the FPU | |
228 | * legacy: only accept legacy-NaN binaries | |
229 | * 2008: only accept 2008-NaN binaries | |
230 | * relaxed: accept any binaries regardless of whether supported by the FPU | |
231 | */ | |
232 | static int __init ieee754_setup(char *s) | |
233 | { | |
234 | if (!s) | |
235 | return -1; | |
236 | else if (!strcmp(s, "strict")) | |
237 | ieee754 = STRICT; | |
238 | else if (!strcmp(s, "legacy")) | |
239 | ieee754 = LEGACY; | |
240 | else if (!strcmp(s, "2008")) | |
241 | ieee754 = STD2008; | |
242 | else if (!strcmp(s, "relaxed")) | |
243 | ieee754 = RELAXED; | |
244 | else | |
245 | return -1; | |
246 | ||
247 | if (!(boot_cpu_data.options & MIPS_CPU_FPU)) | |
248 | cpu_set_nofpu_2008(&boot_cpu_data); | |
249 | cpu_set_nan_2008(&boot_cpu_data); | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | early_param("ieee754", ieee754_setup); | |
255 | ||
f6843626 MR |
256 | /* |
257 | * Set the FIR feature flags for the FPU emulator. | |
258 | */ | |
259 | static void cpu_set_nofpu_id(struct cpuinfo_mips *c) | |
260 | { | |
261 | u32 value; | |
262 | ||
263 | value = 0; | |
264 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
265 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
266 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) | |
267 | value |= MIPS_FPIR_D | MIPS_FPIR_S; | |
268 | if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
269 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) | |
270 | value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; | |
90d53a91 MR |
271 | if (c->options & MIPS_CPU_NAN_2008) |
272 | value |= MIPS_FPIR_HAS2008; | |
f6843626 MR |
273 | c->fpu_id = value; |
274 | } | |
275 | ||
9b26616c MR |
276 | /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ |
277 | static unsigned int mips_nofpu_msk31; | |
278 | ||
7aecd5ca MR |
279 | /* |
280 | * Set options for FPU hardware. | |
281 | */ | |
282 | static void cpu_set_fpu_opts(struct cpuinfo_mips *c) | |
283 | { | |
284 | c->fpu_id = cpu_get_fpu_id(); | |
285 | mips_nofpu_msk31 = c->fpu_msk31; | |
286 | ||
287 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
288 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
289 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { | |
290 | if (c->fpu_id & MIPS_FPIR_3D) | |
291 | c->ases |= MIPS_ASE_MIPS3D; | |
292 | if (c->fpu_id & MIPS_FPIR_FREP) | |
293 | c->options |= MIPS_CPU_FRE; | |
294 | } | |
295 | ||
296 | cpu_set_fpu_fcsr_mask(c); | |
93adeaf6 | 297 | cpu_set_fpu_2008(c); |
503943e0 | 298 | cpu_set_nan_2008(c); |
7aecd5ca MR |
299 | } |
300 | ||
301 | /* | |
302 | * Set options for the FPU emulator. | |
303 | */ | |
304 | static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) | |
305 | { | |
306 | c->options &= ~MIPS_CPU_FPU; | |
307 | c->fpu_msk31 = mips_nofpu_msk31; | |
308 | ||
93adeaf6 | 309 | cpu_set_nofpu_2008(c); |
503943e0 | 310 | cpu_set_nan_2008(c); |
7aecd5ca MR |
311 | cpu_set_nofpu_id(c); |
312 | } | |
313 | ||
078a55fc | 314 | static int mips_fpu_disabled; |
0103d23f KC |
315 | |
316 | static int __init fpu_disable(char *s) | |
317 | { | |
7aecd5ca | 318 | cpu_set_nofpu_opts(&boot_cpu_data); |
0103d23f KC |
319 | mips_fpu_disabled = 1; |
320 | ||
321 | return 1; | |
322 | } | |
323 | ||
324 | __setup("nofpu", fpu_disable); | |
325 | ||
078a55fc | 326 | int mips_dsp_disabled; |
0103d23f KC |
327 | |
328 | static int __init dsp_disable(char *s) | |
329 | { | |
ee80f7c7 | 330 | cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
0103d23f KC |
331 | mips_dsp_disabled = 1; |
332 | ||
333 | return 1; | |
334 | } | |
335 | ||
336 | __setup("nodsp", dsp_disable); | |
337 | ||
3d528b32 MC |
338 | static int mips_htw_disabled; |
339 | ||
340 | static int __init htw_disable(char *s) | |
341 | { | |
342 | mips_htw_disabled = 1; | |
343 | cpu_data[0].options &= ~MIPS_CPU_HTW; | |
344 | write_c0_pwctl(read_c0_pwctl() & | |
345 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); | |
346 | ||
347 | return 1; | |
348 | } | |
349 | ||
350 | __setup("nohtw", htw_disable); | |
351 | ||
97f4ad29 MC |
352 | static int mips_ftlb_disabled; |
353 | static int mips_has_ftlb_configured; | |
354 | ||
912708c2 | 355 | static int set_ftlb_enable(struct cpuinfo_mips *c, int enable); |
97f4ad29 MC |
356 | |
357 | static int __init ftlb_disable(char *s) | |
358 | { | |
359 | unsigned int config4, mmuextdef; | |
360 | ||
361 | /* | |
362 | * If the core hasn't done any FTLB configuration, there is nothing | |
363 | * for us to do here. | |
364 | */ | |
365 | if (!mips_has_ftlb_configured) | |
366 | return 1; | |
367 | ||
368 | /* Disable it in the boot cpu */ | |
912708c2 MC |
369 | if (set_ftlb_enable(&cpu_data[0], 0)) { |
370 | pr_warn("Can't turn FTLB off\n"); | |
371 | return 1; | |
372 | } | |
97f4ad29 MC |
373 | |
374 | back_to_back_c0_hazard(); | |
375 | ||
376 | config4 = read_c0_config4(); | |
377 | ||
378 | /* Check that FTLB has been disabled */ | |
379 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; | |
380 | /* MMUSIZEEXT == VTLB ON, FTLB OFF */ | |
381 | if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { | |
382 | /* This should never happen */ | |
383 | pr_warn("FTLB could not be disabled!\n"); | |
384 | return 1; | |
385 | } | |
386 | ||
387 | mips_ftlb_disabled = 1; | |
388 | mips_has_ftlb_configured = 0; | |
389 | ||
390 | /* | |
391 | * noftlb is mainly used for debug purposes so print | |
392 | * an informative message instead of using pr_debug() | |
393 | */ | |
394 | pr_info("FTLB has been disabled\n"); | |
395 | ||
396 | /* | |
397 | * Some of these bits are duplicated in the decode_config4. | |
398 | * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case | |
399 | * once FTLB has been disabled so undo what decode_config4 did. | |
400 | */ | |
401 | cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * | |
402 | cpu_data[0].tlbsizeftlbsets; | |
403 | cpu_data[0].tlbsizeftlbsets = 0; | |
404 | cpu_data[0].tlbsizeftlbways = 0; | |
405 | ||
406 | return 1; | |
407 | } | |
408 | ||
409 | __setup("noftlb", ftlb_disable); | |
410 | ||
411 | ||
9267a30d MSJ |
412 | static inline void check_errata(void) |
413 | { | |
414 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
415 | ||
69f24d17 | 416 | switch (current_cpu_type()) { |
9267a30d MSJ |
417 | case CPU_34K: |
418 | /* | |
419 | * Erratum "RPS May Cause Incorrect Instruction Execution" | |
b633648c | 420 | * This code only handles VPE0, any SMP/RTOS code |
9267a30d MSJ |
421 | * making use of VPE1 will be responsable for that VPE. |
422 | */ | |
423 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) | |
424 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); | |
425 | break; | |
426 | default: | |
427 | break; | |
428 | } | |
429 | } | |
430 | ||
1da177e4 LT |
431 | void __init check_bugs32(void) |
432 | { | |
9267a30d | 433 | check_errata(); |
1da177e4 LT |
434 | } |
435 | ||
436 | /* | |
437 | * Probe whether cpu has config register by trying to play with | |
438 | * alternate cache bit and see whether it matters. | |
439 | * It's used by cpu_probe to distinguish between R3000A and R3081. | |
440 | */ | |
441 | static inline int cpu_has_confreg(void) | |
442 | { | |
443 | #ifdef CONFIG_CPU_R3000 | |
444 | extern unsigned long r3k_cache_size(unsigned long); | |
445 | unsigned long size1, size2; | |
446 | unsigned long cfg = read_c0_conf(); | |
447 | ||
448 | size1 = r3k_cache_size(ST0_ISC); | |
449 | write_c0_conf(cfg ^ R30XX_CONF_AC); | |
450 | size2 = r3k_cache_size(ST0_ISC); | |
451 | write_c0_conf(cfg); | |
452 | return size1 != size2; | |
453 | #else | |
454 | return 0; | |
455 | #endif | |
456 | } | |
457 | ||
c094c99e RM |
458 | static inline void set_elf_platform(int cpu, const char *plat) |
459 | { | |
460 | if (cpu == 0) | |
461 | __elf_platform = plat; | |
462 | } | |
463 | ||
91dfc423 GR |
464 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) |
465 | { | |
466 | #ifdef __NEED_VMBITS_PROBE | |
5b7efa89 | 467 | write_c0_entryhi(0x3fffffffffffe000ULL); |
91dfc423 | 468 | back_to_back_c0_hazard(); |
5b7efa89 | 469 | c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); |
91dfc423 GR |
470 | #endif |
471 | } | |
472 | ||
078a55fc | 473 | static void set_isa(struct cpuinfo_mips *c, unsigned int isa) |
a96102be SH |
474 | { |
475 | switch (isa) { | |
476 | case MIPS_CPU_ISA_M64R2: | |
477 | c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; | |
478 | case MIPS_CPU_ISA_M64R1: | |
479 | c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; | |
480 | case MIPS_CPU_ISA_V: | |
481 | c->isa_level |= MIPS_CPU_ISA_V; | |
482 | case MIPS_CPU_ISA_IV: | |
483 | c->isa_level |= MIPS_CPU_ISA_IV; | |
484 | case MIPS_CPU_ISA_III: | |
1990e542 | 485 | c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; |
a96102be SH |
486 | break; |
487 | ||
8b8aa636 LY |
488 | /* R6 incompatible with everything else */ |
489 | case MIPS_CPU_ISA_M64R6: | |
490 | c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; | |
491 | case MIPS_CPU_ISA_M32R6: | |
492 | c->isa_level |= MIPS_CPU_ISA_M32R6; | |
493 | /* Break here so we don't add incompatible ISAs */ | |
494 | break; | |
a96102be SH |
495 | case MIPS_CPU_ISA_M32R2: |
496 | c->isa_level |= MIPS_CPU_ISA_M32R2; | |
497 | case MIPS_CPU_ISA_M32R1: | |
498 | c->isa_level |= MIPS_CPU_ISA_M32R1; | |
499 | case MIPS_CPU_ISA_II: | |
500 | c->isa_level |= MIPS_CPU_ISA_II; | |
a96102be SH |
501 | break; |
502 | } | |
503 | } | |
504 | ||
078a55fc | 505 | static char unknown_isa[] = KERN_ERR \ |
2fa36399 KC |
506 | "Unsupported ISA type, c0.config0: %d."; |
507 | ||
cf0a8aa0 MC |
508 | static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) |
509 | { | |
510 | ||
511 | unsigned int probability = c->tlbsize / c->tlbsizevtlb; | |
512 | ||
513 | /* | |
514 | * 0 = All TLBWR instructions go to FTLB | |
515 | * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the | |
516 | * FTLB and 1 goes to the VTLB. | |
517 | * 2 = 7:1: As above with 7:1 ratio. | |
518 | * 3 = 3:1: As above with 3:1 ratio. | |
519 | * | |
520 | * Use the linear midpoint as the probability threshold. | |
521 | */ | |
522 | if (probability >= 12) | |
523 | return 1; | |
524 | else if (probability >= 6) | |
525 | return 2; | |
526 | else | |
527 | /* | |
528 | * So FTLB is less than 4 times bigger than VTLB. | |
529 | * A 3:1 ratio can still be useful though. | |
530 | */ | |
531 | return 3; | |
532 | } | |
533 | ||
912708c2 | 534 | static int set_ftlb_enable(struct cpuinfo_mips *c, int enable) |
75b5b5e0 | 535 | { |
20a7f7e5 | 536 | unsigned int config; |
d83b0e82 JH |
537 | |
538 | /* It's implementation dependent how the FTLB can be enabled */ | |
539 | switch (c->cputype) { | |
540 | case CPU_PROAPTIV: | |
541 | case CPU_P5600: | |
1091bfa2 | 542 | case CPU_P6600: |
d83b0e82 | 543 | /* proAptiv & related cores use Config6 to enable the FTLB */ |
20a7f7e5 | 544 | config = read_c0_config6(); |
cf0a8aa0 | 545 | /* Clear the old probability value */ |
20a7f7e5 | 546 | config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); |
75b5b5e0 LY |
547 | if (enable) |
548 | /* Enable FTLB */ | |
20a7f7e5 | 549 | write_c0_config6(config | |
cf0a8aa0 MC |
550 | (calculate_ftlb_probability(c) |
551 | << MIPS_CONF6_FTLBP_SHIFT) | |
552 | | MIPS_CONF6_FTLBEN); | |
75b5b5e0 LY |
553 | else |
554 | /* Disable FTLB */ | |
20a7f7e5 MC |
555 | write_c0_config6(config & ~MIPS_CONF6_FTLBEN); |
556 | break; | |
557 | case CPU_I6400: | |
558 | /* I6400 & related cores use Config7 to configure FTLB */ | |
559 | config = read_c0_config7(); | |
560 | /* Clear the old probability value */ | |
561 | config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT); | |
562 | write_c0_config7(config | (calculate_ftlb_probability(c) | |
563 | << MIPS_CONF7_FTLBP_SHIFT)); | |
d83b0e82 | 564 | break; |
b2edcfc8 | 565 | case CPU_LOONGSON3: |
06e4814e HC |
566 | /* Flush ITLB, DTLB, VTLB and FTLB */ |
567 | write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | | |
568 | LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); | |
b2edcfc8 HC |
569 | /* Loongson-3 cores use Config6 to enable the FTLB */ |
570 | config = read_c0_config6(); | |
571 | if (enable) | |
572 | /* Enable FTLB */ | |
573 | write_c0_config6(config & ~MIPS_CONF6_FTLBDIS); | |
574 | else | |
575 | /* Disable FTLB */ | |
576 | write_c0_config6(config | MIPS_CONF6_FTLBDIS); | |
577 | break; | |
912708c2 MC |
578 | default: |
579 | return 1; | |
75b5b5e0 | 580 | } |
912708c2 MC |
581 | |
582 | return 0; | |
75b5b5e0 LY |
583 | } |
584 | ||
2fa36399 KC |
585 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
586 | { | |
587 | unsigned int config0; | |
2f6f3136 | 588 | int isa, mt; |
2fa36399 KC |
589 | |
590 | config0 = read_c0_config(); | |
591 | ||
75b5b5e0 LY |
592 | /* |
593 | * Look for Standard TLB or Dual VTLB and FTLB | |
594 | */ | |
2f6f3136 JH |
595 | mt = config0 & MIPS_CONF_MT; |
596 | if (mt == MIPS_CONF_MT_TLB) | |
2fa36399 | 597 | c->options |= MIPS_CPU_TLB; |
2f6f3136 JH |
598 | else if (mt == MIPS_CONF_MT_FTLB) |
599 | c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; | |
75b5b5e0 | 600 | |
2fa36399 KC |
601 | isa = (config0 & MIPS_CONF_AT) >> 13; |
602 | switch (isa) { | |
603 | case 0: | |
604 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
605 | case 0: | |
a96102be | 606 | set_isa(c, MIPS_CPU_ISA_M32R1); |
2fa36399 KC |
607 | break; |
608 | case 1: | |
a96102be | 609 | set_isa(c, MIPS_CPU_ISA_M32R2); |
2fa36399 | 610 | break; |
8b8aa636 LY |
611 | case 2: |
612 | set_isa(c, MIPS_CPU_ISA_M32R6); | |
613 | break; | |
2fa36399 KC |
614 | default: |
615 | goto unknown; | |
616 | } | |
617 | break; | |
618 | case 2: | |
619 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
620 | case 0: | |
a96102be | 621 | set_isa(c, MIPS_CPU_ISA_M64R1); |
2fa36399 KC |
622 | break; |
623 | case 1: | |
a96102be | 624 | set_isa(c, MIPS_CPU_ISA_M64R2); |
2fa36399 | 625 | break; |
8b8aa636 LY |
626 | case 2: |
627 | set_isa(c, MIPS_CPU_ISA_M64R6); | |
628 | break; | |
2fa36399 KC |
629 | default: |
630 | goto unknown; | |
631 | } | |
632 | break; | |
633 | default: | |
634 | goto unknown; | |
635 | } | |
636 | ||
637 | return config0 & MIPS_CONF_M; | |
638 | ||
639 | unknown: | |
640 | panic(unknown_isa, config0); | |
641 | } | |
642 | ||
643 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) | |
644 | { | |
645 | unsigned int config1; | |
646 | ||
647 | config1 = read_c0_config1(); | |
648 | ||
649 | if (config1 & MIPS_CONF1_MD) | |
650 | c->ases |= MIPS_ASE_MDMX; | |
30228c40 JH |
651 | if (config1 & MIPS_CONF1_PC) |
652 | c->options |= MIPS_CPU_PERF; | |
2fa36399 KC |
653 | if (config1 & MIPS_CONF1_WR) |
654 | c->options |= MIPS_CPU_WATCH; | |
655 | if (config1 & MIPS_CONF1_CA) | |
656 | c->ases |= MIPS_ASE_MIPS16; | |
657 | if (config1 & MIPS_CONF1_EP) | |
658 | c->options |= MIPS_CPU_EJTAG; | |
659 | if (config1 & MIPS_CONF1_FP) { | |
660 | c->options |= MIPS_CPU_FPU; | |
661 | c->options |= MIPS_CPU_32FPR; | |
662 | } | |
75b5b5e0 | 663 | if (cpu_has_tlb) { |
2fa36399 | 664 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; |
75b5b5e0 LY |
665 | c->tlbsizevtlb = c->tlbsize; |
666 | c->tlbsizeftlbsets = 0; | |
667 | } | |
2fa36399 KC |
668 | |
669 | return config1 & MIPS_CONF_M; | |
670 | } | |
671 | ||
672 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) | |
673 | { | |
674 | unsigned int config2; | |
675 | ||
676 | config2 = read_c0_config2(); | |
677 | ||
678 | if (config2 & MIPS_CONF2_SL) | |
679 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | |
680 | ||
681 | return config2 & MIPS_CONF_M; | |
682 | } | |
683 | ||
684 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) | |
685 | { | |
686 | unsigned int config3; | |
687 | ||
688 | config3 = read_c0_config3(); | |
689 | ||
b2ab4f08 | 690 | if (config3 & MIPS_CONF3_SM) { |
2fa36399 | 691 | c->ases |= MIPS_ASE_SMARTMIPS; |
f18bdfa1 | 692 | c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; |
b2ab4f08 SH |
693 | } |
694 | if (config3 & MIPS_CONF3_RXI) | |
695 | c->options |= MIPS_CPU_RIXI; | |
f18bdfa1 JH |
696 | if (config3 & MIPS_CONF3_CTXTC) |
697 | c->options |= MIPS_CPU_CTXTC; | |
2fa36399 KC |
698 | if (config3 & MIPS_CONF3_DSP) |
699 | c->ases |= MIPS_ASE_DSP; | |
b5a6455c | 700 | if (config3 & MIPS_CONF3_DSP2P) { |
ee80f7c7 | 701 | c->ases |= MIPS_ASE_DSP2P; |
b5a6455c ZLK |
702 | if (cpu_has_mips_r6) |
703 | c->ases |= MIPS_ASE_DSP3; | |
704 | } | |
2fa36399 KC |
705 | if (config3 & MIPS_CONF3_VINT) |
706 | c->options |= MIPS_CPU_VINT; | |
707 | if (config3 & MIPS_CONF3_VEIC) | |
708 | c->options |= MIPS_CPU_VEIC; | |
12822570 JH |
709 | if (config3 & MIPS_CONF3_LPA) |
710 | c->options |= MIPS_CPU_LPA; | |
2fa36399 KC |
711 | if (config3 & MIPS_CONF3_MT) |
712 | c->ases |= MIPS_ASE_MIPSMT; | |
713 | if (config3 & MIPS_CONF3_ULRI) | |
714 | c->options |= MIPS_CPU_ULRI; | |
f8fa4811 SH |
715 | if (config3 & MIPS_CONF3_ISA) |
716 | c->options |= MIPS_CPU_MICROMIPS; | |
1e7decdb DD |
717 | if (config3 & MIPS_CONF3_VZ) |
718 | c->ases |= MIPS_ASE_VZ; | |
4a0156fb SH |
719 | if (config3 & MIPS_CONF3_SC) |
720 | c->options |= MIPS_CPU_SEGMENTS; | |
e06a1548 JH |
721 | if (config3 & MIPS_CONF3_BI) |
722 | c->options |= MIPS_CPU_BADINSTR; | |
723 | if (config3 & MIPS_CONF3_BP) | |
724 | c->options |= MIPS_CPU_BADINSTRP; | |
a5e9a69e PB |
725 | if (config3 & MIPS_CONF3_MSA) |
726 | c->ases |= MIPS_ASE_MSA; | |
cab25bc7 | 727 | if (config3 & MIPS_CONF3_PW) { |
ed4cbc81 | 728 | c->htw_seq = 0; |
3d528b32 | 729 | c->options |= MIPS_CPU_HTW; |
ed4cbc81 | 730 | } |
9b3274bd JH |
731 | if (config3 & MIPS_CONF3_CDMM) |
732 | c->options |= MIPS_CPU_CDMM; | |
aaa7be48 JH |
733 | if (config3 & MIPS_CONF3_SP) |
734 | c->options |= MIPS_CPU_SP; | |
2fa36399 KC |
735 | |
736 | return config3 & MIPS_CONF_M; | |
737 | } | |
738 | ||
739 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) | |
740 | { | |
741 | unsigned int config4; | |
75b5b5e0 LY |
742 | unsigned int newcf4; |
743 | unsigned int mmuextdef; | |
744 | unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; | |
2db003a5 | 745 | unsigned long asid_mask; |
2fa36399 KC |
746 | |
747 | config4 = read_c0_config4(); | |
748 | ||
1745c1ef LY |
749 | if (cpu_has_tlb) { |
750 | if (((config4 & MIPS_CONF4_IE) >> 29) == 2) | |
751 | c->options |= MIPS_CPU_TLBINV; | |
43d104db | 752 | |
e87569cd | 753 | /* |
43d104db JH |
754 | * R6 has dropped the MMUExtDef field from config4. |
755 | * On R6 the fields always describe the FTLB, and only if it is | |
756 | * present according to Config.MT. | |
e87569cd | 757 | */ |
43d104db JH |
758 | if (!cpu_has_mips_r6) |
759 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; | |
760 | else if (cpu_has_ftlb) | |
e87569cd MC |
761 | mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; |
762 | else | |
43d104db | 763 | mmuextdef = 0; |
e87569cd | 764 | |
75b5b5e0 LY |
765 | switch (mmuextdef) { |
766 | case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: | |
767 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; | |
768 | c->tlbsizevtlb = c->tlbsize; | |
769 | break; | |
770 | case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: | |
771 | c->tlbsizevtlb += | |
772 | ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> | |
773 | MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; | |
774 | c->tlbsize = c->tlbsizevtlb; | |
775 | ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; | |
776 | /* fall through */ | |
777 | case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: | |
97f4ad29 MC |
778 | if (mips_ftlb_disabled) |
779 | break; | |
75b5b5e0 LY |
780 | newcf4 = (config4 & ~ftlb_page) | |
781 | (page_size_ftlb(mmuextdef) << | |
782 | MIPS_CONF4_FTLBPAGESIZE_SHIFT); | |
783 | write_c0_config4(newcf4); | |
784 | back_to_back_c0_hazard(); | |
785 | config4 = read_c0_config4(); | |
786 | if (config4 != newcf4) { | |
787 | pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", | |
788 | PAGE_SIZE, config4); | |
789 | /* Switch FTLB off */ | |
790 | set_ftlb_enable(c, 0); | |
791 | break; | |
792 | } | |
793 | c->tlbsizeftlbsets = 1 << | |
794 | ((config4 & MIPS_CONF4_FTLBSETS) >> | |
795 | MIPS_CONF4_FTLBSETS_SHIFT); | |
796 | c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> | |
797 | MIPS_CONF4_FTLBWAYS_SHIFT) + 2; | |
798 | c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; | |
97f4ad29 | 799 | mips_has_ftlb_configured = 1; |
75b5b5e0 LY |
800 | break; |
801 | } | |
1745c1ef LY |
802 | } |
803 | ||
9e575f75 JH |
804 | c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) |
805 | >> MIPS_CONF4_KSCREXIST_SHIFT; | |
2fa36399 | 806 | |
2db003a5 PB |
807 | asid_mask = MIPS_ENTRYHI_ASID; |
808 | if (config4 & MIPS_CONF4_AE) | |
809 | asid_mask |= MIPS_ENTRYHI_ASIDX; | |
810 | set_cpu_asid_mask(c, asid_mask); | |
811 | ||
812 | /* | |
813 | * Warn if the computed ASID mask doesn't match the mask the kernel | |
814 | * is built for. This may indicate either a serious problem or an | |
815 | * easy optimisation opportunity, but either way should be addressed. | |
816 | */ | |
817 | WARN_ON(asid_mask != cpu_asid_mask(c)); | |
818 | ||
2fa36399 KC |
819 | return config4 & MIPS_CONF_M; |
820 | } | |
821 | ||
8b8a7634 RB |
822 | static inline unsigned int decode_config5(struct cpuinfo_mips *c) |
823 | { | |
824 | unsigned int config5; | |
825 | ||
826 | config5 = read_c0_config5(); | |
d175ed2b | 827 | config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); |
8b8a7634 RB |
828 | write_c0_config5(config5); |
829 | ||
49016748 MC |
830 | if (config5 & MIPS_CONF5_EVA) |
831 | c->options |= MIPS_CPU_EVA; | |
1f6c52ff PB |
832 | if (config5 & MIPS_CONF5_MRP) |
833 | c->options |= MIPS_CPU_MAAR; | |
5aed9da1 MC |
834 | if (config5 & MIPS_CONF5_LLB) |
835 | c->options |= MIPS_CPU_RW_LLB; | |
c5b36783 SH |
836 | #ifdef CONFIG_XPA |
837 | if (config5 & MIPS_CONF5_MVH) | |
838 | c->options |= MIPS_CPU_XPA; | |
839 | #endif | |
f270d881 PB |
840 | if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) |
841 | c->options |= MIPS_CPU_VP; | |
49016748 | 842 | |
8b8a7634 RB |
843 | return config5 & MIPS_CONF_M; |
844 | } | |
845 | ||
078a55fc | 846 | static void decode_configs(struct cpuinfo_mips *c) |
2fa36399 KC |
847 | { |
848 | int ok; | |
849 | ||
850 | /* MIPS32 or MIPS64 compliant CPU. */ | |
851 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | | |
852 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; | |
853 | ||
854 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; | |
855 | ||
97f4ad29 MC |
856 | /* Enable FTLB if present and not disabled */ |
857 | set_ftlb_enable(c, !mips_ftlb_disabled); | |
75b5b5e0 | 858 | |
2fa36399 | 859 | ok = decode_config0(c); /* Read Config registers. */ |
70342287 | 860 | BUG_ON(!ok); /* Arch spec violation! */ |
2fa36399 KC |
861 | if (ok) |
862 | ok = decode_config1(c); | |
863 | if (ok) | |
864 | ok = decode_config2(c); | |
865 | if (ok) | |
866 | ok = decode_config3(c); | |
867 | if (ok) | |
868 | ok = decode_config4(c); | |
8b8a7634 RB |
869 | if (ok) |
870 | ok = decode_config5(c); | |
2fa36399 | 871 | |
37fb60f8 JH |
872 | /* Probe the EBase.WG bit */ |
873 | if (cpu_has_mips_r2_r6) { | |
874 | u64 ebase; | |
875 | unsigned int status; | |
876 | ||
877 | /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ | |
878 | ebase = cpu_has_mips64r6 ? read_c0_ebase_64() | |
879 | : (s32)read_c0_ebase(); | |
880 | if (ebase & MIPS_EBASE_WG) { | |
881 | /* WG bit already set, we can avoid the clumsy probe */ | |
882 | c->options |= MIPS_CPU_EBASE_WG; | |
883 | } else { | |
884 | /* Its UNDEFINED to change EBase while BEV=0 */ | |
885 | status = read_c0_status(); | |
886 | write_c0_status(status | ST0_BEV); | |
887 | irq_enable_hazard(); | |
888 | /* | |
889 | * On pre-r6 cores, this may well clobber the upper bits | |
890 | * of EBase. This is hard to avoid without potentially | |
891 | * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. | |
892 | */ | |
893 | if (cpu_has_mips64r6) | |
894 | write_c0_ebase_64(ebase | MIPS_EBASE_WG); | |
895 | else | |
896 | write_c0_ebase(ebase | MIPS_EBASE_WG); | |
897 | back_to_back_c0_hazard(); | |
898 | /* Restore BEV */ | |
899 | write_c0_status(status); | |
900 | if (read_c0_ebase() & MIPS_EBASE_WG) { | |
901 | c->options |= MIPS_CPU_EBASE_WG; | |
902 | write_c0_ebase(ebase); | |
903 | } | |
904 | } | |
905 | } | |
906 | ||
2fa36399 KC |
907 | mips_probe_watch_registers(c); |
908 | ||
0ee958e1 | 909 | #ifndef CONFIG_MIPS_CPS |
8b8aa636 | 910 | if (cpu_has_mips_r2_r6) { |
45b585c8 | 911 | c->core = get_ebase_cpunum(); |
30ee615b PB |
912 | if (cpu_has_mipsmt) |
913 | c->core >>= fls(core_nvpes()) - 1; | |
914 | } | |
0ee958e1 | 915 | #endif |
2fa36399 KC |
916 | } |
917 | ||
6ad816e7 JH |
918 | /* |
919 | * Probe for certain guest capabilities by writing config bits and reading back. | |
920 | * Finally write back the original value. | |
921 | */ | |
922 | #define probe_gc0_config(name, maxconf, bits) \ | |
923 | do { \ | |
924 | unsigned int tmp; \ | |
925 | tmp = read_gc0_##name(); \ | |
926 | write_gc0_##name(tmp | (bits)); \ | |
927 | back_to_back_c0_hazard(); \ | |
928 | maxconf = read_gc0_##name(); \ | |
929 | write_gc0_##name(tmp); \ | |
930 | } while (0) | |
931 | ||
932 | /* | |
933 | * Probe for dynamic guest capabilities by changing certain config bits and | |
934 | * reading back to see if they change. Finally write back the original value. | |
935 | */ | |
936 | #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ | |
937 | do { \ | |
938 | maxconf = read_gc0_##name(); \ | |
939 | write_gc0_##name(maxconf ^ (bits)); \ | |
940 | back_to_back_c0_hazard(); \ | |
941 | dynconf = maxconf ^ read_gc0_##name(); \ | |
942 | write_gc0_##name(maxconf); \ | |
943 | maxconf |= dynconf; \ | |
944 | } while (0) | |
945 | ||
946 | static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) | |
947 | { | |
948 | unsigned int config0; | |
949 | ||
950 | probe_gc0_config(config, config0, MIPS_CONF_M); | |
951 | ||
952 | if (config0 & MIPS_CONF_M) | |
953 | c->guest.conf |= BIT(1); | |
954 | return config0 & MIPS_CONF_M; | |
955 | } | |
956 | ||
957 | static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) | |
958 | { | |
959 | unsigned int config1, config1_dyn; | |
960 | ||
961 | probe_gc0_config_dyn(config1, config1, config1_dyn, | |
962 | MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | | |
963 | MIPS_CONF1_FP); | |
964 | ||
965 | if (config1 & MIPS_CONF1_FP) | |
966 | c->guest.options |= MIPS_CPU_FPU; | |
967 | if (config1_dyn & MIPS_CONF1_FP) | |
968 | c->guest.options_dyn |= MIPS_CPU_FPU; | |
969 | ||
970 | if (config1 & MIPS_CONF1_WR) | |
971 | c->guest.options |= MIPS_CPU_WATCH; | |
972 | if (config1_dyn & MIPS_CONF1_WR) | |
973 | c->guest.options_dyn |= MIPS_CPU_WATCH; | |
974 | ||
975 | if (config1 & MIPS_CONF1_PC) | |
976 | c->guest.options |= MIPS_CPU_PERF; | |
977 | if (config1_dyn & MIPS_CONF1_PC) | |
978 | c->guest.options_dyn |= MIPS_CPU_PERF; | |
979 | ||
980 | if (config1 & MIPS_CONF_M) | |
981 | c->guest.conf |= BIT(2); | |
982 | return config1 & MIPS_CONF_M; | |
983 | } | |
984 | ||
985 | static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) | |
986 | { | |
987 | unsigned int config2; | |
988 | ||
989 | probe_gc0_config(config2, config2, MIPS_CONF_M); | |
990 | ||
991 | if (config2 & MIPS_CONF_M) | |
992 | c->guest.conf |= BIT(3); | |
993 | return config2 & MIPS_CONF_M; | |
994 | } | |
995 | ||
996 | static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) | |
997 | { | |
998 | unsigned int config3, config3_dyn; | |
999 | ||
1000 | probe_gc0_config_dyn(config3, config3, config3_dyn, | |
1001 | MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_CTXTC); | |
1002 | ||
1003 | if (config3 & MIPS_CONF3_CTXTC) | |
1004 | c->guest.options |= MIPS_CPU_CTXTC; | |
1005 | if (config3_dyn & MIPS_CONF3_CTXTC) | |
1006 | c->guest.options_dyn |= MIPS_CPU_CTXTC; | |
1007 | ||
1008 | if (config3 & MIPS_CONF3_PW) | |
1009 | c->guest.options |= MIPS_CPU_HTW; | |
1010 | ||
1011 | if (config3 & MIPS_CONF3_SC) | |
1012 | c->guest.options |= MIPS_CPU_SEGMENTS; | |
1013 | ||
1014 | if (config3 & MIPS_CONF3_BI) | |
1015 | c->guest.options |= MIPS_CPU_BADINSTR; | |
1016 | if (config3 & MIPS_CONF3_BP) | |
1017 | c->guest.options |= MIPS_CPU_BADINSTRP; | |
1018 | ||
1019 | if (config3 & MIPS_CONF3_MSA) | |
1020 | c->guest.ases |= MIPS_ASE_MSA; | |
1021 | if (config3_dyn & MIPS_CONF3_MSA) | |
1022 | c->guest.ases_dyn |= MIPS_ASE_MSA; | |
1023 | ||
1024 | if (config3 & MIPS_CONF_M) | |
1025 | c->guest.conf |= BIT(4); | |
1026 | return config3 & MIPS_CONF_M; | |
1027 | } | |
1028 | ||
1029 | static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) | |
1030 | { | |
1031 | unsigned int config4; | |
1032 | ||
1033 | probe_gc0_config(config4, config4, | |
1034 | MIPS_CONF_M | MIPS_CONF4_KSCREXIST); | |
1035 | ||
1036 | c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) | |
1037 | >> MIPS_CONF4_KSCREXIST_SHIFT; | |
1038 | ||
1039 | if (config4 & MIPS_CONF_M) | |
1040 | c->guest.conf |= BIT(5); | |
1041 | return config4 & MIPS_CONF_M; | |
1042 | } | |
1043 | ||
1044 | static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) | |
1045 | { | |
1046 | unsigned int config5, config5_dyn; | |
1047 | ||
1048 | probe_gc0_config_dyn(config5, config5, config5_dyn, | |
1049 | MIPS_CONF_M | MIPS_CONF5_MRP); | |
1050 | ||
1051 | if (config5 & MIPS_CONF5_MRP) | |
1052 | c->guest.options |= MIPS_CPU_MAAR; | |
1053 | if (config5_dyn & MIPS_CONF5_MRP) | |
1054 | c->guest.options_dyn |= MIPS_CPU_MAAR; | |
1055 | ||
1056 | if (config5 & MIPS_CONF5_LLB) | |
1057 | c->guest.options |= MIPS_CPU_RW_LLB; | |
1058 | ||
1059 | if (config5 & MIPS_CONF_M) | |
1060 | c->guest.conf |= BIT(6); | |
1061 | return config5 & MIPS_CONF_M; | |
1062 | } | |
1063 | ||
1064 | static inline void decode_guest_configs(struct cpuinfo_mips *c) | |
1065 | { | |
1066 | unsigned int ok; | |
1067 | ||
1068 | ok = decode_guest_config0(c); | |
1069 | if (ok) | |
1070 | ok = decode_guest_config1(c); | |
1071 | if (ok) | |
1072 | ok = decode_guest_config2(c); | |
1073 | if (ok) | |
1074 | ok = decode_guest_config3(c); | |
1075 | if (ok) | |
1076 | ok = decode_guest_config4(c); | |
1077 | if (ok) | |
1078 | decode_guest_config5(c); | |
1079 | } | |
1080 | ||
1081 | static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) | |
1082 | { | |
1083 | unsigned int guestctl0, temp; | |
1084 | ||
1085 | guestctl0 = read_c0_guestctl0(); | |
1086 | ||
1087 | if (guestctl0 & MIPS_GCTL0_G0E) | |
1088 | c->options |= MIPS_CPU_GUESTCTL0EXT; | |
1089 | if (guestctl0 & MIPS_GCTL0_G1) | |
1090 | c->options |= MIPS_CPU_GUESTCTL1; | |
1091 | if (guestctl0 & MIPS_GCTL0_G2) | |
1092 | c->options |= MIPS_CPU_GUESTCTL2; | |
1093 | if (!(guestctl0 & MIPS_GCTL0_RAD)) { | |
1094 | c->options |= MIPS_CPU_GUESTID; | |
1095 | ||
1096 | /* | |
1097 | * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 | |
1098 | * first, otherwise all data accesses will be fully virtualised | |
1099 | * as if they were performed by guest mode. | |
1100 | */ | |
1101 | write_c0_guestctl1(0); | |
1102 | tlbw_use_hazard(); | |
1103 | ||
1104 | write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); | |
1105 | back_to_back_c0_hazard(); | |
1106 | temp = read_c0_guestctl0(); | |
1107 | ||
1108 | if (temp & MIPS_GCTL0_DRG) { | |
1109 | write_c0_guestctl0(guestctl0); | |
1110 | c->options |= MIPS_CPU_DRG; | |
1111 | } | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) | |
1116 | { | |
1117 | if (cpu_has_guestid) { | |
1118 | /* determine the number of bits of GuestID available */ | |
1119 | write_c0_guestctl1(MIPS_GCTL1_ID); | |
1120 | back_to_back_c0_hazard(); | |
1121 | c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) | |
1122 | >> MIPS_GCTL1_ID_SHIFT; | |
1123 | write_c0_guestctl1(0); | |
1124 | } | |
1125 | } | |
1126 | ||
1127 | static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) | |
1128 | { | |
1129 | /* determine the number of bits of GTOffset available */ | |
1130 | write_c0_gtoffset(0xffffffff); | |
1131 | back_to_back_c0_hazard(); | |
1132 | c->gtoffset_mask = read_c0_gtoffset(); | |
1133 | write_c0_gtoffset(0); | |
1134 | } | |
1135 | ||
1136 | static inline void cpu_probe_vz(struct cpuinfo_mips *c) | |
1137 | { | |
1138 | cpu_probe_guestctl0(c); | |
1139 | if (cpu_has_guestctl1) | |
1140 | cpu_probe_guestctl1(c); | |
1141 | ||
1142 | cpu_probe_gtoffset(c); | |
1143 | ||
1144 | decode_guest_configs(c); | |
1145 | } | |
1146 | ||
02cf2119 | 1147 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
1da177e4 LT |
1148 | | MIPS_CPU_COUNTER) |
1149 | ||
cea7e2df | 1150 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1151 | { |
8ff374b9 | 1152 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1153 | case PRID_IMP_R2000: |
1154 | c->cputype = CPU_R2000; | |
cea7e2df | 1155 | __cpu_name[cpu] = "R2000"; |
9b26616c | 1156 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
02cf2119 | 1157 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
03751e79 | 1158 | MIPS_CPU_NOFPUEX; |
1da177e4 LT |
1159 | if (__cpu_has_fpu()) |
1160 | c->options |= MIPS_CPU_FPU; | |
1161 | c->tlbsize = 64; | |
1162 | break; | |
1163 | case PRID_IMP_R3000: | |
8ff374b9 | 1164 | if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { |
cea7e2df | 1165 | if (cpu_has_confreg()) { |
1da177e4 | 1166 | c->cputype = CPU_R3081E; |
cea7e2df RB |
1167 | __cpu_name[cpu] = "R3081"; |
1168 | } else { | |
1da177e4 | 1169 | c->cputype = CPU_R3000A; |
cea7e2df RB |
1170 | __cpu_name[cpu] = "R3000A"; |
1171 | } | |
cea7e2df | 1172 | } else { |
1da177e4 | 1173 | c->cputype = CPU_R3000; |
cea7e2df RB |
1174 | __cpu_name[cpu] = "R3000"; |
1175 | } | |
9b26616c | 1176 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
02cf2119 | 1177 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
03751e79 | 1178 | MIPS_CPU_NOFPUEX; |
1da177e4 LT |
1179 | if (__cpu_has_fpu()) |
1180 | c->options |= MIPS_CPU_FPU; | |
1181 | c->tlbsize = 64; | |
1182 | break; | |
1183 | case PRID_IMP_R4000: | |
1184 | if (read_c0_config() & CONF_SC) { | |
8ff374b9 MR |
1185 | if ((c->processor_id & PRID_REV_MASK) >= |
1186 | PRID_REV_R4400) { | |
1da177e4 | 1187 | c->cputype = CPU_R4400PC; |
cea7e2df RB |
1188 | __cpu_name[cpu] = "R4400PC"; |
1189 | } else { | |
1da177e4 | 1190 | c->cputype = CPU_R4000PC; |
cea7e2df RB |
1191 | __cpu_name[cpu] = "R4000PC"; |
1192 | } | |
1da177e4 | 1193 | } else { |
7f177a52 MR |
1194 | int cca = read_c0_config() & CONF_CM_CMASK; |
1195 | int mc; | |
1196 | ||
1197 | /* | |
1198 | * SC and MC versions can't be reliably told apart, | |
1199 | * but only the latter support coherent caching | |
1200 | * modes so assume the firmware has set the KSEG0 | |
1201 | * coherency attribute reasonably (if uncached, we | |
1202 | * assume SC). | |
1203 | */ | |
1204 | switch (cca) { | |
1205 | case CONF_CM_CACHABLE_CE: | |
1206 | case CONF_CM_CACHABLE_COW: | |
1207 | case CONF_CM_CACHABLE_CUW: | |
1208 | mc = 1; | |
1209 | break; | |
1210 | default: | |
1211 | mc = 0; | |
1212 | break; | |
1213 | } | |
8ff374b9 MR |
1214 | if ((c->processor_id & PRID_REV_MASK) >= |
1215 | PRID_REV_R4400) { | |
7f177a52 MR |
1216 | c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; |
1217 | __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; | |
cea7e2df | 1218 | } else { |
7f177a52 MR |
1219 | c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; |
1220 | __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; | |
cea7e2df | 1221 | } |
1da177e4 LT |
1222 | } |
1223 | ||
a96102be | 1224 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 1225 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 1226 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 SH |
1227 | MIPS_CPU_WATCH | MIPS_CPU_VCE | |
1228 | MIPS_CPU_LLSC; | |
1da177e4 LT |
1229 | c->tlbsize = 48; |
1230 | break; | |
1231 | case PRID_IMP_VR41XX: | |
9f91e506 | 1232 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 1233 | c->fpu_msk31 |= FPU_CSR_CONDX; |
9f91e506 YY |
1234 | c->options = R4K_OPTS; |
1235 | c->tlbsize = 32; | |
1da177e4 | 1236 | switch (c->processor_id & 0xf0) { |
1da177e4 LT |
1237 | case PRID_REV_VR4111: |
1238 | c->cputype = CPU_VR4111; | |
cea7e2df | 1239 | __cpu_name[cpu] = "NEC VR4111"; |
1da177e4 | 1240 | break; |
1da177e4 LT |
1241 | case PRID_REV_VR4121: |
1242 | c->cputype = CPU_VR4121; | |
cea7e2df | 1243 | __cpu_name[cpu] = "NEC VR4121"; |
1da177e4 LT |
1244 | break; |
1245 | case PRID_REV_VR4122: | |
cea7e2df | 1246 | if ((c->processor_id & 0xf) < 0x3) { |
1da177e4 | 1247 | c->cputype = CPU_VR4122; |
cea7e2df RB |
1248 | __cpu_name[cpu] = "NEC VR4122"; |
1249 | } else { | |
1da177e4 | 1250 | c->cputype = CPU_VR4181A; |
cea7e2df RB |
1251 | __cpu_name[cpu] = "NEC VR4181A"; |
1252 | } | |
1da177e4 LT |
1253 | break; |
1254 | case PRID_REV_VR4130: | |
cea7e2df | 1255 | if ((c->processor_id & 0xf) < 0x4) { |
1da177e4 | 1256 | c->cputype = CPU_VR4131; |
cea7e2df RB |
1257 | __cpu_name[cpu] = "NEC VR4131"; |
1258 | } else { | |
1da177e4 | 1259 | c->cputype = CPU_VR4133; |
9f91e506 | 1260 | c->options |= MIPS_CPU_LLSC; |
cea7e2df RB |
1261 | __cpu_name[cpu] = "NEC VR4133"; |
1262 | } | |
1da177e4 LT |
1263 | break; |
1264 | default: | |
1265 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); | |
1266 | c->cputype = CPU_VR41XX; | |
cea7e2df | 1267 | __cpu_name[cpu] = "NEC Vr41xx"; |
1da177e4 LT |
1268 | break; |
1269 | } | |
1da177e4 LT |
1270 | break; |
1271 | case PRID_IMP_R4300: | |
1272 | c->cputype = CPU_R4300; | |
cea7e2df | 1273 | __cpu_name[cpu] = "R4300"; |
a96102be | 1274 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 1275 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 1276 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 1277 | MIPS_CPU_LLSC; |
1da177e4 LT |
1278 | c->tlbsize = 32; |
1279 | break; | |
1280 | case PRID_IMP_R4600: | |
1281 | c->cputype = CPU_R4600; | |
cea7e2df | 1282 | __cpu_name[cpu] = "R4600"; |
a96102be | 1283 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 1284 | c->fpu_msk31 |= FPU_CSR_CONDX; |
075e7502 TS |
1285 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1286 | MIPS_CPU_LLSC; | |
1da177e4 LT |
1287 | c->tlbsize = 48; |
1288 | break; | |
1289 | #if 0 | |
03751e79 | 1290 | case PRID_IMP_R4650: |
1da177e4 LT |
1291 | /* |
1292 | * This processor doesn't have an MMU, so it's not | |
1293 | * "real easy" to run Linux on it. It is left purely | |
1294 | * for documentation. Commented out because it shares | |
1295 | * it's c0_prid id number with the TX3900. | |
1296 | */ | |
a3dddd56 | 1297 | c->cputype = CPU_R4650; |
cea7e2df | 1298 | __cpu_name[cpu] = "R4650"; |
a96102be | 1299 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 1300 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 1301 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; |
03751e79 | 1302 | c->tlbsize = 48; |
1da177e4 LT |
1303 | break; |
1304 | #endif | |
1305 | case PRID_IMP_TX39: | |
9b26616c | 1306 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
02cf2119 | 1307 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
1da177e4 LT |
1308 | |
1309 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { | |
1310 | c->cputype = CPU_TX3927; | |
cea7e2df | 1311 | __cpu_name[cpu] = "TX3927"; |
1da177e4 LT |
1312 | c->tlbsize = 64; |
1313 | } else { | |
8ff374b9 | 1314 | switch (c->processor_id & PRID_REV_MASK) { |
1da177e4 LT |
1315 | case PRID_REV_TX3912: |
1316 | c->cputype = CPU_TX3912; | |
cea7e2df | 1317 | __cpu_name[cpu] = "TX3912"; |
1da177e4 LT |
1318 | c->tlbsize = 32; |
1319 | break; | |
1320 | case PRID_REV_TX3922: | |
1321 | c->cputype = CPU_TX3922; | |
cea7e2df | 1322 | __cpu_name[cpu] = "TX3922"; |
1da177e4 LT |
1323 | c->tlbsize = 64; |
1324 | break; | |
1da177e4 LT |
1325 | } |
1326 | } | |
1327 | break; | |
1328 | case PRID_IMP_R4700: | |
1329 | c->cputype = CPU_R4700; | |
cea7e2df | 1330 | __cpu_name[cpu] = "R4700"; |
a96102be | 1331 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 1332 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 1333 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 1334 | MIPS_CPU_LLSC; |
1da177e4 LT |
1335 | c->tlbsize = 48; |
1336 | break; | |
1337 | case PRID_IMP_TX49: | |
1338 | c->cputype = CPU_TX49XX; | |
cea7e2df | 1339 | __cpu_name[cpu] = "R49XX"; |
a96102be | 1340 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 1341 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 LT |
1342 | c->options = R4K_OPTS | MIPS_CPU_LLSC; |
1343 | if (!(c->processor_id & 0x08)) | |
1344 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; | |
1345 | c->tlbsize = 48; | |
1346 | break; | |
1347 | case PRID_IMP_R5000: | |
1348 | c->cputype = CPU_R5000; | |
cea7e2df | 1349 | __cpu_name[cpu] = "R5000"; |
a96102be | 1350 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 1351 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 1352 | MIPS_CPU_LLSC; |
1da177e4 LT |
1353 | c->tlbsize = 48; |
1354 | break; | |
1355 | case PRID_IMP_R5432: | |
1356 | c->cputype = CPU_R5432; | |
cea7e2df | 1357 | __cpu_name[cpu] = "R5432"; |
a96102be | 1358 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 1359 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 1360 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
1da177e4 LT |
1361 | c->tlbsize = 48; |
1362 | break; | |
1363 | case PRID_IMP_R5500: | |
1364 | c->cputype = CPU_R5500; | |
cea7e2df | 1365 | __cpu_name[cpu] = "R5500"; |
a96102be | 1366 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 1367 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 1368 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
1da177e4 LT |
1369 | c->tlbsize = 48; |
1370 | break; | |
1371 | case PRID_IMP_NEVADA: | |
1372 | c->cputype = CPU_NEVADA; | |
cea7e2df | 1373 | __cpu_name[cpu] = "Nevada"; |
a96102be | 1374 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 1375 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 1376 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; |
1da177e4 LT |
1377 | c->tlbsize = 48; |
1378 | break; | |
1379 | case PRID_IMP_R6000: | |
1380 | c->cputype = CPU_R6000; | |
cea7e2df | 1381 | __cpu_name[cpu] = "R6000"; |
a96102be | 1382 | set_isa(c, MIPS_CPU_ISA_II); |
9b26616c | 1383 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
1da177e4 | 1384 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
03751e79 | 1385 | MIPS_CPU_LLSC; |
1da177e4 LT |
1386 | c->tlbsize = 32; |
1387 | break; | |
1388 | case PRID_IMP_R6000A: | |
1389 | c->cputype = CPU_R6000A; | |
cea7e2df | 1390 | __cpu_name[cpu] = "R6000A"; |
a96102be | 1391 | set_isa(c, MIPS_CPU_ISA_II); |
9b26616c | 1392 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
1da177e4 | 1393 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
03751e79 | 1394 | MIPS_CPU_LLSC; |
1da177e4 LT |
1395 | c->tlbsize = 32; |
1396 | break; | |
1397 | case PRID_IMP_RM7000: | |
1398 | c->cputype = CPU_RM7000; | |
cea7e2df | 1399 | __cpu_name[cpu] = "RM7000"; |
a96102be | 1400 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 1401 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 1402 | MIPS_CPU_LLSC; |
1da177e4 | 1403 | /* |
70342287 | 1404 | * Undocumented RM7000: Bit 29 in the info register of |
1da177e4 LT |
1405 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 |
1406 | * entries. | |
1407 | * | |
70342287 RB |
1408 | * 29 1 => 64 entry JTLB |
1409 | * 0 => 48 entry JTLB | |
1da177e4 LT |
1410 | */ |
1411 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
1da177e4 LT |
1412 | break; |
1413 | case PRID_IMP_R8000: | |
1414 | c->cputype = CPU_R8000; | |
cea7e2df | 1415 | __cpu_name[cpu] = "RM8000"; |
a96102be | 1416 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 1417 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | |
03751e79 SH |
1418 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1419 | MIPS_CPU_LLSC; | |
1da177e4 LT |
1420 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ |
1421 | break; | |
1422 | case PRID_IMP_R10000: | |
1423 | c->cputype = CPU_R10000; | |
cea7e2df | 1424 | __cpu_name[cpu] = "R10000"; |
a96102be | 1425 | set_isa(c, MIPS_CPU_ISA_IV); |
8b36612a | 1426 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 1427 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1da177e4 | 1428 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
03751e79 | 1429 | MIPS_CPU_LLSC; |
1da177e4 LT |
1430 | c->tlbsize = 64; |
1431 | break; | |
1432 | case PRID_IMP_R12000: | |
1433 | c->cputype = CPU_R12000; | |
cea7e2df | 1434 | __cpu_name[cpu] = "R12000"; |
a96102be | 1435 | set_isa(c, MIPS_CPU_ISA_IV); |
8b36612a | 1436 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 1437 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1da177e4 | 1438 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
8d5ded16 | 1439 | MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; |
1da177e4 LT |
1440 | c->tlbsize = 64; |
1441 | break; | |
44d921b2 | 1442 | case PRID_IMP_R14000: |
30577391 JK |
1443 | if (((c->processor_id >> 4) & 0x0f) > 2) { |
1444 | c->cputype = CPU_R16000; | |
1445 | __cpu_name[cpu] = "R16000"; | |
1446 | } else { | |
1447 | c->cputype = CPU_R14000; | |
1448 | __cpu_name[cpu] = "R14000"; | |
1449 | } | |
a96102be | 1450 | set_isa(c, MIPS_CPU_ISA_IV); |
44d921b2 | 1451 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 1452 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
44d921b2 | 1453 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
8d5ded16 | 1454 | MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; |
44d921b2 K |
1455 | c->tlbsize = 64; |
1456 | break; | |
26859198 | 1457 | case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ |
5aac1e8a RM |
1458 | switch (c->processor_id & PRID_REV_MASK) { |
1459 | case PRID_REV_LOONGSON2E: | |
c579d310 HC |
1460 | c->cputype = CPU_LOONGSON2; |
1461 | __cpu_name[cpu] = "ICT Loongson-2"; | |
5aac1e8a | 1462 | set_elf_platform(cpu, "loongson2e"); |
7352c8b1 | 1463 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 1464 | c->fpu_msk31 |= FPU_CSR_CONDX; |
5aac1e8a RM |
1465 | break; |
1466 | case PRID_REV_LOONGSON2F: | |
c579d310 HC |
1467 | c->cputype = CPU_LOONGSON2; |
1468 | __cpu_name[cpu] = "ICT Loongson-2"; | |
5aac1e8a | 1469 | set_elf_platform(cpu, "loongson2f"); |
7352c8b1 | 1470 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 1471 | c->fpu_msk31 |= FPU_CSR_CONDX; |
5aac1e8a | 1472 | break; |
b2edcfc8 | 1473 | case PRID_REV_LOONGSON3A_R1: |
c579d310 HC |
1474 | c->cputype = CPU_LOONGSON3; |
1475 | __cpu_name[cpu] = "ICT Loongson-3"; | |
1476 | set_elf_platform(cpu, "loongson3a"); | |
7352c8b1 | 1477 | set_isa(c, MIPS_CPU_ISA_M64R1); |
c579d310 | 1478 | break; |
e7841be5 HC |
1479 | case PRID_REV_LOONGSON3B_R1: |
1480 | case PRID_REV_LOONGSON3B_R2: | |
1481 | c->cputype = CPU_LOONGSON3; | |
1482 | __cpu_name[cpu] = "ICT Loongson-3"; | |
1483 | set_elf_platform(cpu, "loongson3b"); | |
7352c8b1 | 1484 | set_isa(c, MIPS_CPU_ISA_M64R1); |
e7841be5 | 1485 | break; |
5aac1e8a RM |
1486 | } |
1487 | ||
2a21c730 FZ |
1488 | c->options = R4K_OPTS | |
1489 | MIPS_CPU_FPU | MIPS_CPU_LLSC | | |
1490 | MIPS_CPU_32FPR; | |
1491 | c->tlbsize = 64; | |
cc94ea31 | 1492 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
2a21c730 | 1493 | break; |
26859198 | 1494 | case PRID_IMP_LOONGSON_32: /* Loongson-1 */ |
2fa36399 | 1495 | decode_configs(c); |
b4672d37 | 1496 | |
2fa36399 | 1497 | c->cputype = CPU_LOONGSON1; |
1da177e4 | 1498 | |
2fa36399 KC |
1499 | switch (c->processor_id & PRID_REV_MASK) { |
1500 | case PRID_REV_LOONGSON1B: | |
1501 | __cpu_name[cpu] = "Loongson 1B"; | |
b4672d37 | 1502 | break; |
b4672d37 | 1503 | } |
4194318c | 1504 | |
2fa36399 | 1505 | break; |
1da177e4 | 1506 | } |
1da177e4 LT |
1507 | } |
1508 | ||
cea7e2df | 1509 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1510 | { |
4f12b91d | 1511 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
8ff374b9 | 1512 | switch (c->processor_id & PRID_IMP_MASK) { |
b2498af5 LY |
1513 | case PRID_IMP_QEMU_GENERIC: |
1514 | c->writecombine = _CACHE_UNCACHED; | |
1515 | c->cputype = CPU_QEMU_GENERIC; | |
1516 | __cpu_name[cpu] = "MIPS GENERIC QEMU"; | |
1517 | break; | |
1da177e4 LT |
1518 | case PRID_IMP_4KC: |
1519 | c->cputype = CPU_4KC; | |
4f12b91d | 1520 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1521 | __cpu_name[cpu] = "MIPS 4Kc"; |
1da177e4 LT |
1522 | break; |
1523 | case PRID_IMP_4KEC: | |
2b07bd02 RB |
1524 | case PRID_IMP_4KECR2: |
1525 | c->cputype = CPU_4KEC; | |
4f12b91d | 1526 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1527 | __cpu_name[cpu] = "MIPS 4KEc"; |
2b07bd02 | 1528 | break; |
1da177e4 | 1529 | case PRID_IMP_4KSC: |
8afcb5d8 | 1530 | case PRID_IMP_4KSD: |
1da177e4 | 1531 | c->cputype = CPU_4KSC; |
4f12b91d | 1532 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1533 | __cpu_name[cpu] = "MIPS 4KSc"; |
1da177e4 LT |
1534 | break; |
1535 | case PRID_IMP_5KC: | |
1536 | c->cputype = CPU_5KC; | |
4f12b91d | 1537 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1538 | __cpu_name[cpu] = "MIPS 5Kc"; |
1da177e4 | 1539 | break; |
78d4803f LY |
1540 | case PRID_IMP_5KE: |
1541 | c->cputype = CPU_5KE; | |
4f12b91d | 1542 | c->writecombine = _CACHE_UNCACHED; |
78d4803f LY |
1543 | __cpu_name[cpu] = "MIPS 5KE"; |
1544 | break; | |
1da177e4 LT |
1545 | case PRID_IMP_20KC: |
1546 | c->cputype = CPU_20KC; | |
4f12b91d | 1547 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1548 | __cpu_name[cpu] = "MIPS 20Kc"; |
1da177e4 LT |
1549 | break; |
1550 | case PRID_IMP_24K: | |
1551 | c->cputype = CPU_24K; | |
4f12b91d | 1552 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1553 | __cpu_name[cpu] = "MIPS 24Kc"; |
1da177e4 | 1554 | break; |
42f3caef JC |
1555 | case PRID_IMP_24KE: |
1556 | c->cputype = CPU_24K; | |
4f12b91d | 1557 | c->writecombine = _CACHE_UNCACHED; |
42f3caef JC |
1558 | __cpu_name[cpu] = "MIPS 24KEc"; |
1559 | break; | |
1da177e4 LT |
1560 | case PRID_IMP_25KF: |
1561 | c->cputype = CPU_25KF; | |
4f12b91d | 1562 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1563 | __cpu_name[cpu] = "MIPS 25Kc"; |
1da177e4 | 1564 | break; |
bbc7f22f RB |
1565 | case PRID_IMP_34K: |
1566 | c->cputype = CPU_34K; | |
4f12b91d | 1567 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1568 | __cpu_name[cpu] = "MIPS 34Kc"; |
bbc7f22f | 1569 | break; |
c620953c CD |
1570 | case PRID_IMP_74K: |
1571 | c->cputype = CPU_74K; | |
4f12b91d | 1572 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1573 | __cpu_name[cpu] = "MIPS 74Kc"; |
c620953c | 1574 | break; |
113c62d9 SH |
1575 | case PRID_IMP_M14KC: |
1576 | c->cputype = CPU_M14KC; | |
4f12b91d | 1577 | c->writecombine = _CACHE_UNCACHED; |
113c62d9 SH |
1578 | __cpu_name[cpu] = "MIPS M14Kc"; |
1579 | break; | |
f8fa4811 SH |
1580 | case PRID_IMP_M14KEC: |
1581 | c->cputype = CPU_M14KEC; | |
4f12b91d | 1582 | c->writecombine = _CACHE_UNCACHED; |
f8fa4811 SH |
1583 | __cpu_name[cpu] = "MIPS M14KEc"; |
1584 | break; | |
39b8d525 RB |
1585 | case PRID_IMP_1004K: |
1586 | c->cputype = CPU_1004K; | |
4f12b91d | 1587 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1588 | __cpu_name[cpu] = "MIPS 1004Kc"; |
39b8d525 | 1589 | break; |
006a851b | 1590 | case PRID_IMP_1074K: |
442e14a2 | 1591 | c->cputype = CPU_1074K; |
4f12b91d | 1592 | c->writecombine = _CACHE_UNCACHED; |
006a851b SH |
1593 | __cpu_name[cpu] = "MIPS 1074Kc"; |
1594 | break; | |
b5f065e7 LY |
1595 | case PRID_IMP_INTERAPTIV_UP: |
1596 | c->cputype = CPU_INTERAPTIV; | |
1597 | __cpu_name[cpu] = "MIPS interAptiv"; | |
1598 | break; | |
1599 | case PRID_IMP_INTERAPTIV_MP: | |
1600 | c->cputype = CPU_INTERAPTIV; | |
1601 | __cpu_name[cpu] = "MIPS interAptiv (multi)"; | |
1602 | break; | |
b0d4d300 LY |
1603 | case PRID_IMP_PROAPTIV_UP: |
1604 | c->cputype = CPU_PROAPTIV; | |
1605 | __cpu_name[cpu] = "MIPS proAptiv"; | |
1606 | break; | |
1607 | case PRID_IMP_PROAPTIV_MP: | |
1608 | c->cputype = CPU_PROAPTIV; | |
1609 | __cpu_name[cpu] = "MIPS proAptiv (multi)"; | |
1610 | break; | |
829dcc0a JH |
1611 | case PRID_IMP_P5600: |
1612 | c->cputype = CPU_P5600; | |
1613 | __cpu_name[cpu] = "MIPS P5600"; | |
1614 | break; | |
eba20a3a PB |
1615 | case PRID_IMP_P6600: |
1616 | c->cputype = CPU_P6600; | |
1617 | __cpu_name[cpu] = "MIPS P6600"; | |
1618 | break; | |
e57f9a2d MC |
1619 | case PRID_IMP_I6400: |
1620 | c->cputype = CPU_I6400; | |
1621 | __cpu_name[cpu] = "MIPS I6400"; | |
1622 | break; | |
9943ed92 LY |
1623 | case PRID_IMP_M5150: |
1624 | c->cputype = CPU_M5150; | |
1625 | __cpu_name[cpu] = "MIPS M5150"; | |
1626 | break; | |
43aff742 PB |
1627 | case PRID_IMP_M6250: |
1628 | c->cputype = CPU_M6250; | |
1629 | __cpu_name[cpu] = "MIPS M6250"; | |
1630 | break; | |
1da177e4 | 1631 | } |
0b6d497f | 1632 | |
75b5b5e0 LY |
1633 | decode_configs(c); |
1634 | ||
0b6d497f | 1635 | spram_config(); |
1da177e4 LT |
1636 | } |
1637 | ||
cea7e2df | 1638 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1639 | { |
4194318c | 1640 | decode_configs(c); |
8ff374b9 | 1641 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1642 | case PRID_IMP_AU1_REV1: |
1643 | case PRID_IMP_AU1_REV2: | |
270717a8 | 1644 | c->cputype = CPU_ALCHEMY; |
1da177e4 LT |
1645 | switch ((c->processor_id >> 24) & 0xff) { |
1646 | case 0: | |
cea7e2df | 1647 | __cpu_name[cpu] = "Au1000"; |
1da177e4 LT |
1648 | break; |
1649 | case 1: | |
cea7e2df | 1650 | __cpu_name[cpu] = "Au1500"; |
1da177e4 LT |
1651 | break; |
1652 | case 2: | |
cea7e2df | 1653 | __cpu_name[cpu] = "Au1100"; |
1da177e4 LT |
1654 | break; |
1655 | case 3: | |
cea7e2df | 1656 | __cpu_name[cpu] = "Au1550"; |
1da177e4 | 1657 | break; |
e3ad1c23 | 1658 | case 4: |
cea7e2df | 1659 | __cpu_name[cpu] = "Au1200"; |
8ff374b9 | 1660 | if ((c->processor_id & PRID_REV_MASK) == 2) |
cea7e2df | 1661 | __cpu_name[cpu] = "Au1250"; |
237cfee1 ML |
1662 | break; |
1663 | case 5: | |
cea7e2df | 1664 | __cpu_name[cpu] = "Au1210"; |
e3ad1c23 | 1665 | break; |
1da177e4 | 1666 | default: |
270717a8 | 1667 | __cpu_name[cpu] = "Au1xxx"; |
1da177e4 LT |
1668 | break; |
1669 | } | |
1da177e4 LT |
1670 | break; |
1671 | } | |
1672 | } | |
1673 | ||
cea7e2df | 1674 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1675 | { |
4194318c | 1676 | decode_configs(c); |
02cf2119 | 1677 | |
4f12b91d | 1678 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
8ff374b9 | 1679 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1680 | case PRID_IMP_SB1: |
1681 | c->cputype = CPU_SB1; | |
cea7e2df | 1682 | __cpu_name[cpu] = "SiByte SB1"; |
1da177e4 | 1683 | /* FPU in pass1 is known to have issues. */ |
8ff374b9 | 1684 | if ((c->processor_id & PRID_REV_MASK) < 0x02) |
010b853b | 1685 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
1da177e4 | 1686 | break; |
93ce2f52 AI |
1687 | case PRID_IMP_SB1A: |
1688 | c->cputype = CPU_SB1A; | |
cea7e2df | 1689 | __cpu_name[cpu] = "SiByte SB1A"; |
93ce2f52 | 1690 | break; |
1da177e4 LT |
1691 | } |
1692 | } | |
1693 | ||
cea7e2df | 1694 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1695 | { |
4194318c | 1696 | decode_configs(c); |
8ff374b9 | 1697 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1698 | case PRID_IMP_SR71000: |
1699 | c->cputype = CPU_SR71000; | |
cea7e2df | 1700 | __cpu_name[cpu] = "Sandcraft SR71000"; |
1da177e4 LT |
1701 | c->scache.ways = 8; |
1702 | c->tlbsize = 64; | |
1703 | break; | |
1704 | } | |
1705 | } | |
1706 | ||
cea7e2df | 1707 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
bdf21b18 PP |
1708 | { |
1709 | decode_configs(c); | |
8ff374b9 | 1710 | switch (c->processor_id & PRID_IMP_MASK) { |
bdf21b18 PP |
1711 | case PRID_IMP_PR4450: |
1712 | c->cputype = CPU_PR4450; | |
cea7e2df | 1713 | __cpu_name[cpu] = "Philips PR4450"; |
a96102be | 1714 | set_isa(c, MIPS_CPU_ISA_M32R1); |
bdf21b18 | 1715 | break; |
bdf21b18 PP |
1716 | } |
1717 | } | |
1718 | ||
cea7e2df | 1719 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
1c0c13eb AJ |
1720 | { |
1721 | decode_configs(c); | |
8ff374b9 | 1722 | switch (c->processor_id & PRID_IMP_MASK) { |
190fca3e KC |
1723 | case PRID_IMP_BMIPS32_REV4: |
1724 | case PRID_IMP_BMIPS32_REV8: | |
602977b0 KC |
1725 | c->cputype = CPU_BMIPS32; |
1726 | __cpu_name[cpu] = "Broadcom BMIPS32"; | |
06785df0 | 1727 | set_elf_platform(cpu, "bmips32"); |
602977b0 KC |
1728 | break; |
1729 | case PRID_IMP_BMIPS3300: | |
1730 | case PRID_IMP_BMIPS3300_ALT: | |
1731 | case PRID_IMP_BMIPS3300_BUG: | |
1732 | c->cputype = CPU_BMIPS3300; | |
1733 | __cpu_name[cpu] = "Broadcom BMIPS3300"; | |
06785df0 | 1734 | set_elf_platform(cpu, "bmips3300"); |
602977b0 KC |
1735 | break; |
1736 | case PRID_IMP_BMIPS43XX: { | |
8ff374b9 | 1737 | int rev = c->processor_id & PRID_REV_MASK; |
602977b0 KC |
1738 | |
1739 | if (rev >= PRID_REV_BMIPS4380_LO && | |
1740 | rev <= PRID_REV_BMIPS4380_HI) { | |
1741 | c->cputype = CPU_BMIPS4380; | |
1742 | __cpu_name[cpu] = "Broadcom BMIPS4380"; | |
06785df0 | 1743 | set_elf_platform(cpu, "bmips4380"); |
b4720809 | 1744 | c->options |= MIPS_CPU_RIXI; |
602977b0 KC |
1745 | } else { |
1746 | c->cputype = CPU_BMIPS4350; | |
1747 | __cpu_name[cpu] = "Broadcom BMIPS4350"; | |
06785df0 | 1748 | set_elf_platform(cpu, "bmips4350"); |
602977b0 | 1749 | } |
0de663ef | 1750 | break; |
602977b0 KC |
1751 | } |
1752 | case PRID_IMP_BMIPS5000: | |
68e6a783 | 1753 | case PRID_IMP_BMIPS5200: |
602977b0 | 1754 | c->cputype = CPU_BMIPS5000; |
37808d62 FF |
1755 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) |
1756 | __cpu_name[cpu] = "Broadcom BMIPS5200"; | |
1757 | else | |
1758 | __cpu_name[cpu] = "Broadcom BMIPS5000"; | |
06785df0 | 1759 | set_elf_platform(cpu, "bmips5000"); |
b4720809 | 1760 | c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; |
0de663ef | 1761 | break; |
1c0c13eb AJ |
1762 | } |
1763 | } | |
1764 | ||
0dd4781b DD |
1765 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
1766 | { | |
1767 | decode_configs(c); | |
8ff374b9 | 1768 | switch (c->processor_id & PRID_IMP_MASK) { |
0dd4781b DD |
1769 | case PRID_IMP_CAVIUM_CN38XX: |
1770 | case PRID_IMP_CAVIUM_CN31XX: | |
1771 | case PRID_IMP_CAVIUM_CN30XX: | |
6f329468 DD |
1772 | c->cputype = CPU_CAVIUM_OCTEON; |
1773 | __cpu_name[cpu] = "Cavium Octeon"; | |
1774 | goto platform; | |
0dd4781b DD |
1775 | case PRID_IMP_CAVIUM_CN58XX: |
1776 | case PRID_IMP_CAVIUM_CN56XX: | |
1777 | case PRID_IMP_CAVIUM_CN50XX: | |
1778 | case PRID_IMP_CAVIUM_CN52XX: | |
6f329468 DD |
1779 | c->cputype = CPU_CAVIUM_OCTEON_PLUS; |
1780 | __cpu_name[cpu] = "Cavium Octeon+"; | |
1781 | platform: | |
c094c99e | 1782 | set_elf_platform(cpu, "octeon"); |
0dd4781b | 1783 | break; |
a1431b61 | 1784 | case PRID_IMP_CAVIUM_CN61XX: |
0e56b385 | 1785 | case PRID_IMP_CAVIUM_CN63XX: |
a1431b61 DD |
1786 | case PRID_IMP_CAVIUM_CN66XX: |
1787 | case PRID_IMP_CAVIUM_CN68XX: | |
af04bb85 | 1788 | case PRID_IMP_CAVIUM_CNF71XX: |
0e56b385 DD |
1789 | c->cputype = CPU_CAVIUM_OCTEON2; |
1790 | __cpu_name[cpu] = "Cavium Octeon II"; | |
c094c99e | 1791 | set_elf_platform(cpu, "octeon2"); |
0e56b385 | 1792 | break; |
af04bb85 | 1793 | case PRID_IMP_CAVIUM_CN70XX: |
b8c8f665 DD |
1794 | case PRID_IMP_CAVIUM_CN73XX: |
1795 | case PRID_IMP_CAVIUM_CNF75XX: | |
af04bb85 DD |
1796 | case PRID_IMP_CAVIUM_CN78XX: |
1797 | c->cputype = CPU_CAVIUM_OCTEON3; | |
1798 | __cpu_name[cpu] = "Cavium Octeon III"; | |
1799 | set_elf_platform(cpu, "octeon3"); | |
1800 | break; | |
0dd4781b DD |
1801 | default: |
1802 | printk(KERN_INFO "Unknown Octeon chip!\n"); | |
1803 | c->cputype = CPU_UNKNOWN; | |
1804 | break; | |
1805 | } | |
1806 | } | |
1807 | ||
b2edcfc8 HC |
1808 | static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) |
1809 | { | |
1810 | switch (c->processor_id & PRID_IMP_MASK) { | |
1811 | case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ | |
1812 | switch (c->processor_id & PRID_REV_MASK) { | |
1813 | case PRID_REV_LOONGSON3A_R2: | |
1814 | c->cputype = CPU_LOONGSON3; | |
1815 | __cpu_name[cpu] = "ICT Loongson-3"; | |
1816 | set_elf_platform(cpu, "loongson3a"); | |
1817 | set_isa(c, MIPS_CPU_ISA_M64R2); | |
1818 | break; | |
1819 | } | |
1820 | ||
1821 | decode_configs(c); | |
380cd582 | 1822 | c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; |
b2edcfc8 HC |
1823 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
1824 | break; | |
1825 | default: | |
1826 | panic("Unknown Loongson Processor ID!"); | |
1827 | break; | |
1828 | } | |
1829 | } | |
1830 | ||
83ccf69d LPC |
1831 | static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) |
1832 | { | |
1833 | decode_configs(c); | |
1834 | /* JZRISC does not implement the CP0 counter. */ | |
1835 | c->options &= ~MIPS_CPU_COUNTER; | |
06947aaa | 1836 | BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); |
8ff374b9 | 1837 | switch (c->processor_id & PRID_IMP_MASK) { |
83ccf69d LPC |
1838 | case PRID_IMP_JZRISC: |
1839 | c->cputype = CPU_JZRISC; | |
4f12b91d | 1840 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
83ccf69d LPC |
1841 | __cpu_name[cpu] = "Ingenic JZRISC"; |
1842 | break; | |
1843 | default: | |
1844 | panic("Unknown Ingenic Processor ID!"); | |
1845 | break; | |
1846 | } | |
1847 | } | |
1848 | ||
a7117c6b J |
1849 | static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) |
1850 | { | |
1851 | decode_configs(c); | |
1852 | ||
8ff374b9 | 1853 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { |
809f36c6 ML |
1854 | c->cputype = CPU_ALCHEMY; |
1855 | __cpu_name[cpu] = "Au1300"; | |
1856 | /* following stuff is not for Alchemy */ | |
1857 | return; | |
1858 | } | |
1859 | ||
70342287 RB |
1860 | c->options = (MIPS_CPU_TLB | |
1861 | MIPS_CPU_4KEX | | |
a7117c6b | 1862 | MIPS_CPU_COUNTER | |
70342287 RB |
1863 | MIPS_CPU_DIVEC | |
1864 | MIPS_CPU_WATCH | | |
1865 | MIPS_CPU_EJTAG | | |
a7117c6b J |
1866 | MIPS_CPU_LLSC); |
1867 | ||
8ff374b9 | 1868 | switch (c->processor_id & PRID_IMP_MASK) { |
4ca86a2f | 1869 | case PRID_IMP_NETLOGIC_XLP2XX: |
8907c55e | 1870 | case PRID_IMP_NETLOGIC_XLP9XX: |
1c983986 | 1871 | case PRID_IMP_NETLOGIC_XLP5XX: |
4ca86a2f J |
1872 | c->cputype = CPU_XLP; |
1873 | __cpu_name[cpu] = "Broadcom XLPII"; | |
1874 | break; | |
1875 | ||
2aa54b20 J |
1876 | case PRID_IMP_NETLOGIC_XLP8XX: |
1877 | case PRID_IMP_NETLOGIC_XLP3XX: | |
a3d4fb2d J |
1878 | c->cputype = CPU_XLP; |
1879 | __cpu_name[cpu] = "Netlogic XLP"; | |
1880 | break; | |
1881 | ||
a7117c6b J |
1882 | case PRID_IMP_NETLOGIC_XLR732: |
1883 | case PRID_IMP_NETLOGIC_XLR716: | |
1884 | case PRID_IMP_NETLOGIC_XLR532: | |
1885 | case PRID_IMP_NETLOGIC_XLR308: | |
1886 | case PRID_IMP_NETLOGIC_XLR532C: | |
1887 | case PRID_IMP_NETLOGIC_XLR516C: | |
1888 | case PRID_IMP_NETLOGIC_XLR508C: | |
1889 | case PRID_IMP_NETLOGIC_XLR308C: | |
1890 | c->cputype = CPU_XLR; | |
1891 | __cpu_name[cpu] = "Netlogic XLR"; | |
1892 | break; | |
1893 | ||
1894 | case PRID_IMP_NETLOGIC_XLS608: | |
1895 | case PRID_IMP_NETLOGIC_XLS408: | |
1896 | case PRID_IMP_NETLOGIC_XLS404: | |
1897 | case PRID_IMP_NETLOGIC_XLS208: | |
1898 | case PRID_IMP_NETLOGIC_XLS204: | |
1899 | case PRID_IMP_NETLOGIC_XLS108: | |
1900 | case PRID_IMP_NETLOGIC_XLS104: | |
1901 | case PRID_IMP_NETLOGIC_XLS616B: | |
1902 | case PRID_IMP_NETLOGIC_XLS608B: | |
1903 | case PRID_IMP_NETLOGIC_XLS416B: | |
1904 | case PRID_IMP_NETLOGIC_XLS412B: | |
1905 | case PRID_IMP_NETLOGIC_XLS408B: | |
1906 | case PRID_IMP_NETLOGIC_XLS404B: | |
1907 | c->cputype = CPU_XLR; | |
1908 | __cpu_name[cpu] = "Netlogic XLS"; | |
1909 | break; | |
1910 | ||
1911 | default: | |
a3d4fb2d | 1912 | pr_info("Unknown Netlogic chip id [%02x]!\n", |
a7117c6b J |
1913 | c->processor_id); |
1914 | c->cputype = CPU_XLR; | |
1915 | break; | |
1916 | } | |
1917 | ||
a3d4fb2d | 1918 | if (c->cputype == CPU_XLP) { |
a96102be | 1919 | set_isa(c, MIPS_CPU_ISA_M64R2); |
a3d4fb2d J |
1920 | c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); |
1921 | /* This will be updated again after all threads are woken up */ | |
1922 | c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; | |
1923 | } else { | |
a96102be | 1924 | set_isa(c, MIPS_CPU_ISA_M64R1); |
a3d4fb2d J |
1925 | c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; |
1926 | } | |
7777b939 | 1927 | c->kscratch_mask = 0xf; |
a7117c6b J |
1928 | } |
1929 | ||
949e51be DD |
1930 | #ifdef CONFIG_64BIT |
1931 | /* For use by uaccess.h */ | |
1932 | u64 __ua_limit; | |
1933 | EXPORT_SYMBOL(__ua_limit); | |
1934 | #endif | |
1935 | ||
9966db25 | 1936 | const char *__cpu_name[NR_CPUS]; |
874fd3b5 | 1937 | const char *__elf_platform; |
9966db25 | 1938 | |
078a55fc | 1939 | void cpu_probe(void) |
1da177e4 LT |
1940 | { |
1941 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
9966db25 | 1942 | unsigned int cpu = smp_processor_id(); |
1da177e4 | 1943 | |
70342287 | 1944 | c->processor_id = PRID_IMP_UNKNOWN; |
1da177e4 LT |
1945 | c->fpu_id = FPIR_IMP_NONE; |
1946 | c->cputype = CPU_UNKNOWN; | |
4f12b91d | 1947 | c->writecombine = _CACHE_UNCACHED; |
1da177e4 | 1948 | |
9b26616c MR |
1949 | c->fpu_csr31 = FPU_CSR_RN; |
1950 | c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
1951 | ||
1da177e4 | 1952 | c->processor_id = read_c0_prid(); |
8ff374b9 | 1953 | switch (c->processor_id & PRID_COMP_MASK) { |
1da177e4 | 1954 | case PRID_COMP_LEGACY: |
cea7e2df | 1955 | cpu_probe_legacy(c, cpu); |
1da177e4 LT |
1956 | break; |
1957 | case PRID_COMP_MIPS: | |
cea7e2df | 1958 | cpu_probe_mips(c, cpu); |
1da177e4 LT |
1959 | break; |
1960 | case PRID_COMP_ALCHEMY: | |
cea7e2df | 1961 | cpu_probe_alchemy(c, cpu); |
1da177e4 LT |
1962 | break; |
1963 | case PRID_COMP_SIBYTE: | |
cea7e2df | 1964 | cpu_probe_sibyte(c, cpu); |
1da177e4 | 1965 | break; |
1c0c13eb | 1966 | case PRID_COMP_BROADCOM: |
cea7e2df | 1967 | cpu_probe_broadcom(c, cpu); |
1c0c13eb | 1968 | break; |
1da177e4 | 1969 | case PRID_COMP_SANDCRAFT: |
cea7e2df | 1970 | cpu_probe_sandcraft(c, cpu); |
1da177e4 | 1971 | break; |
a92b0588 | 1972 | case PRID_COMP_NXP: |
cea7e2df | 1973 | cpu_probe_nxp(c, cpu); |
a3dddd56 | 1974 | break; |
0dd4781b DD |
1975 | case PRID_COMP_CAVIUM: |
1976 | cpu_probe_cavium(c, cpu); | |
1977 | break; | |
b2edcfc8 HC |
1978 | case PRID_COMP_LOONGSON: |
1979 | cpu_probe_loongson(c, cpu); | |
1980 | break; | |
252617a4 PB |
1981 | case PRID_COMP_INGENIC_D0: |
1982 | case PRID_COMP_INGENIC_D1: | |
1983 | case PRID_COMP_INGENIC_E1: | |
83ccf69d LPC |
1984 | cpu_probe_ingenic(c, cpu); |
1985 | break; | |
a7117c6b J |
1986 | case PRID_COMP_NETLOGIC: |
1987 | cpu_probe_netlogic(c, cpu); | |
1988 | break; | |
1da177e4 | 1989 | } |
dec8b1ca | 1990 | |
cea7e2df RB |
1991 | BUG_ON(!__cpu_name[cpu]); |
1992 | BUG_ON(c->cputype == CPU_UNKNOWN); | |
1993 | ||
dec8b1ca FBH |
1994 | /* |
1995 | * Platform code can force the cpu type to optimize code | |
1996 | * generation. In that case be sure the cpu type is correctly | |
1997 | * manually setup otherwise it could trigger some nasty bugs. | |
1998 | */ | |
1999 | BUG_ON(current_cpu_type() != c->cputype); | |
2000 | ||
2e274768 FF |
2001 | if (cpu_has_rixi) { |
2002 | /* Enable the RIXI exceptions */ | |
2003 | set_c0_pagegrain(PG_IEC); | |
2004 | back_to_back_c0_hazard(); | |
2005 | /* Verify the IEC bit is set */ | |
2006 | if (read_c0_pagegrain() & PG_IEC) | |
2007 | c->options |= MIPS_CPU_RIXIEX; | |
2008 | } | |
2009 | ||
0103d23f KC |
2010 | if (mips_fpu_disabled) |
2011 | c->options &= ~MIPS_CPU_FPU; | |
2012 | ||
2013 | if (mips_dsp_disabled) | |
ee80f7c7 | 2014 | c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
0103d23f | 2015 | |
3d528b32 MC |
2016 | if (mips_htw_disabled) { |
2017 | c->options &= ~MIPS_CPU_HTW; | |
2018 | write_c0_pwctl(read_c0_pwctl() & | |
2019 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); | |
2020 | } | |
2021 | ||
7aecd5ca MR |
2022 | if (c->options & MIPS_CPU_FPU) |
2023 | cpu_set_fpu_opts(c); | |
2024 | else | |
2025 | cpu_set_nofpu_opts(c); | |
9966db25 | 2026 | |
8d5ded16 JK |
2027 | if (cpu_has_bp_ghist) |
2028 | write_c0_r10k_diag(read_c0_r10k_diag() | | |
2029 | R10K_DIAG_E_GHIST); | |
2030 | ||
8b8aa636 | 2031 | if (cpu_has_mips_r2_r6) { |
f6771dbb | 2032 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |
da4b62cd AC |
2033 | /* R2 has Performance Counter Interrupt indicator */ |
2034 | c->options |= MIPS_CPU_PCI; | |
2035 | } | |
f6771dbb RB |
2036 | else |
2037 | c->srsets = 1; | |
91dfc423 | 2038 | |
4c063034 PB |
2039 | if (cpu_has_mips_r6) |
2040 | elf_hwcap |= HWCAP_MIPS_R6; | |
2041 | ||
a8ad1367 | 2042 | if (cpu_has_msa) { |
a5e9a69e | 2043 | c->msa_id = cpu_get_msa_id(); |
a8ad1367 PB |
2044 | WARN(c->msa_id & MSA_IR_WRPF, |
2045 | "Vector register partitioning unimplemented!"); | |
3cc9fa7f | 2046 | elf_hwcap |= HWCAP_MIPS_MSA; |
a8ad1367 | 2047 | } |
a5e9a69e | 2048 | |
6ad816e7 JH |
2049 | if (cpu_has_vz) |
2050 | cpu_probe_vz(c); | |
2051 | ||
91dfc423 | 2052 | cpu_probe_vmbits(c); |
949e51be DD |
2053 | |
2054 | #ifdef CONFIG_64BIT | |
2055 | if (cpu == 0) | |
2056 | __ua_limit = ~((1ull << cpu_vmbits) - 1); | |
2057 | #endif | |
1da177e4 LT |
2058 | } |
2059 | ||
078a55fc | 2060 | void cpu_report(void) |
1da177e4 LT |
2061 | { |
2062 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
2063 | ||
d9f897c9 LY |
2064 | pr_info("CPU%d revision is: %08x (%s)\n", |
2065 | smp_processor_id(), c->processor_id, cpu_name_string()); | |
1da177e4 | 2066 | if (c->options & MIPS_CPU_FPU) |
9966db25 | 2067 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); |
a5e9a69e PB |
2068 | if (cpu_has_msa) |
2069 | pr_info("MSA revision is: %08x\n", c->msa_id); | |
1da177e4 | 2070 | } |