Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Processor capabilities determination functions. | |
3 | * | |
4 | * Copyright (C) xxxx the Anonymous | |
010b853b | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
4194318c | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
70342287 | 7 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ptrace.h> | |
631330f5 | 17 | #include <linux/smp.h> |
1da177e4 | 18 | #include <linux/stddef.h> |
73bc256d | 19 | #include <linux/export.h> |
1da177e4 | 20 | |
5759906c | 21 | #include <asm/bugs.h> |
1da177e4 LT |
22 | #include <asm/cpu.h> |
23 | #include <asm/fpu.h> | |
24 | #include <asm/mipsregs.h> | |
654f57bf | 25 | #include <asm/watch.h> |
06372a63 | 26 | #include <asm/elf.h> |
a074f0e8 | 27 | #include <asm/spram.h> |
949e51be DD |
28 | #include <asm/uaccess.h> |
29 | ||
1da177e4 LT |
30 | /* |
31 | * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, | |
32 | * the implementation of the "wait" feature differs between CPU families. This | |
33 | * points to the function that implements CPU specific wait. | |
34 | * The wait instruction stops the pipeline and reduces the power consumption of | |
35 | * the CPU very much. | |
36 | */ | |
982f6ffe | 37 | void (*cpu_wait)(void); |
f8ede0f7 | 38 | EXPORT_SYMBOL(cpu_wait); |
1da177e4 LT |
39 | |
40 | static void r3081_wait(void) | |
41 | { | |
42 | unsigned long cfg = read_c0_conf(); | |
43 | write_c0_conf(cfg | R30XX_CONF_HALT); | |
44 | } | |
45 | ||
46 | static void r39xx_wait(void) | |
47 | { | |
60a6c377 AN |
48 | local_irq_disable(); |
49 | if (!need_resched()) | |
50 | write_c0_conf(read_c0_conf() | TX39_CONF_HALT); | |
51 | local_irq_enable(); | |
1da177e4 LT |
52 | } |
53 | ||
c65a5480 | 54 | extern void r4k_wait(void); |
60a6c377 AN |
55 | |
56 | /* | |
57 | * This variant is preferable as it allows testing need_resched and going to | |
58 | * sleep depending on the outcome atomically. Unfortunately the "It is | |
59 | * implementation-dependent whether the pipeline restarts when a non-enabled | |
60 | * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes | |
61 | * using this version a gamble. | |
62 | */ | |
8531a35e | 63 | void r4k_wait_irqoff(void) |
60a6c377 AN |
64 | { |
65 | local_irq_disable(); | |
66 | if (!need_resched()) | |
8531a35e KK |
67 | __asm__(" .set push \n" |
68 | " .set mips3 \n" | |
60a6c377 | 69 | " wait \n" |
8531a35e | 70 | " .set pop \n"); |
60a6c377 | 71 | local_irq_enable(); |
70342287 | 72 | __asm__(" .globl __pastwait \n" |
8531a35e | 73 | "__pastwait: \n"); |
1da177e4 LT |
74 | } |
75 | ||
5a812999 | 76 | /* |
70342287 | 77 | * The RM7000 variant has to handle erratum 38. The workaround is to not |
5a812999 RB |
78 | * have any pending stores when the WAIT instruction is executed. |
79 | */ | |
80 | static void rm7k_wait_irqoff(void) | |
81 | { | |
82 | local_irq_disable(); | |
83 | if (!need_resched()) | |
84 | __asm__( | |
85 | " .set push \n" | |
86 | " .set mips3 \n" | |
87 | " .set noat \n" | |
88 | " mfc0 $1, $12 \n" | |
89 | " sync \n" | |
90 | " mtc0 $1, $12 # stalls until W stage \n" | |
91 | " wait \n" | |
92 | " mtc0 $1, $12 # stalls until W stage \n" | |
93 | " .set pop \n"); | |
94 | local_irq_enable(); | |
95 | } | |
96 | ||
2882b0c6 ML |
97 | /* |
98 | * The Au1xxx wait is available only if using 32khz counter or | |
99 | * external timer source, but specifically not CP0 Counter. | |
100 | * alchemy/common/time.c may override cpu_wait! | |
101 | */ | |
494900af | 102 | static void au1k_wait(void) |
1da177e4 | 103 | { |
60a6c377 AN |
104 | __asm__(" .set mips3 \n" |
105 | " cache 0x14, 0(%0) \n" | |
106 | " cache 0x14, 32(%0) \n" | |
107 | " sync \n" | |
108 | " nop \n" | |
109 | " wait \n" | |
110 | " nop \n" | |
111 | " nop \n" | |
112 | " nop \n" | |
113 | " nop \n" | |
114 | " .set mips0 \n" | |
10f650db | 115 | : : "r" (au1k_wait)); |
1da177e4 LT |
116 | } |
117 | ||
982f6ffe | 118 | static int __initdata nowait; |
55d04dff | 119 | |
f49a747c | 120 | static int __init wait_disable(char *s) |
55d04dff RB |
121 | { |
122 | nowait = 1; | |
123 | ||
124 | return 1; | |
125 | } | |
126 | ||
127 | __setup("nowait", wait_disable); | |
128 | ||
0103d23f KC |
129 | static int __cpuinitdata mips_fpu_disabled; |
130 | ||
131 | static int __init fpu_disable(char *s) | |
132 | { | |
133 | cpu_data[0].options &= ~MIPS_CPU_FPU; | |
134 | mips_fpu_disabled = 1; | |
135 | ||
136 | return 1; | |
137 | } | |
138 | ||
139 | __setup("nofpu", fpu_disable); | |
140 | ||
141 | int __cpuinitdata mips_dsp_disabled; | |
142 | ||
143 | static int __init dsp_disable(char *s) | |
144 | { | |
ee80f7c7 | 145 | cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
0103d23f KC |
146 | mips_dsp_disabled = 1; |
147 | ||
148 | return 1; | |
149 | } | |
150 | ||
151 | __setup("nodsp", dsp_disable); | |
152 | ||
c65a5480 | 153 | void __init check_wait(void) |
1da177e4 LT |
154 | { |
155 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
156 | ||
55d04dff | 157 | if (nowait) { |
c2379230 | 158 | printk("Wait instruction disabled.\n"); |
55d04dff RB |
159 | return; |
160 | } | |
161 | ||
1da177e4 LT |
162 | switch (c->cputype) { |
163 | case CPU_R3081: | |
164 | case CPU_R3081E: | |
165 | cpu_wait = r3081_wait; | |
1da177e4 LT |
166 | break; |
167 | case CPU_TX3927: | |
168 | cpu_wait = r39xx_wait; | |
1da177e4 LT |
169 | break; |
170 | case CPU_R4200: | |
171 | /* case CPU_R4300: */ | |
172 | case CPU_R4600: | |
173 | case CPU_R4640: | |
174 | case CPU_R4650: | |
175 | case CPU_R4700: | |
176 | case CPU_R5000: | |
a644b277 | 177 | case CPU_R5500: |
1da177e4 | 178 | case CPU_NEVADA: |
1da177e4 LT |
179 | case CPU_4KC: |
180 | case CPU_4KEC: | |
181 | case CPU_4KSC: | |
182 | case CPU_5KC: | |
1da177e4 | 183 | case CPU_25KF: |
4b3e975e | 184 | case CPU_PR4450: |
602977b0 KC |
185 | case CPU_BMIPS3300: |
186 | case CPU_BMIPS4350: | |
187 | case CPU_BMIPS4380: | |
188 | case CPU_BMIPS5000: | |
0dd4781b | 189 | case CPU_CAVIUM_OCTEON: |
6f329468 | 190 | case CPU_CAVIUM_OCTEON_PLUS: |
0e56b385 | 191 | case CPU_CAVIUM_OCTEON2: |
83ccf69d | 192 | case CPU_JZRISC: |
2fa36399 | 193 | case CPU_LOONGSON1: |
11d48aac | 194 | case CPU_XLR: |
a3d4fb2d | 195 | case CPU_XLP: |
4b3e975e RB |
196 | cpu_wait = r4k_wait; |
197 | break; | |
198 | ||
5a812999 RB |
199 | case CPU_RM7000: |
200 | cpu_wait = rm7k_wait_irqoff; | |
201 | break; | |
202 | ||
113c62d9 | 203 | case CPU_M14KC: |
f8fa4811 | 204 | case CPU_M14KEC: |
4b3e975e | 205 | case CPU_24K: |
bbc7f22f | 206 | case CPU_34K: |
39b8d525 | 207 | case CPU_1004K: |
4b3e975e RB |
208 | cpu_wait = r4k_wait; |
209 | if (read_c0_config7() & MIPS_CONF7_WII) | |
210 | cpu_wait = r4k_wait_irqoff; | |
211 | break; | |
212 | ||
c620953c | 213 | case CPU_74K: |
1da177e4 | 214 | cpu_wait = r4k_wait; |
4b3e975e RB |
215 | if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) |
216 | cpu_wait = r4k_wait_irqoff; | |
1da177e4 | 217 | break; |
4b3e975e | 218 | |
60a6c377 AN |
219 | case CPU_TX49XX: |
220 | cpu_wait = r4k_wait_irqoff; | |
60a6c377 | 221 | break; |
270717a8 | 222 | case CPU_ALCHEMY: |
0c694de1 | 223 | cpu_wait = au1k_wait; |
1da177e4 | 224 | break; |
c8eae71d RB |
225 | case CPU_20KC: |
226 | /* | |
227 | * WAIT on Rev1.0 has E1, E2, E3 and E16. | |
228 | * WAIT on Rev2.0 and Rev3.0 has E16. | |
229 | * Rev3.1 WAIT is nop, why bother | |
230 | */ | |
231 | if ((c->processor_id & 0xff) <= 0x64) | |
232 | break; | |
233 | ||
50da469a RB |
234 | /* |
235 | * Another rev is incremeting c0_count at a reduced clock | |
236 | * rate while in WAIT mode. So we basically have the choice | |
237 | * between using the cp0 timer as clocksource or avoiding | |
238 | * the WAIT instruction. Until more details are known, | |
239 | * disable the use of WAIT for 20Kc entirely. | |
240 | cpu_wait = r4k_wait; | |
241 | */ | |
c8eae71d | 242 | break; |
441ee341 | 243 | case CPU_RM9000: |
c2379230 | 244 | if ((c->processor_id & 0x00ff) >= 0x40) |
441ee341 | 245 | cpu_wait = r4k_wait; |
441ee341 | 246 | break; |
1da177e4 | 247 | default: |
1da177e4 LT |
248 | break; |
249 | } | |
250 | } | |
251 | ||
9267a30d MSJ |
252 | static inline void check_errata(void) |
253 | { | |
254 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
255 | ||
256 | switch (c->cputype) { | |
257 | case CPU_34K: | |
258 | /* | |
259 | * Erratum "RPS May Cause Incorrect Instruction Execution" | |
260 | * This code only handles VPE0, any SMP/SMTC/RTOS code | |
261 | * making use of VPE1 will be responsable for that VPE. | |
262 | */ | |
263 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) | |
264 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); | |
265 | break; | |
266 | default: | |
267 | break; | |
268 | } | |
269 | } | |
270 | ||
1da177e4 LT |
271 | void __init check_bugs32(void) |
272 | { | |
9267a30d | 273 | check_errata(); |
1da177e4 LT |
274 | } |
275 | ||
276 | /* | |
277 | * Probe whether cpu has config register by trying to play with | |
278 | * alternate cache bit and see whether it matters. | |
279 | * It's used by cpu_probe to distinguish between R3000A and R3081. | |
280 | */ | |
281 | static inline int cpu_has_confreg(void) | |
282 | { | |
283 | #ifdef CONFIG_CPU_R3000 | |
284 | extern unsigned long r3k_cache_size(unsigned long); | |
285 | unsigned long size1, size2; | |
286 | unsigned long cfg = read_c0_conf(); | |
287 | ||
288 | size1 = r3k_cache_size(ST0_ISC); | |
289 | write_c0_conf(cfg ^ R30XX_CONF_AC); | |
290 | size2 = r3k_cache_size(ST0_ISC); | |
291 | write_c0_conf(cfg); | |
292 | return size1 != size2; | |
293 | #else | |
294 | return 0; | |
295 | #endif | |
296 | } | |
297 | ||
c094c99e RM |
298 | static inline void set_elf_platform(int cpu, const char *plat) |
299 | { | |
300 | if (cpu == 0) | |
301 | __elf_platform = plat; | |
302 | } | |
303 | ||
1da177e4 LT |
304 | /* |
305 | * Get the FPU Implementation/Revision. | |
306 | */ | |
307 | static inline unsigned long cpu_get_fpu_id(void) | |
308 | { | |
309 | unsigned long tmp, fpu_id; | |
310 | ||
311 | tmp = read_c0_status(); | |
312 | __enable_fpu(); | |
313 | fpu_id = read_32bit_cp1_register(CP1_REVISION); | |
314 | write_c0_status(tmp); | |
315 | return fpu_id; | |
316 | } | |
317 | ||
318 | /* | |
319 | * Check the CPU has an FPU the official way. | |
320 | */ | |
321 | static inline int __cpu_has_fpu(void) | |
322 | { | |
323 | return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); | |
324 | } | |
325 | ||
91dfc423 GR |
326 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) |
327 | { | |
328 | #ifdef __NEED_VMBITS_PROBE | |
5b7efa89 | 329 | write_c0_entryhi(0x3fffffffffffe000ULL); |
91dfc423 | 330 | back_to_back_c0_hazard(); |
5b7efa89 | 331 | c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); |
91dfc423 GR |
332 | #endif |
333 | } | |
334 | ||
a96102be SH |
335 | static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa) |
336 | { | |
337 | switch (isa) { | |
338 | case MIPS_CPU_ISA_M64R2: | |
339 | c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; | |
340 | case MIPS_CPU_ISA_M64R1: | |
341 | c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; | |
342 | case MIPS_CPU_ISA_V: | |
343 | c->isa_level |= MIPS_CPU_ISA_V; | |
344 | case MIPS_CPU_ISA_IV: | |
345 | c->isa_level |= MIPS_CPU_ISA_IV; | |
346 | case MIPS_CPU_ISA_III: | |
347 | c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | | |
348 | MIPS_CPU_ISA_III; | |
349 | break; | |
350 | ||
351 | case MIPS_CPU_ISA_M32R2: | |
352 | c->isa_level |= MIPS_CPU_ISA_M32R2; | |
353 | case MIPS_CPU_ISA_M32R1: | |
354 | c->isa_level |= MIPS_CPU_ISA_M32R1; | |
355 | case MIPS_CPU_ISA_II: | |
356 | c->isa_level |= MIPS_CPU_ISA_II; | |
357 | case MIPS_CPU_ISA_I: | |
358 | c->isa_level |= MIPS_CPU_ISA_I; | |
359 | break; | |
360 | } | |
361 | } | |
362 | ||
2fa36399 KC |
363 | static char unknown_isa[] __cpuinitdata = KERN_ERR \ |
364 | "Unsupported ISA type, c0.config0: %d."; | |
365 | ||
366 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) | |
367 | { | |
368 | unsigned int config0; | |
369 | int isa; | |
370 | ||
371 | config0 = read_c0_config(); | |
372 | ||
373 | if (((config0 & MIPS_CONF_MT) >> 7) == 1) | |
374 | c->options |= MIPS_CPU_TLB; | |
375 | isa = (config0 & MIPS_CONF_AT) >> 13; | |
376 | switch (isa) { | |
377 | case 0: | |
378 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
379 | case 0: | |
a96102be | 380 | set_isa(c, MIPS_CPU_ISA_M32R1); |
2fa36399 KC |
381 | break; |
382 | case 1: | |
a96102be | 383 | set_isa(c, MIPS_CPU_ISA_M32R2); |
2fa36399 KC |
384 | break; |
385 | default: | |
386 | goto unknown; | |
387 | } | |
388 | break; | |
389 | case 2: | |
390 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
391 | case 0: | |
a96102be | 392 | set_isa(c, MIPS_CPU_ISA_M64R1); |
2fa36399 KC |
393 | break; |
394 | case 1: | |
a96102be | 395 | set_isa(c, MIPS_CPU_ISA_M64R2); |
2fa36399 KC |
396 | break; |
397 | default: | |
398 | goto unknown; | |
399 | } | |
400 | break; | |
401 | default: | |
402 | goto unknown; | |
403 | } | |
404 | ||
405 | return config0 & MIPS_CONF_M; | |
406 | ||
407 | unknown: | |
408 | panic(unknown_isa, config0); | |
409 | } | |
410 | ||
411 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) | |
412 | { | |
413 | unsigned int config1; | |
414 | ||
415 | config1 = read_c0_config1(); | |
416 | ||
417 | if (config1 & MIPS_CONF1_MD) | |
418 | c->ases |= MIPS_ASE_MDMX; | |
419 | if (config1 & MIPS_CONF1_WR) | |
420 | c->options |= MIPS_CPU_WATCH; | |
421 | if (config1 & MIPS_CONF1_CA) | |
422 | c->ases |= MIPS_ASE_MIPS16; | |
423 | if (config1 & MIPS_CONF1_EP) | |
424 | c->options |= MIPS_CPU_EJTAG; | |
425 | if (config1 & MIPS_CONF1_FP) { | |
426 | c->options |= MIPS_CPU_FPU; | |
427 | c->options |= MIPS_CPU_32FPR; | |
428 | } | |
429 | if (cpu_has_tlb) | |
430 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; | |
431 | ||
432 | return config1 & MIPS_CONF_M; | |
433 | } | |
434 | ||
435 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) | |
436 | { | |
437 | unsigned int config2; | |
438 | ||
439 | config2 = read_c0_config2(); | |
440 | ||
441 | if (config2 & MIPS_CONF2_SL) | |
442 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | |
443 | ||
444 | return config2 & MIPS_CONF_M; | |
445 | } | |
446 | ||
447 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) | |
448 | { | |
449 | unsigned int config3; | |
450 | ||
451 | config3 = read_c0_config3(); | |
452 | ||
b2ab4f08 | 453 | if (config3 & MIPS_CONF3_SM) { |
2fa36399 | 454 | c->ases |= MIPS_ASE_SMARTMIPS; |
b2ab4f08 SH |
455 | c->options |= MIPS_CPU_RIXI; |
456 | } | |
457 | if (config3 & MIPS_CONF3_RXI) | |
458 | c->options |= MIPS_CPU_RIXI; | |
2fa36399 KC |
459 | if (config3 & MIPS_CONF3_DSP) |
460 | c->ases |= MIPS_ASE_DSP; | |
ee80f7c7 SH |
461 | if (config3 & MIPS_CONF3_DSP2P) |
462 | c->ases |= MIPS_ASE_DSP2P; | |
2fa36399 KC |
463 | if (config3 & MIPS_CONF3_VINT) |
464 | c->options |= MIPS_CPU_VINT; | |
465 | if (config3 & MIPS_CONF3_VEIC) | |
466 | c->options |= MIPS_CPU_VEIC; | |
467 | if (config3 & MIPS_CONF3_MT) | |
468 | c->ases |= MIPS_ASE_MIPSMT; | |
469 | if (config3 & MIPS_CONF3_ULRI) | |
470 | c->options |= MIPS_CPU_ULRI; | |
f8fa4811 SH |
471 | if (config3 & MIPS_CONF3_ISA) |
472 | c->options |= MIPS_CPU_MICROMIPS; | |
1e7decdb DD |
473 | if (config3 & MIPS_CONF3_VZ) |
474 | c->ases |= MIPS_ASE_VZ; | |
2fa36399 KC |
475 | |
476 | return config3 & MIPS_CONF_M; | |
477 | } | |
478 | ||
479 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) | |
480 | { | |
481 | unsigned int config4; | |
482 | ||
483 | config4 = read_c0_config4(); | |
484 | ||
485 | if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT | |
486 | && cpu_has_tlb) | |
487 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; | |
488 | ||
489 | c->kscratch_mask = (config4 >> 16) & 0xff; | |
490 | ||
491 | return config4 & MIPS_CONF_M; | |
492 | } | |
493 | ||
494 | static void __cpuinit decode_configs(struct cpuinfo_mips *c) | |
495 | { | |
496 | int ok; | |
497 | ||
498 | /* MIPS32 or MIPS64 compliant CPU. */ | |
499 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | | |
500 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; | |
501 | ||
502 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; | |
503 | ||
504 | ok = decode_config0(c); /* Read Config registers. */ | |
70342287 | 505 | BUG_ON(!ok); /* Arch spec violation! */ |
2fa36399 KC |
506 | if (ok) |
507 | ok = decode_config1(c); | |
508 | if (ok) | |
509 | ok = decode_config2(c); | |
510 | if (ok) | |
511 | ok = decode_config3(c); | |
512 | if (ok) | |
513 | ok = decode_config4(c); | |
514 | ||
515 | mips_probe_watch_registers(c); | |
516 | ||
517 | if (cpu_has_mips_r2) | |
518 | c->core = read_c0_ebase() & 0x3ff; | |
519 | } | |
520 | ||
02cf2119 | 521 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
1da177e4 LT |
522 | | MIPS_CPU_COUNTER) |
523 | ||
cea7e2df | 524 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 LT |
525 | { |
526 | switch (c->processor_id & 0xff00) { | |
527 | case PRID_IMP_R2000: | |
528 | c->cputype = CPU_R2000; | |
cea7e2df | 529 | __cpu_name[cpu] = "R2000"; |
a96102be | 530 | set_isa(c, MIPS_CPU_ISA_I); |
02cf2119 | 531 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
03751e79 | 532 | MIPS_CPU_NOFPUEX; |
1da177e4 LT |
533 | if (__cpu_has_fpu()) |
534 | c->options |= MIPS_CPU_FPU; | |
535 | c->tlbsize = 64; | |
536 | break; | |
537 | case PRID_IMP_R3000: | |
cea7e2df RB |
538 | if ((c->processor_id & 0xff) == PRID_REV_R3000A) { |
539 | if (cpu_has_confreg()) { | |
1da177e4 | 540 | c->cputype = CPU_R3081E; |
cea7e2df RB |
541 | __cpu_name[cpu] = "R3081"; |
542 | } else { | |
1da177e4 | 543 | c->cputype = CPU_R3000A; |
cea7e2df RB |
544 | __cpu_name[cpu] = "R3000A"; |
545 | } | |
cea7e2df | 546 | } else { |
1da177e4 | 547 | c->cputype = CPU_R3000; |
cea7e2df RB |
548 | __cpu_name[cpu] = "R3000"; |
549 | } | |
a96102be | 550 | set_isa(c, MIPS_CPU_ISA_I); |
02cf2119 | 551 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
03751e79 | 552 | MIPS_CPU_NOFPUEX; |
1da177e4 LT |
553 | if (__cpu_has_fpu()) |
554 | c->options |= MIPS_CPU_FPU; | |
555 | c->tlbsize = 64; | |
556 | break; | |
557 | case PRID_IMP_R4000: | |
558 | if (read_c0_config() & CONF_SC) { | |
cea7e2df | 559 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) { |
1da177e4 | 560 | c->cputype = CPU_R4400PC; |
cea7e2df RB |
561 | __cpu_name[cpu] = "R4400PC"; |
562 | } else { | |
1da177e4 | 563 | c->cputype = CPU_R4000PC; |
cea7e2df RB |
564 | __cpu_name[cpu] = "R4000PC"; |
565 | } | |
1da177e4 | 566 | } else { |
cea7e2df | 567 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) { |
1da177e4 | 568 | c->cputype = CPU_R4400SC; |
cea7e2df RB |
569 | __cpu_name[cpu] = "R4400SC"; |
570 | } else { | |
1da177e4 | 571 | c->cputype = CPU_R4000SC; |
cea7e2df RB |
572 | __cpu_name[cpu] = "R4000SC"; |
573 | } | |
1da177e4 LT |
574 | } |
575 | ||
a96102be | 576 | set_isa(c, MIPS_CPU_ISA_III); |
1da177e4 | 577 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 SH |
578 | MIPS_CPU_WATCH | MIPS_CPU_VCE | |
579 | MIPS_CPU_LLSC; | |
1da177e4 LT |
580 | c->tlbsize = 48; |
581 | break; | |
582 | case PRID_IMP_VR41XX: | |
9f91e506 YY |
583 | set_isa(c, MIPS_CPU_ISA_III); |
584 | c->options = R4K_OPTS; | |
585 | c->tlbsize = 32; | |
1da177e4 | 586 | switch (c->processor_id & 0xf0) { |
1da177e4 LT |
587 | case PRID_REV_VR4111: |
588 | c->cputype = CPU_VR4111; | |
cea7e2df | 589 | __cpu_name[cpu] = "NEC VR4111"; |
1da177e4 | 590 | break; |
1da177e4 LT |
591 | case PRID_REV_VR4121: |
592 | c->cputype = CPU_VR4121; | |
cea7e2df | 593 | __cpu_name[cpu] = "NEC VR4121"; |
1da177e4 LT |
594 | break; |
595 | case PRID_REV_VR4122: | |
cea7e2df | 596 | if ((c->processor_id & 0xf) < 0x3) { |
1da177e4 | 597 | c->cputype = CPU_VR4122; |
cea7e2df RB |
598 | __cpu_name[cpu] = "NEC VR4122"; |
599 | } else { | |
1da177e4 | 600 | c->cputype = CPU_VR4181A; |
cea7e2df RB |
601 | __cpu_name[cpu] = "NEC VR4181A"; |
602 | } | |
1da177e4 LT |
603 | break; |
604 | case PRID_REV_VR4130: | |
cea7e2df | 605 | if ((c->processor_id & 0xf) < 0x4) { |
1da177e4 | 606 | c->cputype = CPU_VR4131; |
cea7e2df RB |
607 | __cpu_name[cpu] = "NEC VR4131"; |
608 | } else { | |
1da177e4 | 609 | c->cputype = CPU_VR4133; |
9f91e506 | 610 | c->options |= MIPS_CPU_LLSC; |
cea7e2df RB |
611 | __cpu_name[cpu] = "NEC VR4133"; |
612 | } | |
1da177e4 LT |
613 | break; |
614 | default: | |
615 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); | |
616 | c->cputype = CPU_VR41XX; | |
cea7e2df | 617 | __cpu_name[cpu] = "NEC Vr41xx"; |
1da177e4 LT |
618 | break; |
619 | } | |
1da177e4 LT |
620 | break; |
621 | case PRID_IMP_R4300: | |
622 | c->cputype = CPU_R4300; | |
cea7e2df | 623 | __cpu_name[cpu] = "R4300"; |
a96102be | 624 | set_isa(c, MIPS_CPU_ISA_III); |
1da177e4 | 625 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 626 | MIPS_CPU_LLSC; |
1da177e4 LT |
627 | c->tlbsize = 32; |
628 | break; | |
629 | case PRID_IMP_R4600: | |
630 | c->cputype = CPU_R4600; | |
cea7e2df | 631 | __cpu_name[cpu] = "R4600"; |
a96102be | 632 | set_isa(c, MIPS_CPU_ISA_III); |
075e7502 TS |
633 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
634 | MIPS_CPU_LLSC; | |
1da177e4 LT |
635 | c->tlbsize = 48; |
636 | break; | |
637 | #if 0 | |
03751e79 | 638 | case PRID_IMP_R4650: |
1da177e4 LT |
639 | /* |
640 | * This processor doesn't have an MMU, so it's not | |
641 | * "real easy" to run Linux on it. It is left purely | |
642 | * for documentation. Commented out because it shares | |
643 | * it's c0_prid id number with the TX3900. | |
644 | */ | |
a3dddd56 | 645 | c->cputype = CPU_R4650; |
cea7e2df | 646 | __cpu_name[cpu] = "R4650"; |
a96102be | 647 | set_isa(c, MIPS_CPU_ISA_III); |
1da177e4 | 648 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; |
03751e79 | 649 | c->tlbsize = 48; |
1da177e4 LT |
650 | break; |
651 | #endif | |
652 | case PRID_IMP_TX39: | |
a96102be | 653 | set_isa(c, MIPS_CPU_ISA_I); |
02cf2119 | 654 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
1da177e4 LT |
655 | |
656 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { | |
657 | c->cputype = CPU_TX3927; | |
cea7e2df | 658 | __cpu_name[cpu] = "TX3927"; |
1da177e4 LT |
659 | c->tlbsize = 64; |
660 | } else { | |
661 | switch (c->processor_id & 0xff) { | |
662 | case PRID_REV_TX3912: | |
663 | c->cputype = CPU_TX3912; | |
cea7e2df | 664 | __cpu_name[cpu] = "TX3912"; |
1da177e4 LT |
665 | c->tlbsize = 32; |
666 | break; | |
667 | case PRID_REV_TX3922: | |
668 | c->cputype = CPU_TX3922; | |
cea7e2df | 669 | __cpu_name[cpu] = "TX3922"; |
1da177e4 LT |
670 | c->tlbsize = 64; |
671 | break; | |
1da177e4 LT |
672 | } |
673 | } | |
674 | break; | |
675 | case PRID_IMP_R4700: | |
676 | c->cputype = CPU_R4700; | |
cea7e2df | 677 | __cpu_name[cpu] = "R4700"; |
a96102be | 678 | set_isa(c, MIPS_CPU_ISA_III); |
1da177e4 | 679 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 680 | MIPS_CPU_LLSC; |
1da177e4 LT |
681 | c->tlbsize = 48; |
682 | break; | |
683 | case PRID_IMP_TX49: | |
684 | c->cputype = CPU_TX49XX; | |
cea7e2df | 685 | __cpu_name[cpu] = "R49XX"; |
a96102be | 686 | set_isa(c, MIPS_CPU_ISA_III); |
1da177e4 LT |
687 | c->options = R4K_OPTS | MIPS_CPU_LLSC; |
688 | if (!(c->processor_id & 0x08)) | |
689 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; | |
690 | c->tlbsize = 48; | |
691 | break; | |
692 | case PRID_IMP_R5000: | |
693 | c->cputype = CPU_R5000; | |
cea7e2df | 694 | __cpu_name[cpu] = "R5000"; |
a96102be | 695 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 696 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 697 | MIPS_CPU_LLSC; |
1da177e4 LT |
698 | c->tlbsize = 48; |
699 | break; | |
700 | case PRID_IMP_R5432: | |
701 | c->cputype = CPU_R5432; | |
cea7e2df | 702 | __cpu_name[cpu] = "R5432"; |
a96102be | 703 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 704 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 705 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
1da177e4 LT |
706 | c->tlbsize = 48; |
707 | break; | |
708 | case PRID_IMP_R5500: | |
709 | c->cputype = CPU_R5500; | |
cea7e2df | 710 | __cpu_name[cpu] = "R5500"; |
a96102be | 711 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 712 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 713 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
1da177e4 LT |
714 | c->tlbsize = 48; |
715 | break; | |
716 | case PRID_IMP_NEVADA: | |
717 | c->cputype = CPU_NEVADA; | |
cea7e2df | 718 | __cpu_name[cpu] = "Nevada"; |
a96102be | 719 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 720 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 721 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; |
1da177e4 LT |
722 | c->tlbsize = 48; |
723 | break; | |
724 | case PRID_IMP_R6000: | |
725 | c->cputype = CPU_R6000; | |
cea7e2df | 726 | __cpu_name[cpu] = "R6000"; |
a96102be | 727 | set_isa(c, MIPS_CPU_ISA_II); |
1da177e4 | 728 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
03751e79 | 729 | MIPS_CPU_LLSC; |
1da177e4 LT |
730 | c->tlbsize = 32; |
731 | break; | |
732 | case PRID_IMP_R6000A: | |
733 | c->cputype = CPU_R6000A; | |
cea7e2df | 734 | __cpu_name[cpu] = "R6000A"; |
a96102be | 735 | set_isa(c, MIPS_CPU_ISA_II); |
1da177e4 | 736 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
03751e79 | 737 | MIPS_CPU_LLSC; |
1da177e4 LT |
738 | c->tlbsize = 32; |
739 | break; | |
740 | case PRID_IMP_RM7000: | |
741 | c->cputype = CPU_RM7000; | |
cea7e2df | 742 | __cpu_name[cpu] = "RM7000"; |
a96102be | 743 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 744 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 745 | MIPS_CPU_LLSC; |
1da177e4 | 746 | /* |
70342287 | 747 | * Undocumented RM7000: Bit 29 in the info register of |
1da177e4 LT |
748 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 |
749 | * entries. | |
750 | * | |
70342287 RB |
751 | * 29 1 => 64 entry JTLB |
752 | * 0 => 48 entry JTLB | |
1da177e4 LT |
753 | */ |
754 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
755 | break; | |
756 | case PRID_IMP_RM9000: | |
757 | c->cputype = CPU_RM9000; | |
cea7e2df | 758 | __cpu_name[cpu] = "RM9000"; |
a96102be | 759 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 760 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 761 | MIPS_CPU_LLSC; |
1da177e4 LT |
762 | /* |
763 | * Bit 29 in the info register of the RM9000 | |
764 | * indicates if the TLB has 48 or 64 entries. | |
765 | * | |
70342287 RB |
766 | * 29 1 => 64 entry JTLB |
767 | * 0 => 48 entry JTLB | |
1da177e4 LT |
768 | */ |
769 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
770 | break; | |
771 | case PRID_IMP_R8000: | |
772 | c->cputype = CPU_R8000; | |
cea7e2df | 773 | __cpu_name[cpu] = "RM8000"; |
a96102be | 774 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 775 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | |
03751e79 SH |
776 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
777 | MIPS_CPU_LLSC; | |
1da177e4 LT |
778 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ |
779 | break; | |
780 | case PRID_IMP_R10000: | |
781 | c->cputype = CPU_R10000; | |
cea7e2df | 782 | __cpu_name[cpu] = "R10000"; |
a96102be | 783 | set_isa(c, MIPS_CPU_ISA_IV); |
8b36612a | 784 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 785 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1da177e4 | 786 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
03751e79 | 787 | MIPS_CPU_LLSC; |
1da177e4 LT |
788 | c->tlbsize = 64; |
789 | break; | |
790 | case PRID_IMP_R12000: | |
791 | c->cputype = CPU_R12000; | |
cea7e2df | 792 | __cpu_name[cpu] = "R12000"; |
a96102be | 793 | set_isa(c, MIPS_CPU_ISA_IV); |
8b36612a | 794 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 795 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1da177e4 | 796 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
03751e79 | 797 | MIPS_CPU_LLSC; |
1da177e4 LT |
798 | c->tlbsize = 64; |
799 | break; | |
44d921b2 K |
800 | case PRID_IMP_R14000: |
801 | c->cputype = CPU_R14000; | |
cea7e2df | 802 | __cpu_name[cpu] = "R14000"; |
a96102be | 803 | set_isa(c, MIPS_CPU_ISA_IV); |
44d921b2 | 804 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 805 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
44d921b2 | 806 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
03751e79 | 807 | MIPS_CPU_LLSC; |
44d921b2 K |
808 | c->tlbsize = 64; |
809 | break; | |
2a21c730 FZ |
810 | case PRID_IMP_LOONGSON2: |
811 | c->cputype = CPU_LOONGSON2; | |
cea7e2df | 812 | __cpu_name[cpu] = "ICT Loongson-2"; |
5aac1e8a RM |
813 | |
814 | switch (c->processor_id & PRID_REV_MASK) { | |
815 | case PRID_REV_LOONGSON2E: | |
816 | set_elf_platform(cpu, "loongson2e"); | |
817 | break; | |
818 | case PRID_REV_LOONGSON2F: | |
819 | set_elf_platform(cpu, "loongson2f"); | |
820 | break; | |
821 | } | |
822 | ||
a96102be | 823 | set_isa(c, MIPS_CPU_ISA_III); |
2a21c730 FZ |
824 | c->options = R4K_OPTS | |
825 | MIPS_CPU_FPU | MIPS_CPU_LLSC | | |
826 | MIPS_CPU_32FPR; | |
827 | c->tlbsize = 64; | |
828 | break; | |
2fa36399 KC |
829 | case PRID_IMP_LOONGSON1: |
830 | decode_configs(c); | |
b4672d37 | 831 | |
2fa36399 | 832 | c->cputype = CPU_LOONGSON1; |
1da177e4 | 833 | |
2fa36399 KC |
834 | switch (c->processor_id & PRID_REV_MASK) { |
835 | case PRID_REV_LOONGSON1B: | |
836 | __cpu_name[cpu] = "Loongson 1B"; | |
b4672d37 | 837 | break; |
b4672d37 | 838 | } |
4194318c | 839 | |
2fa36399 | 840 | break; |
1da177e4 | 841 | } |
1da177e4 LT |
842 | } |
843 | ||
cea7e2df | 844 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 845 | { |
4194318c | 846 | decode_configs(c); |
1da177e4 LT |
847 | switch (c->processor_id & 0xff00) { |
848 | case PRID_IMP_4KC: | |
849 | c->cputype = CPU_4KC; | |
cea7e2df | 850 | __cpu_name[cpu] = "MIPS 4Kc"; |
1da177e4 LT |
851 | break; |
852 | case PRID_IMP_4KEC: | |
2b07bd02 RB |
853 | case PRID_IMP_4KECR2: |
854 | c->cputype = CPU_4KEC; | |
cea7e2df | 855 | __cpu_name[cpu] = "MIPS 4KEc"; |
2b07bd02 | 856 | break; |
1da177e4 | 857 | case PRID_IMP_4KSC: |
8afcb5d8 | 858 | case PRID_IMP_4KSD: |
1da177e4 | 859 | c->cputype = CPU_4KSC; |
cea7e2df | 860 | __cpu_name[cpu] = "MIPS 4KSc"; |
1da177e4 LT |
861 | break; |
862 | case PRID_IMP_5KC: | |
863 | c->cputype = CPU_5KC; | |
cea7e2df | 864 | __cpu_name[cpu] = "MIPS 5Kc"; |
1da177e4 | 865 | break; |
78d4803f LY |
866 | case PRID_IMP_5KE: |
867 | c->cputype = CPU_5KE; | |
868 | __cpu_name[cpu] = "MIPS 5KE"; | |
869 | break; | |
1da177e4 LT |
870 | case PRID_IMP_20KC: |
871 | c->cputype = CPU_20KC; | |
cea7e2df | 872 | __cpu_name[cpu] = "MIPS 20Kc"; |
1da177e4 LT |
873 | break; |
874 | case PRID_IMP_24K: | |
875 | c->cputype = CPU_24K; | |
cea7e2df | 876 | __cpu_name[cpu] = "MIPS 24Kc"; |
1da177e4 | 877 | break; |
42f3caef JC |
878 | case PRID_IMP_24KE: |
879 | c->cputype = CPU_24K; | |
880 | __cpu_name[cpu] = "MIPS 24KEc"; | |
881 | break; | |
1da177e4 LT |
882 | case PRID_IMP_25KF: |
883 | c->cputype = CPU_25KF; | |
cea7e2df | 884 | __cpu_name[cpu] = "MIPS 25Kc"; |
1da177e4 | 885 | break; |
bbc7f22f RB |
886 | case PRID_IMP_34K: |
887 | c->cputype = CPU_34K; | |
cea7e2df | 888 | __cpu_name[cpu] = "MIPS 34Kc"; |
bbc7f22f | 889 | break; |
c620953c CD |
890 | case PRID_IMP_74K: |
891 | c->cputype = CPU_74K; | |
cea7e2df | 892 | __cpu_name[cpu] = "MIPS 74Kc"; |
c620953c | 893 | break; |
113c62d9 SH |
894 | case PRID_IMP_M14KC: |
895 | c->cputype = CPU_M14KC; | |
896 | __cpu_name[cpu] = "MIPS M14Kc"; | |
897 | break; | |
f8fa4811 SH |
898 | case PRID_IMP_M14KEC: |
899 | c->cputype = CPU_M14KEC; | |
900 | __cpu_name[cpu] = "MIPS M14KEc"; | |
901 | break; | |
39b8d525 RB |
902 | case PRID_IMP_1004K: |
903 | c->cputype = CPU_1004K; | |
cea7e2df | 904 | __cpu_name[cpu] = "MIPS 1004Kc"; |
39b8d525 | 905 | break; |
006a851b SH |
906 | case PRID_IMP_1074K: |
907 | c->cputype = CPU_74K; | |
908 | __cpu_name[cpu] = "MIPS 1074Kc"; | |
909 | break; | |
1da177e4 | 910 | } |
0b6d497f CD |
911 | |
912 | spram_config(); | |
1da177e4 LT |
913 | } |
914 | ||
cea7e2df | 915 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 916 | { |
4194318c | 917 | decode_configs(c); |
1da177e4 LT |
918 | switch (c->processor_id & 0xff00) { |
919 | case PRID_IMP_AU1_REV1: | |
920 | case PRID_IMP_AU1_REV2: | |
270717a8 | 921 | c->cputype = CPU_ALCHEMY; |
1da177e4 LT |
922 | switch ((c->processor_id >> 24) & 0xff) { |
923 | case 0: | |
cea7e2df | 924 | __cpu_name[cpu] = "Au1000"; |
1da177e4 LT |
925 | break; |
926 | case 1: | |
cea7e2df | 927 | __cpu_name[cpu] = "Au1500"; |
1da177e4 LT |
928 | break; |
929 | case 2: | |
cea7e2df | 930 | __cpu_name[cpu] = "Au1100"; |
1da177e4 LT |
931 | break; |
932 | case 3: | |
cea7e2df | 933 | __cpu_name[cpu] = "Au1550"; |
1da177e4 | 934 | break; |
e3ad1c23 | 935 | case 4: |
cea7e2df | 936 | __cpu_name[cpu] = "Au1200"; |
270717a8 | 937 | if ((c->processor_id & 0xff) == 2) |
cea7e2df | 938 | __cpu_name[cpu] = "Au1250"; |
237cfee1 ML |
939 | break; |
940 | case 5: | |
cea7e2df | 941 | __cpu_name[cpu] = "Au1210"; |
e3ad1c23 | 942 | break; |
1da177e4 | 943 | default: |
270717a8 | 944 | __cpu_name[cpu] = "Au1xxx"; |
1da177e4 LT |
945 | break; |
946 | } | |
1da177e4 LT |
947 | break; |
948 | } | |
949 | } | |
950 | ||
cea7e2df | 951 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 952 | { |
4194318c | 953 | decode_configs(c); |
02cf2119 | 954 | |
1da177e4 LT |
955 | switch (c->processor_id & 0xff00) { |
956 | case PRID_IMP_SB1: | |
957 | c->cputype = CPU_SB1; | |
cea7e2df | 958 | __cpu_name[cpu] = "SiByte SB1"; |
1da177e4 | 959 | /* FPU in pass1 is known to have issues. */ |
aa32374a | 960 | if ((c->processor_id & 0xff) < 0x02) |
010b853b | 961 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
1da177e4 | 962 | break; |
93ce2f52 AI |
963 | case PRID_IMP_SB1A: |
964 | c->cputype = CPU_SB1A; | |
cea7e2df | 965 | __cpu_name[cpu] = "SiByte SB1A"; |
93ce2f52 | 966 | break; |
1da177e4 LT |
967 | } |
968 | } | |
969 | ||
cea7e2df | 970 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 971 | { |
4194318c | 972 | decode_configs(c); |
1da177e4 LT |
973 | switch (c->processor_id & 0xff00) { |
974 | case PRID_IMP_SR71000: | |
975 | c->cputype = CPU_SR71000; | |
cea7e2df | 976 | __cpu_name[cpu] = "Sandcraft SR71000"; |
1da177e4 LT |
977 | c->scache.ways = 8; |
978 | c->tlbsize = 64; | |
979 | break; | |
980 | } | |
981 | } | |
982 | ||
cea7e2df | 983 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
bdf21b18 PP |
984 | { |
985 | decode_configs(c); | |
986 | switch (c->processor_id & 0xff00) { | |
987 | case PRID_IMP_PR4450: | |
988 | c->cputype = CPU_PR4450; | |
cea7e2df | 989 | __cpu_name[cpu] = "Philips PR4450"; |
a96102be | 990 | set_isa(c, MIPS_CPU_ISA_M32R1); |
bdf21b18 | 991 | break; |
bdf21b18 PP |
992 | } |
993 | } | |
994 | ||
cea7e2df | 995 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
1c0c13eb AJ |
996 | { |
997 | decode_configs(c); | |
998 | switch (c->processor_id & 0xff00) { | |
190fca3e KC |
999 | case PRID_IMP_BMIPS32_REV4: |
1000 | case PRID_IMP_BMIPS32_REV8: | |
602977b0 KC |
1001 | c->cputype = CPU_BMIPS32; |
1002 | __cpu_name[cpu] = "Broadcom BMIPS32"; | |
06785df0 | 1003 | set_elf_platform(cpu, "bmips32"); |
602977b0 KC |
1004 | break; |
1005 | case PRID_IMP_BMIPS3300: | |
1006 | case PRID_IMP_BMIPS3300_ALT: | |
1007 | case PRID_IMP_BMIPS3300_BUG: | |
1008 | c->cputype = CPU_BMIPS3300; | |
1009 | __cpu_name[cpu] = "Broadcom BMIPS3300"; | |
06785df0 | 1010 | set_elf_platform(cpu, "bmips3300"); |
602977b0 KC |
1011 | break; |
1012 | case PRID_IMP_BMIPS43XX: { | |
1013 | int rev = c->processor_id & 0xff; | |
1014 | ||
1015 | if (rev >= PRID_REV_BMIPS4380_LO && | |
1016 | rev <= PRID_REV_BMIPS4380_HI) { | |
1017 | c->cputype = CPU_BMIPS4380; | |
1018 | __cpu_name[cpu] = "Broadcom BMIPS4380"; | |
06785df0 | 1019 | set_elf_platform(cpu, "bmips4380"); |
602977b0 KC |
1020 | } else { |
1021 | c->cputype = CPU_BMIPS4350; | |
1022 | __cpu_name[cpu] = "Broadcom BMIPS4350"; | |
06785df0 | 1023 | set_elf_platform(cpu, "bmips4350"); |
602977b0 | 1024 | } |
0de663ef | 1025 | break; |
602977b0 KC |
1026 | } |
1027 | case PRID_IMP_BMIPS5000: | |
1028 | c->cputype = CPU_BMIPS5000; | |
1029 | __cpu_name[cpu] = "Broadcom BMIPS5000"; | |
06785df0 | 1030 | set_elf_platform(cpu, "bmips5000"); |
602977b0 | 1031 | c->options |= MIPS_CPU_ULRI; |
0de663ef | 1032 | break; |
1c0c13eb AJ |
1033 | } |
1034 | } | |
1035 | ||
0dd4781b DD |
1036 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
1037 | { | |
1038 | decode_configs(c); | |
1039 | switch (c->processor_id & 0xff00) { | |
1040 | case PRID_IMP_CAVIUM_CN38XX: | |
1041 | case PRID_IMP_CAVIUM_CN31XX: | |
1042 | case PRID_IMP_CAVIUM_CN30XX: | |
6f329468 DD |
1043 | c->cputype = CPU_CAVIUM_OCTEON; |
1044 | __cpu_name[cpu] = "Cavium Octeon"; | |
1045 | goto platform; | |
0dd4781b DD |
1046 | case PRID_IMP_CAVIUM_CN58XX: |
1047 | case PRID_IMP_CAVIUM_CN56XX: | |
1048 | case PRID_IMP_CAVIUM_CN50XX: | |
1049 | case PRID_IMP_CAVIUM_CN52XX: | |
6f329468 DD |
1050 | c->cputype = CPU_CAVIUM_OCTEON_PLUS; |
1051 | __cpu_name[cpu] = "Cavium Octeon+"; | |
1052 | platform: | |
c094c99e | 1053 | set_elf_platform(cpu, "octeon"); |
0dd4781b | 1054 | break; |
a1431b61 | 1055 | case PRID_IMP_CAVIUM_CN61XX: |
0e56b385 | 1056 | case PRID_IMP_CAVIUM_CN63XX: |
a1431b61 DD |
1057 | case PRID_IMP_CAVIUM_CN66XX: |
1058 | case PRID_IMP_CAVIUM_CN68XX: | |
0e56b385 DD |
1059 | c->cputype = CPU_CAVIUM_OCTEON2; |
1060 | __cpu_name[cpu] = "Cavium Octeon II"; | |
c094c99e | 1061 | set_elf_platform(cpu, "octeon2"); |
0e56b385 | 1062 | break; |
0dd4781b DD |
1063 | default: |
1064 | printk(KERN_INFO "Unknown Octeon chip!\n"); | |
1065 | c->cputype = CPU_UNKNOWN; | |
1066 | break; | |
1067 | } | |
1068 | } | |
1069 | ||
83ccf69d LPC |
1070 | static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) |
1071 | { | |
1072 | decode_configs(c); | |
1073 | /* JZRISC does not implement the CP0 counter. */ | |
1074 | c->options &= ~MIPS_CPU_COUNTER; | |
1075 | switch (c->processor_id & 0xff00) { | |
1076 | case PRID_IMP_JZRISC: | |
1077 | c->cputype = CPU_JZRISC; | |
1078 | __cpu_name[cpu] = "Ingenic JZRISC"; | |
1079 | break; | |
1080 | default: | |
1081 | panic("Unknown Ingenic Processor ID!"); | |
1082 | break; | |
1083 | } | |
1084 | } | |
1085 | ||
a7117c6b J |
1086 | static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) |
1087 | { | |
1088 | decode_configs(c); | |
1089 | ||
809f36c6 ML |
1090 | if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) { |
1091 | c->cputype = CPU_ALCHEMY; | |
1092 | __cpu_name[cpu] = "Au1300"; | |
1093 | /* following stuff is not for Alchemy */ | |
1094 | return; | |
1095 | } | |
1096 | ||
70342287 RB |
1097 | c->options = (MIPS_CPU_TLB | |
1098 | MIPS_CPU_4KEX | | |
a7117c6b | 1099 | MIPS_CPU_COUNTER | |
70342287 RB |
1100 | MIPS_CPU_DIVEC | |
1101 | MIPS_CPU_WATCH | | |
1102 | MIPS_CPU_EJTAG | | |
a7117c6b J |
1103 | MIPS_CPU_LLSC); |
1104 | ||
1105 | switch (c->processor_id & 0xff00) { | |
2aa54b20 J |
1106 | case PRID_IMP_NETLOGIC_XLP8XX: |
1107 | case PRID_IMP_NETLOGIC_XLP3XX: | |
a3d4fb2d J |
1108 | c->cputype = CPU_XLP; |
1109 | __cpu_name[cpu] = "Netlogic XLP"; | |
1110 | break; | |
1111 | ||
a7117c6b J |
1112 | case PRID_IMP_NETLOGIC_XLR732: |
1113 | case PRID_IMP_NETLOGIC_XLR716: | |
1114 | case PRID_IMP_NETLOGIC_XLR532: | |
1115 | case PRID_IMP_NETLOGIC_XLR308: | |
1116 | case PRID_IMP_NETLOGIC_XLR532C: | |
1117 | case PRID_IMP_NETLOGIC_XLR516C: | |
1118 | case PRID_IMP_NETLOGIC_XLR508C: | |
1119 | case PRID_IMP_NETLOGIC_XLR308C: | |
1120 | c->cputype = CPU_XLR; | |
1121 | __cpu_name[cpu] = "Netlogic XLR"; | |
1122 | break; | |
1123 | ||
1124 | case PRID_IMP_NETLOGIC_XLS608: | |
1125 | case PRID_IMP_NETLOGIC_XLS408: | |
1126 | case PRID_IMP_NETLOGIC_XLS404: | |
1127 | case PRID_IMP_NETLOGIC_XLS208: | |
1128 | case PRID_IMP_NETLOGIC_XLS204: | |
1129 | case PRID_IMP_NETLOGIC_XLS108: | |
1130 | case PRID_IMP_NETLOGIC_XLS104: | |
1131 | case PRID_IMP_NETLOGIC_XLS616B: | |
1132 | case PRID_IMP_NETLOGIC_XLS608B: | |
1133 | case PRID_IMP_NETLOGIC_XLS416B: | |
1134 | case PRID_IMP_NETLOGIC_XLS412B: | |
1135 | case PRID_IMP_NETLOGIC_XLS408B: | |
1136 | case PRID_IMP_NETLOGIC_XLS404B: | |
1137 | c->cputype = CPU_XLR; | |
1138 | __cpu_name[cpu] = "Netlogic XLS"; | |
1139 | break; | |
1140 | ||
1141 | default: | |
a3d4fb2d | 1142 | pr_info("Unknown Netlogic chip id [%02x]!\n", |
a7117c6b J |
1143 | c->processor_id); |
1144 | c->cputype = CPU_XLR; | |
1145 | break; | |
1146 | } | |
1147 | ||
a3d4fb2d | 1148 | if (c->cputype == CPU_XLP) { |
a96102be | 1149 | set_isa(c, MIPS_CPU_ISA_M64R2); |
a3d4fb2d J |
1150 | c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); |
1151 | /* This will be updated again after all threads are woken up */ | |
1152 | c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; | |
1153 | } else { | |
a96102be | 1154 | set_isa(c, MIPS_CPU_ISA_M64R1); |
a3d4fb2d J |
1155 | c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; |
1156 | } | |
a7117c6b J |
1157 | } |
1158 | ||
949e51be DD |
1159 | #ifdef CONFIG_64BIT |
1160 | /* For use by uaccess.h */ | |
1161 | u64 __ua_limit; | |
1162 | EXPORT_SYMBOL(__ua_limit); | |
1163 | #endif | |
1164 | ||
9966db25 | 1165 | const char *__cpu_name[NR_CPUS]; |
874fd3b5 | 1166 | const char *__elf_platform; |
9966db25 | 1167 | |
234fcd14 | 1168 | __cpuinit void cpu_probe(void) |
1da177e4 LT |
1169 | { |
1170 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
9966db25 | 1171 | unsigned int cpu = smp_processor_id(); |
1da177e4 | 1172 | |
70342287 | 1173 | c->processor_id = PRID_IMP_UNKNOWN; |
1da177e4 LT |
1174 | c->fpu_id = FPIR_IMP_NONE; |
1175 | c->cputype = CPU_UNKNOWN; | |
1176 | ||
1177 | c->processor_id = read_c0_prid(); | |
1178 | switch (c->processor_id & 0xff0000) { | |
1179 | case PRID_COMP_LEGACY: | |
cea7e2df | 1180 | cpu_probe_legacy(c, cpu); |
1da177e4 LT |
1181 | break; |
1182 | case PRID_COMP_MIPS: | |
cea7e2df | 1183 | cpu_probe_mips(c, cpu); |
1da177e4 LT |
1184 | break; |
1185 | case PRID_COMP_ALCHEMY: | |
cea7e2df | 1186 | cpu_probe_alchemy(c, cpu); |
1da177e4 LT |
1187 | break; |
1188 | case PRID_COMP_SIBYTE: | |
cea7e2df | 1189 | cpu_probe_sibyte(c, cpu); |
1da177e4 | 1190 | break; |
1c0c13eb | 1191 | case PRID_COMP_BROADCOM: |
cea7e2df | 1192 | cpu_probe_broadcom(c, cpu); |
1c0c13eb | 1193 | break; |
1da177e4 | 1194 | case PRID_COMP_SANDCRAFT: |
cea7e2df | 1195 | cpu_probe_sandcraft(c, cpu); |
1da177e4 | 1196 | break; |
a92b0588 | 1197 | case PRID_COMP_NXP: |
cea7e2df | 1198 | cpu_probe_nxp(c, cpu); |
a3dddd56 | 1199 | break; |
0dd4781b DD |
1200 | case PRID_COMP_CAVIUM: |
1201 | cpu_probe_cavium(c, cpu); | |
1202 | break; | |
83ccf69d LPC |
1203 | case PRID_COMP_INGENIC: |
1204 | cpu_probe_ingenic(c, cpu); | |
1205 | break; | |
a7117c6b J |
1206 | case PRID_COMP_NETLOGIC: |
1207 | cpu_probe_netlogic(c, cpu); | |
1208 | break; | |
1da177e4 | 1209 | } |
dec8b1ca | 1210 | |
cea7e2df RB |
1211 | BUG_ON(!__cpu_name[cpu]); |
1212 | BUG_ON(c->cputype == CPU_UNKNOWN); | |
1213 | ||
dec8b1ca FBH |
1214 | /* |
1215 | * Platform code can force the cpu type to optimize code | |
1216 | * generation. In that case be sure the cpu type is correctly | |
1217 | * manually setup otherwise it could trigger some nasty bugs. | |
1218 | */ | |
1219 | BUG_ON(current_cpu_type() != c->cputype); | |
1220 | ||
0103d23f KC |
1221 | if (mips_fpu_disabled) |
1222 | c->options &= ~MIPS_CPU_FPU; | |
1223 | ||
1224 | if (mips_dsp_disabled) | |
ee80f7c7 | 1225 | c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
0103d23f | 1226 | |
4194318c | 1227 | if (c->options & MIPS_CPU_FPU) { |
1da177e4 | 1228 | c->fpu_id = cpu_get_fpu_id(); |
4194318c | 1229 | |
adb37892 DCZ |
1230 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | |
1231 | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { | |
4194318c RB |
1232 | if (c->fpu_id & MIPS_FPIR_3D) |
1233 | c->ases |= MIPS_ASE_MIPS3D; | |
1234 | } | |
1235 | } | |
9966db25 | 1236 | |
da4b62cd | 1237 | if (cpu_has_mips_r2) { |
f6771dbb | 1238 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |
da4b62cd AC |
1239 | /* R2 has Performance Counter Interrupt indicator */ |
1240 | c->options |= MIPS_CPU_PCI; | |
1241 | } | |
f6771dbb RB |
1242 | else |
1243 | c->srsets = 1; | |
91dfc423 GR |
1244 | |
1245 | cpu_probe_vmbits(c); | |
949e51be DD |
1246 | |
1247 | #ifdef CONFIG_64BIT | |
1248 | if (cpu == 0) | |
1249 | __ua_limit = ~((1ull << cpu_vmbits) - 1); | |
1250 | #endif | |
1da177e4 LT |
1251 | } |
1252 | ||
234fcd14 | 1253 | __cpuinit void cpu_report(void) |
1da177e4 LT |
1254 | { |
1255 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1256 | ||
9966db25 RB |
1257 | printk(KERN_INFO "CPU revision is: %08x (%s)\n", |
1258 | c->processor_id, cpu_name_string()); | |
1da177e4 | 1259 | if (c->options & MIPS_CPU_FPU) |
9966db25 | 1260 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); |
1da177e4 | 1261 | } |