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MIPS: Get rid of MIPS I flag and test macros.
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4
LT		 22#include <asm/cpu.h>
23#include <asm/fpu.h>
24#include <asm/mipsregs.h>
654f57bf 25#include <asm/watch.h>
06372a63 26#include <asm/elf.h>
a074f0e8 27#include <asm/spram.h>
949e51be
DD		 28#include <asm/uaccess.h>
29
0103d23f
KC		 30static int __cpuinitdata mips_fpu_disabled;
31
32static int __init fpu_disable(char *s)
33{
34 cpu_data[0].options &= ~MIPS_CPU_FPU;
35 mips_fpu_disabled = 1;
36
37 return 1;
38}
39
40__setup("nofpu", fpu_disable);
41
42int __cpuinitdata mips_dsp_disabled;
43
44static int __init dsp_disable(char *s)
45{
ee80f7c7 46 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 47 mips_dsp_disabled = 1;
48
49 return 1;
50}
51
52__setup("nodsp", dsp_disable);
53
9267a30d
MSJ		 54static inline void check_errata(void)
55{
56 struct cpuinfo_mips *c = &current_cpu_data;
57
58 switch (c->cputype) {
59 case CPU_34K:
60 /*
61 * Erratum "RPS May Cause Incorrect Instruction Execution"
62 * This code only handles VPE0, any SMP/SMTC/RTOS code
63 * making use of VPE1 will be responsable for that VPE.
64 */
65 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
66 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
67 break;
68 default:
69 break;
70 }
71}
72
1da177e4
LT		 73void __init check_bugs32(void)
74{
9267a30d 75 check_errata();
1da177e4
LT		 76}
77
78/*
79 * Probe whether cpu has config register by trying to play with
80 * alternate cache bit and see whether it matters.
81 * It's used by cpu_probe to distinguish between R3000A and R3081.
82 */
83static inline int cpu_has_confreg(void)
84{
85#ifdef CONFIG_CPU_R3000
86 extern unsigned long r3k_cache_size(unsigned long);
87 unsigned long size1, size2;
88 unsigned long cfg = read_c0_conf();
89
90 size1 = r3k_cache_size(ST0_ISC);
91 write_c0_conf(cfg ^ R30XX_CONF_AC);
92 size2 = r3k_cache_size(ST0_ISC);
93 write_c0_conf(cfg);
94 return size1 != size2;
95#else
96 return 0;
97#endif
98}
99
c094c99e
RM		 100static inline void set_elf_platform(int cpu, const char *plat)
101{
102 if (cpu == 0)
103 __elf_platform = plat;
104}
105
1da177e4
LT		 106/*
107 * Get the FPU Implementation/Revision.
108 */
109static inline unsigned long cpu_get_fpu_id(void)
110{
111 unsigned long tmp, fpu_id;
112
113 tmp = read_c0_status();
114 __enable_fpu();
115 fpu_id = read_32bit_cp1_register(CP1_REVISION);
116 write_c0_status(tmp);
117 return fpu_id;
118}
119
120/*
121 * Check the CPU has an FPU the official way.
122 */
123static inline int __cpu_has_fpu(void)
124{
125 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
126}
127
91dfc423
GR		 128static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
129{
130#ifdef __NEED_VMBITS_PROBE
5b7efa89 131 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 132 back_to_back_c0_hazard();
5b7efa89 133 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 134#endif
135}
136
a96102be
SH		 137static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
138{
139 switch (isa) {
140 case MIPS_CPU_ISA_M64R2:
141 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
142 case MIPS_CPU_ISA_M64R1:
143 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
144 case MIPS_CPU_ISA_V:
145 c->isa_level |= MIPS_CPU_ISA_V;
146 case MIPS_CPU_ISA_IV:
147 c->isa_level |= MIPS_CPU_ISA_IV;
148 case MIPS_CPU_ISA_III:
1990e542 149 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 150 break;
151
152 case MIPS_CPU_ISA_M32R2:
153 c->isa_level |= MIPS_CPU_ISA_M32R2;
154 case MIPS_CPU_ISA_M32R1:
155 c->isa_level |= MIPS_CPU_ISA_M32R1;
156 case MIPS_CPU_ISA_II:
157 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 158 break;
159 }
160}
161
2fa36399
KC		 162static char unknown_isa[] __cpuinitdata = KERN_ERR \
163 "Unsupported ISA type, c0.config0: %d.";
164
165static inline unsigned int decode_config0(struct cpuinfo_mips *c)
166{
167 unsigned int config0;
168 int isa;
169
170 config0 = read_c0_config();
171
172 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
173 c->options |= MIPS_CPU_TLB;
174 isa = (config0 & MIPS_CONF_AT) >> 13;
175 switch (isa) {
176 case 0:
177 switch ((config0 & MIPS_CONF_AR) >> 10) {
178 case 0:
a96102be 179 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 180 break;
181 case 1:
a96102be 182 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 183 break;
184 default:
185 goto unknown;
186 }
187 break;
188 case 2:
189 switch ((config0 & MIPS_CONF_AR) >> 10) {
190 case 0:
a96102be 191 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 192 break;
193 case 1:
a96102be 194 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 195 break;
196 default:
197 goto unknown;
198 }
199 break;
200 default:
201 goto unknown;
202 }
203
204 return config0 & MIPS_CONF_M;
205
206unknown:
207 panic(unknown_isa, config0);
208}
209
210static inline unsigned int decode_config1(struct cpuinfo_mips *c)
211{
212 unsigned int config1;
213
214 config1 = read_c0_config1();
215
216 if (config1 & MIPS_CONF1_MD)
217 c->ases |= MIPS_ASE_MDMX;
218 if (config1 & MIPS_CONF1_WR)
219 c->options |= MIPS_CPU_WATCH;
220 if (config1 & MIPS_CONF1_CA)
221 c->ases |= MIPS_ASE_MIPS16;
222 if (config1 & MIPS_CONF1_EP)
223 c->options |= MIPS_CPU_EJTAG;
224 if (config1 & MIPS_CONF1_FP) {
225 c->options |= MIPS_CPU_FPU;
226 c->options |= MIPS_CPU_32FPR;
227 }
228 if (cpu_has_tlb)
229 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
230
231 return config1 & MIPS_CONF_M;
232}
233
234static inline unsigned int decode_config2(struct cpuinfo_mips *c)
235{
236 unsigned int config2;
237
238 config2 = read_c0_config2();
239
240 if (config2 & MIPS_CONF2_SL)
241 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
242
243 return config2 & MIPS_CONF_M;
244}
245
246static inline unsigned int decode_config3(struct cpuinfo_mips *c)
247{
248 unsigned int config3;
249
250 config3 = read_c0_config3();
251
b2ab4f08 252 if (config3 & MIPS_CONF3_SM) {
2fa36399 253 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 254 c->options |= MIPS_CPU_RIXI;
255 }
256 if (config3 & MIPS_CONF3_RXI)
257 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 258 if (config3 & MIPS_CONF3_DSP)
259 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 260 if (config3 & MIPS_CONF3_DSP2P)
261 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 262 if (config3 & MIPS_CONF3_VINT)
263 c->options |= MIPS_CPU_VINT;
264 if (config3 & MIPS_CONF3_VEIC)
265 c->options |= MIPS_CPU_VEIC;
266 if (config3 & MIPS_CONF3_MT)
267 c->ases |= MIPS_ASE_MIPSMT;
268 if (config3 & MIPS_CONF3_ULRI)
269 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 270 if (config3 & MIPS_CONF3_ISA)
271 c->options |= MIPS_CPU_MICROMIPS;
2a0b24f5
SH		 272#ifdef CONFIG_CPU_MICROMIPS
273 write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE);
274#endif
1e7decdb
DD		 275 if (config3 & MIPS_CONF3_VZ)
276 c->ases |= MIPS_ASE_VZ;
2fa36399
KC		 277
278 return config3 & MIPS_CONF_M;
279}
280
281static inline unsigned int decode_config4(struct cpuinfo_mips *c)
282{
283 unsigned int config4;
284
285 config4 = read_c0_config4();
286
287 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
288 && cpu_has_tlb)
289 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
290
291 c->kscratch_mask = (config4 >> 16) & 0xff;
292
293 return config4 & MIPS_CONF_M;
294}
295
296static void __cpuinit decode_configs(struct cpuinfo_mips *c)
297{
298 int ok;
299
300 /* MIPS32 or MIPS64 compliant CPU. */
301 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
302 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
303
304 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
305
306 ok = decode_config0(c); /* Read Config registers. */
70342287 307 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 308 if (ok)
309 ok = decode_config1(c);
310 if (ok)
311 ok = decode_config2(c);
312 if (ok)
313 ok = decode_config3(c);
314 if (ok)
315 ok = decode_config4(c);
316
317 mips_probe_watch_registers(c);
318
319 if (cpu_has_mips_r2)
320 c->core = read_c0_ebase() & 0x3ff;
321}
322
02cf2119 323#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 324 | MIPS_CPU_COUNTER)
325
cea7e2df 326static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4
LT		 327{
328 switch (c->processor_id & 0xff00) {
329 case PRID_IMP_R2000:
330 c->cputype = CPU_R2000;
cea7e2df 331 __cpu_name[cpu] = "R2000";
02cf2119 332 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 333 MIPS_CPU_NOFPUEX;
1da177e4
LT		 334 if (__cpu_has_fpu())
335 c->options |= MIPS_CPU_FPU;
336 c->tlbsize = 64;
337 break;
338 case PRID_IMP_R3000:
cea7e2df
RB		 339 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
340 if (cpu_has_confreg()) {
1da177e4 341 c->cputype = CPU_R3081E;
cea7e2df
RB		 342 __cpu_name[cpu] = "R3081";
343 } else {
1da177e4 344 c->cputype = CPU_R3000A;
cea7e2df
RB		 345 __cpu_name[cpu] = "R3000A";
346 }
cea7e2df 347 } else {
1da177e4 348 c->cputype = CPU_R3000;
cea7e2df
RB		 349 __cpu_name[cpu] = "R3000";
350 }
02cf2119 351 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 352 MIPS_CPU_NOFPUEX;
1da177e4
LT		 353 if (__cpu_has_fpu())
354 c->options |= MIPS_CPU_FPU;
355 c->tlbsize = 64;
356 break;
357 case PRID_IMP_R4000:
358 if (read_c0_config() & CONF_SC) {
cea7e2df 359 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 360 c->cputype = CPU_R4400PC;
cea7e2df
RB		 361 __cpu_name[cpu] = "R4400PC";
362 } else {
1da177e4 363 c->cputype = CPU_R4000PC;
cea7e2df
RB		 364 __cpu_name[cpu] = "R4000PC";
365 }
1da177e4 366 } else {
cea7e2df 367 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 368 c->cputype = CPU_R4400SC;
cea7e2df
RB		 369 __cpu_name[cpu] = "R4400SC";
370 } else {
1da177e4 371 c->cputype = CPU_R4000SC;
cea7e2df
RB		 372 __cpu_name[cpu] = "R4000SC";
373 }
1da177e4
LT		 374 }
375
a96102be 376 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 377 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 378 MIPS_CPU_WATCH | MIPS_CPU_VCE |
379 MIPS_CPU_LLSC;
1da177e4
LT		 380 c->tlbsize = 48;
381 break;
382 case PRID_IMP_VR41XX:
9f91e506
YY		 383 set_isa(c, MIPS_CPU_ISA_III);
384 c->options = R4K_OPTS;
385 c->tlbsize = 32;
1da177e4 386 switch (c->processor_id & 0xf0) {
1da177e4
LT		 387 case PRID_REV_VR4111:
388 c->cputype = CPU_VR4111;
cea7e2df 389 __cpu_name[cpu] = "NEC VR4111";
1da177e4 390 break;
1da177e4
LT		 391 case PRID_REV_VR4121:
392 c->cputype = CPU_VR4121;
cea7e2df 393 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 394 break;
395 case PRID_REV_VR4122:
cea7e2df 396 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 397 c->cputype = CPU_VR4122;
cea7e2df
RB		 398 __cpu_name[cpu] = "NEC VR4122";
399 } else {
1da177e4 400 c->cputype = CPU_VR4181A;
cea7e2df
RB		 401 __cpu_name[cpu] = "NEC VR4181A";
402 }
1da177e4
LT		 403 break;
404 case PRID_REV_VR4130:
cea7e2df 405 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 406 c->cputype = CPU_VR4131;
cea7e2df
RB		 407 __cpu_name[cpu] = "NEC VR4131";
408 } else {
1da177e4 409 c->cputype = CPU_VR4133;
9f91e506 410 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 411 __cpu_name[cpu] = "NEC VR4133";
412 }
1da177e4
LT		 413 break;
414 default:
415 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
416 c->cputype = CPU_VR41XX;
cea7e2df 417 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 418 break;
419 }
1da177e4
LT		 420 break;
421 case PRID_IMP_R4300:
422 c->cputype = CPU_R4300;
cea7e2df 423 __cpu_name[cpu] = "R4300";
a96102be 424 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 425 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 426 MIPS_CPU_LLSC;
1da177e4
LT		 427 c->tlbsize = 32;
428 break;
429 case PRID_IMP_R4600:
430 c->cputype = CPU_R4600;
cea7e2df 431 __cpu_name[cpu] = "R4600";
a96102be 432 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 433 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
434 MIPS_CPU_LLSC;
1da177e4
LT		 435 c->tlbsize = 48;
436 break;
437 #if 0
03751e79 438 case PRID_IMP_R4650:
1da177e4
LT		 439 /*
440 * This processor doesn't have an MMU, so it's not
441 * "real easy" to run Linux on it. It is left purely
442 * for documentation. Commented out because it shares
443 * it's c0_prid id number with the TX3900.
444 */
a3dddd56 445 c->cputype = CPU_R4650;
cea7e2df 446 __cpu_name[cpu] = "R4650";
a96102be 447 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 448 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 449 c->tlbsize = 48;
1da177e4
LT		 450 break;
451 #endif
452 case PRID_IMP_TX39:
02cf2119 453 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 454
455 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
456 c->cputype = CPU_TX3927;
cea7e2df 457 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 458 c->tlbsize = 64;
459 } else {
460 switch (c->processor_id & 0xff) {
461 case PRID_REV_TX3912:
462 c->cputype = CPU_TX3912;
cea7e2df 463 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 464 c->tlbsize = 32;
465 break;
466 case PRID_REV_TX3922:
467 c->cputype = CPU_TX3922;
cea7e2df 468 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 469 c->tlbsize = 64;
470 break;
1da177e4
LT		 471 }
472 }
473 break;
474 case PRID_IMP_R4700:
475 c->cputype = CPU_R4700;
cea7e2df 476 __cpu_name[cpu] = "R4700";
a96102be 477 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 478 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 479 MIPS_CPU_LLSC;
1da177e4
LT		 480 c->tlbsize = 48;
481 break;
482 case PRID_IMP_TX49:
483 c->cputype = CPU_TX49XX;
cea7e2df 484 __cpu_name[cpu] = "R49XX";
a96102be 485 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 486 c->options = R4K_OPTS | MIPS_CPU_LLSC;
487 if (!(c->processor_id & 0x08))
488 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
489 c->tlbsize = 48;
490 break;
491 case PRID_IMP_R5000:
492 c->cputype = CPU_R5000;
cea7e2df 493 __cpu_name[cpu] = "R5000";
a96102be 494 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 495 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 496 MIPS_CPU_LLSC;
1da177e4
LT		 497 c->tlbsize = 48;
498 break;
499 case PRID_IMP_R5432:
500 c->cputype = CPU_R5432;
cea7e2df 501 __cpu_name[cpu] = "R5432";
a96102be 502 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 503 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 504 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 505 c->tlbsize = 48;
506 break;
507 case PRID_IMP_R5500:
508 c->cputype = CPU_R5500;
cea7e2df 509 __cpu_name[cpu] = "R5500";
a96102be 510 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 511 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 512 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 513 c->tlbsize = 48;
514 break;
515 case PRID_IMP_NEVADA:
516 c->cputype = CPU_NEVADA;
cea7e2df 517 __cpu_name[cpu] = "Nevada";
a96102be 518 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 519 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 520 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 521 c->tlbsize = 48;
522 break;
523 case PRID_IMP_R6000:
524 c->cputype = CPU_R6000;
cea7e2df 525 __cpu_name[cpu] = "R6000";
a96102be 526 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 527 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 528 MIPS_CPU_LLSC;
1da177e4
LT		 529 c->tlbsize = 32;
530 break;
531 case PRID_IMP_R6000A:
532 c->cputype = CPU_R6000A;
cea7e2df 533 __cpu_name[cpu] = "R6000A";
a96102be 534 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 535 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 536 MIPS_CPU_LLSC;
1da177e4
LT		 537 c->tlbsize = 32;
538 break;
539 case PRID_IMP_RM7000:
540 c->cputype = CPU_RM7000;
cea7e2df 541 __cpu_name[cpu] = "RM7000";
a96102be 542 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 543 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 544 MIPS_CPU_LLSC;
1da177e4 545 /*
70342287 546 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 547 * the RM7000 v2.0 indicates if the TLB has 48 or 64
548 * entries.
549 *
70342287
RB		 550 * 29 1 => 64 entry JTLB
551 * 0 => 48 entry JTLB
1da177e4
LT		 552 */
553 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
554 break;
555 case PRID_IMP_RM9000:
556 c->cputype = CPU_RM9000;
cea7e2df 557 __cpu_name[cpu] = "RM9000";
a96102be 558 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 559 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 560 MIPS_CPU_LLSC;
1da177e4
LT		 561 /*
562 * Bit 29 in the info register of the RM9000
563 * indicates if the TLB has 48 or 64 entries.
564 *
70342287
RB		 565 * 29 1 => 64 entry JTLB
566 * 0 => 48 entry JTLB
1da177e4
LT		 567 */
568 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
569 break;
570 case PRID_IMP_R8000:
571 c->cputype = CPU_R8000;
cea7e2df 572 __cpu_name[cpu] = "RM8000";
a96102be 573 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 574 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 575 MIPS_CPU_FPU | MIPS_CPU_32FPR |
576 MIPS_CPU_LLSC;
1da177e4
LT		 577 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
578 break;
579 case PRID_IMP_R10000:
580 c->cputype = CPU_R10000;
cea7e2df 581 __cpu_name[cpu] = "R10000";
a96102be 582 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 583 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 584 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 585 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 586 MIPS_CPU_LLSC;
1da177e4
LT		 587 c->tlbsize = 64;
588 break;
589 case PRID_IMP_R12000:
590 c->cputype = CPU_R12000;
cea7e2df 591 __cpu_name[cpu] = "R12000";
a96102be 592 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 593 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 594 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 595 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 596 MIPS_CPU_LLSC;
1da177e4
LT		 597 c->tlbsize = 64;
598 break;
44d921b2
K		 599 case PRID_IMP_R14000:
600 c->cputype = CPU_R14000;
cea7e2df 601 __cpu_name[cpu] = "R14000";
a96102be 602 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 603 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 604 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 605 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 606 MIPS_CPU_LLSC;
44d921b2
K		 607 c->tlbsize = 64;
608 break;
2a21c730
FZ		 609 case PRID_IMP_LOONGSON2:
610 c->cputype = CPU_LOONGSON2;
cea7e2df 611 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 612
613 switch (c->processor_id & PRID_REV_MASK) {
614 case PRID_REV_LOONGSON2E:
615 set_elf_platform(cpu, "loongson2e");
616 break;
617 case PRID_REV_LOONGSON2F:
618 set_elf_platform(cpu, "loongson2f");
619 break;
620 }
621
a96102be 622 set_isa(c, MIPS_CPU_ISA_III);
2a21c730
FZ		 623 c->options = R4K_OPTS |
624 MIPS_CPU_FPU | MIPS_CPU_LLSC |
625 MIPS_CPU_32FPR;
626 c->tlbsize = 64;
627 break;
2fa36399
KC		 628 case PRID_IMP_LOONGSON1:
629 decode_configs(c);
b4672d37 630
2fa36399 631 c->cputype = CPU_LOONGSON1;
1da177e4 632
2fa36399
KC		 633 switch (c->processor_id & PRID_REV_MASK) {
634 case PRID_REV_LOONGSON1B:
635 __cpu_name[cpu] = "Loongson 1B";
b4672d37 636 break;
b4672d37 637 }
4194318c 638
2fa36399 639 break;
1da177e4 640 }
1da177e4
LT		 641}
642
cea7e2df 643static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 644{
4194318c 645 decode_configs(c);
1da177e4
LT		 646 switch (c->processor_id & 0xff00) {
647 case PRID_IMP_4KC:
648 c->cputype = CPU_4KC;
cea7e2df 649 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 650 break;
651 case PRID_IMP_4KEC:
2b07bd02
RB		 652 case PRID_IMP_4KECR2:
653 c->cputype = CPU_4KEC;
cea7e2df 654 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 655 break;
1da177e4 656 case PRID_IMP_4KSC:
8afcb5d8 657 case PRID_IMP_4KSD:
1da177e4 658 c->cputype = CPU_4KSC;
cea7e2df 659 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 660 break;
661 case PRID_IMP_5KC:
662 c->cputype = CPU_5KC;
cea7e2df 663 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 664 break;
78d4803f
LY		 665 case PRID_IMP_5KE:
666 c->cputype = CPU_5KE;
667 __cpu_name[cpu] = "MIPS 5KE";
668 break;
1da177e4
LT		 669 case PRID_IMP_20KC:
670 c->cputype = CPU_20KC;
cea7e2df 671 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 672 break;
673 case PRID_IMP_24K:
674 c->cputype = CPU_24K;
cea7e2df 675 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 676 break;
42f3caef
JC		 677 case PRID_IMP_24KE:
678 c->cputype = CPU_24K;
679 __cpu_name[cpu] = "MIPS 24KEc";
680 break;
1da177e4
LT		 681 case PRID_IMP_25KF:
682 c->cputype = CPU_25KF;
cea7e2df 683 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 684 break;
bbc7f22f
RB		 685 case PRID_IMP_34K:
686 c->cputype = CPU_34K;
cea7e2df 687 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 688 break;
c620953c
CD		 689 case PRID_IMP_74K:
690 c->cputype = CPU_74K;
cea7e2df 691 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 692 break;
113c62d9
SH		 693 case PRID_IMP_M14KC:
694 c->cputype = CPU_M14KC;
695 __cpu_name[cpu] = "MIPS M14Kc";
696 break;
f8fa4811
SH		 697 case PRID_IMP_M14KEC:
698 c->cputype = CPU_M14KEC;
699 __cpu_name[cpu] = "MIPS M14KEc";
700 break;
39b8d525
RB		 701 case PRID_IMP_1004K:
702 c->cputype = CPU_1004K;
cea7e2df 703 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 704 break;
006a851b
SH		 705 case PRID_IMP_1074K:
706 c->cputype = CPU_74K;
707 __cpu_name[cpu] = "MIPS 1074Kc";
708 break;
1da177e4 709 }
0b6d497f
CD		 710
711 spram_config();
1da177e4
LT		 712}
713
cea7e2df 714static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 715{
4194318c 716 decode_configs(c);
1da177e4
LT		 717 switch (c->processor_id & 0xff00) {
718 case PRID_IMP_AU1_REV1:
719 case PRID_IMP_AU1_REV2:
270717a8 720 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 721 switch ((c->processor_id >> 24) & 0xff) {
722 case 0:
cea7e2df 723 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 724 break;
725 case 1:
cea7e2df 726 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 727 break;
728 case 2:
cea7e2df 729 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 730 break;
731 case 3:
cea7e2df 732 __cpu_name[cpu] = "Au1550";
1da177e4 733 break;
e3ad1c23 734 case 4:
cea7e2df 735 __cpu_name[cpu] = "Au1200";
270717a8 736 if ((c->processor_id & 0xff) == 2)
cea7e2df 737 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 738 break;
739 case 5:
cea7e2df 740 __cpu_name[cpu] = "Au1210";
e3ad1c23 741 break;
1da177e4 742 default:
270717a8 743 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 744 break;
745 }
1da177e4
LT		 746 break;
747 }
748}
749
cea7e2df 750static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 751{
4194318c 752 decode_configs(c);
02cf2119 753
1da177e4
LT		 754 switch (c->processor_id & 0xff00) {
755 case PRID_IMP_SB1:
756 c->cputype = CPU_SB1;
cea7e2df 757 __cpu_name[cpu] = "SiByte SB1";
1da177e4 758 /* FPU in pass1 is known to have issues. */
aa32374a 759 if ((c->processor_id & 0xff) < 0x02)
010b853b 760 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 761 break;
93ce2f52
AI		 762 case PRID_IMP_SB1A:
763 c->cputype = CPU_SB1A;
cea7e2df 764 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 765 break;
1da177e4
LT		 766 }
767}
768
cea7e2df 769static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 770{
4194318c 771 decode_configs(c);
1da177e4
LT		 772 switch (c->processor_id & 0xff00) {
773 case PRID_IMP_SR71000:
774 c->cputype = CPU_SR71000;
cea7e2df 775 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 776 c->scache.ways = 8;
777 c->tlbsize = 64;
778 break;
779 }
780}
781
cea7e2df 782static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 783{
784 decode_configs(c);
785 switch (c->processor_id & 0xff00) {
786 case PRID_IMP_PR4450:
787 c->cputype = CPU_PR4450;
cea7e2df 788 __cpu_name[cpu] = "Philips PR4450";
a96102be 789 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 790 break;
bdf21b18
PP		 791 }
792}
793
cea7e2df 794static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 795{
796 decode_configs(c);
797 switch (c->processor_id & 0xff00) {
190fca3e
KC		 798 case PRID_IMP_BMIPS32_REV4:
799 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 800 c->cputype = CPU_BMIPS32;
801 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 802 set_elf_platform(cpu, "bmips32");
602977b0
KC		 803 break;
804 case PRID_IMP_BMIPS3300:
805 case PRID_IMP_BMIPS3300_ALT:
806 case PRID_IMP_BMIPS3300_BUG:
807 c->cputype = CPU_BMIPS3300;
808 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 809 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 810 break;
811 case PRID_IMP_BMIPS43XX: {
812 int rev = c->processor_id & 0xff;
813
814 if (rev >= PRID_REV_BMIPS4380_LO &&
815 rev <= PRID_REV_BMIPS4380_HI) {
816 c->cputype = CPU_BMIPS4380;
817 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 818 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 819 } else {
820 c->cputype = CPU_BMIPS4350;
821 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 822 set_elf_platform(cpu, "bmips4350");
602977b0 823 }
0de663ef 824 break;
602977b0
KC		 825 }
826 case PRID_IMP_BMIPS5000:
827 c->cputype = CPU_BMIPS5000;
828 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 829 set_elf_platform(cpu, "bmips5000");
602977b0 830 c->options |= MIPS_CPU_ULRI;
0de663ef 831 break;
1c0c13eb
AJ		 832 }
833}
834
0dd4781b
DD		 835static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
836{
837 decode_configs(c);
838 switch (c->processor_id & 0xff00) {
839 case PRID_IMP_CAVIUM_CN38XX:
840 case PRID_IMP_CAVIUM_CN31XX:
841 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 842 c->cputype = CPU_CAVIUM_OCTEON;
843 __cpu_name[cpu] = "Cavium Octeon";
844 goto platform;
0dd4781b
DD		 845 case PRID_IMP_CAVIUM_CN58XX:
846 case PRID_IMP_CAVIUM_CN56XX:
847 case PRID_IMP_CAVIUM_CN50XX:
848 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 849 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
850 __cpu_name[cpu] = "Cavium Octeon+";
851platform:
c094c99e 852 set_elf_platform(cpu, "octeon");
0dd4781b 853 break;
a1431b61 854 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 855 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 856 case PRID_IMP_CAVIUM_CN66XX:
857 case PRID_IMP_CAVIUM_CN68XX:
0e56b385
DD		 858 c->cputype = CPU_CAVIUM_OCTEON2;
859 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 860 set_elf_platform(cpu, "octeon2");
0e56b385 861 break;
0dd4781b
DD		 862 default:
863 printk(KERN_INFO "Unknown Octeon chip!\n");
864 c->cputype = CPU_UNKNOWN;
865 break;
866 }
867}
868
83ccf69d
LPC		 869static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
870{
871 decode_configs(c);
872 /* JZRISC does not implement the CP0 counter. */
873 c->options &= ~MIPS_CPU_COUNTER;
874 switch (c->processor_id & 0xff00) {
875 case PRID_IMP_JZRISC:
876 c->cputype = CPU_JZRISC;
877 __cpu_name[cpu] = "Ingenic JZRISC";
878 break;
879 default:
880 panic("Unknown Ingenic Processor ID!");
881 break;
882 }
883}
884
a7117c6b
J		 885static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
886{
887 decode_configs(c);
888
809f36c6
ML		 889 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
890 c->cputype = CPU_ALCHEMY;
891 __cpu_name[cpu] = "Au1300";
892 /* following stuff is not for Alchemy */
893 return;
894 }
895
70342287
RB		 896 c->options = (MIPS_CPU_TLB |
897 MIPS_CPU_4KEX |
a7117c6b 898 MIPS_CPU_COUNTER |
70342287
RB		 899 MIPS_CPU_DIVEC |
900 MIPS_CPU_WATCH |
901 MIPS_CPU_EJTAG |
a7117c6b
J		 902 MIPS_CPU_LLSC);
903
904 switch (c->processor_id & 0xff00) {
2aa54b20
J		 905 case PRID_IMP_NETLOGIC_XLP8XX:
906 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 907 c->cputype = CPU_XLP;
908 __cpu_name[cpu] = "Netlogic XLP";
909 break;
910
a7117c6b
J		 911 case PRID_IMP_NETLOGIC_XLR732:
912 case PRID_IMP_NETLOGIC_XLR716:
913 case PRID_IMP_NETLOGIC_XLR532:
914 case PRID_IMP_NETLOGIC_XLR308:
915 case PRID_IMP_NETLOGIC_XLR532C:
916 case PRID_IMP_NETLOGIC_XLR516C:
917 case PRID_IMP_NETLOGIC_XLR508C:
918 case PRID_IMP_NETLOGIC_XLR308C:
919 c->cputype = CPU_XLR;
920 __cpu_name[cpu] = "Netlogic XLR";
921 break;
922
923 case PRID_IMP_NETLOGIC_XLS608:
924 case PRID_IMP_NETLOGIC_XLS408:
925 case PRID_IMP_NETLOGIC_XLS404:
926 case PRID_IMP_NETLOGIC_XLS208:
927 case PRID_IMP_NETLOGIC_XLS204:
928 case PRID_IMP_NETLOGIC_XLS108:
929 case PRID_IMP_NETLOGIC_XLS104:
930 case PRID_IMP_NETLOGIC_XLS616B:
931 case PRID_IMP_NETLOGIC_XLS608B:
932 case PRID_IMP_NETLOGIC_XLS416B:
933 case PRID_IMP_NETLOGIC_XLS412B:
934 case PRID_IMP_NETLOGIC_XLS408B:
935 case PRID_IMP_NETLOGIC_XLS404B:
936 c->cputype = CPU_XLR;
937 __cpu_name[cpu] = "Netlogic XLS";
938 break;
939
940 default:
a3d4fb2d 941 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 942 c->processor_id);
943 c->cputype = CPU_XLR;
944 break;
945 }
946
a3d4fb2d 947 if (c->cputype == CPU_XLP) {
a96102be 948 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 949 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
950 /* This will be updated again after all threads are woken up */
951 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
952 } else {
a96102be 953 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 954 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
955 }
7777b939 956 c->kscratch_mask = 0xf;
a7117c6b
J		 957}
958
949e51be
DD		 959#ifdef CONFIG_64BIT
960/* For use by uaccess.h */
961u64 __ua_limit;
962EXPORT_SYMBOL(__ua_limit);
963#endif
964
9966db25 965const char *__cpu_name[NR_CPUS];
874fd3b5 966const char *__elf_platform;
9966db25 967
234fcd14 968__cpuinit void cpu_probe(void)
1da177e4
LT		 969{
970 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 971 unsigned int cpu = smp_processor_id();
1da177e4 972
70342287 973 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 974 c->fpu_id = FPIR_IMP_NONE;
975 c->cputype = CPU_UNKNOWN;
976
977 c->processor_id = read_c0_prid();
978 switch (c->processor_id & 0xff0000) {
979 case PRID_COMP_LEGACY:
cea7e2df 980 cpu_probe_legacy(c, cpu);
1da177e4
LT		 981 break;
982 case PRID_COMP_MIPS:
cea7e2df 983 cpu_probe_mips(c, cpu);
1da177e4
LT		 984 break;
985 case PRID_COMP_ALCHEMY:
cea7e2df 986 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 987 break;
988 case PRID_COMP_SIBYTE:
cea7e2df 989 cpu_probe_sibyte(c, cpu);
1da177e4 990 break;
1c0c13eb 991 case PRID_COMP_BROADCOM:
cea7e2df 992 cpu_probe_broadcom(c, cpu);
1c0c13eb 993 break;
1da177e4 994 case PRID_COMP_SANDCRAFT:
cea7e2df 995 cpu_probe_sandcraft(c, cpu);
1da177e4 996 break;
a92b0588 997 case PRID_COMP_NXP:
cea7e2df 998 cpu_probe_nxp(c, cpu);
a3dddd56 999 break;
0dd4781b
DD		 1000 case PRID_COMP_CAVIUM:
1001 cpu_probe_cavium(c, cpu);
1002 break;
83ccf69d
LPC		 1003 case PRID_COMP_INGENIC:
1004 cpu_probe_ingenic(c, cpu);
1005 break;
a7117c6b
J		 1006 case PRID_COMP_NETLOGIC:
1007 cpu_probe_netlogic(c, cpu);
1008 break;
1da177e4 1009 }
dec8b1ca 1010
cea7e2df
RB		 1011 BUG_ON(!__cpu_name[cpu]);
1012 BUG_ON(c->cputype == CPU_UNKNOWN);
1013
dec8b1ca
FBH		 1014 /*
1015 * Platform code can force the cpu type to optimize code
1016 * generation. In that case be sure the cpu type is correctly
1017 * manually setup otherwise it could trigger some nasty bugs.
1018 */
1019 BUG_ON(current_cpu_type() != c->cputype);
1020
0103d23f
KC		 1021 if (mips_fpu_disabled)
1022 c->options &= ~MIPS_CPU_FPU;
1023
1024 if (mips_dsp_disabled)
ee80f7c7 1025 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1026
4194318c 1027 if (c->options & MIPS_CPU_FPU) {
1da177e4 1028 c->fpu_id = cpu_get_fpu_id();
4194318c 1029
adb37892
DCZ		 1030 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1031 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
4194318c
RB		 1032 if (c->fpu_id & MIPS_FPIR_3D)
1033 c->ases |= MIPS_ASE_MIPS3D;
1034 }
1035 }
9966db25 1036
da4b62cd 1037 if (cpu_has_mips_r2) {
f6771dbb 1038 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1039 /* R2 has Performance Counter Interrupt indicator */
1040 c->options |= MIPS_CPU_PCI;
1041 }
f6771dbb
RB		 1042 else
1043 c->srsets = 1;
91dfc423
GR		 1044
1045 cpu_probe_vmbits(c);
949e51be
DD		 1046
1047#ifdef CONFIG_64BIT
1048 if (cpu == 0)
1049 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1050#endif
1da177e4
LT		 1051}
1052
234fcd14 1053__cpuinit void cpu_report(void)
1da177e4
LT		 1054{
1055 struct cpuinfo_mips *c = &current_cpu_data;
1056
9966db25
RB		 1057 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1058 c->processor_id, cpu_name_string());
1da177e4 1059 if (c->options & MIPS_CPU_FPU)
9966db25 1060 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 1061}
Linux kernel - Deliverables
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