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Merge tag 'range-macro' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
69f24d17 23#include <asm/cpu-type.h>
1da177e4
LT		 24#include <asm/fpu.h>
25#include <asm/mipsregs.h>
654f57bf 26#include <asm/watch.h>
06372a63 27#include <asm/elf.h>
a074f0e8 28#include <asm/spram.h>
949e51be
DD		 29#include <asm/uaccess.h>
30
078a55fc 31static int mips_fpu_disabled;
0103d23f
KC		 32
33static int __init fpu_disable(char *s)
34{
35 cpu_data[0].options &= ~MIPS_CPU_FPU;
36 mips_fpu_disabled = 1;
37
38 return 1;
39}
40
41__setup("nofpu", fpu_disable);
42
078a55fc 43int mips_dsp_disabled;
0103d23f
KC		 44
45static int __init dsp_disable(char *s)
46{
ee80f7c7 47 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 48 mips_dsp_disabled = 1;
49
50 return 1;
51}
52
53__setup("nodsp", dsp_disable);
54
9267a30d
MSJ		 55static inline void check_errata(void)
56{
57 struct cpuinfo_mips *c = &current_cpu_data;
58
69f24d17 59 switch (current_cpu_type()) {
9267a30d
MSJ		 60 case CPU_34K:
61 /*
62 * Erratum "RPS May Cause Incorrect Instruction Execution"
63 * This code only handles VPE0, any SMP/SMTC/RTOS code
64 * making use of VPE1 will be responsable for that VPE.
65 */
66 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
67 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
68 break;
69 default:
70 break;
71 }
72}
73
1da177e4
LT		 74void __init check_bugs32(void)
75{
9267a30d 76 check_errata();
1da177e4
LT		 77}
78
79/*
80 * Probe whether cpu has config register by trying to play with
81 * alternate cache bit and see whether it matters.
82 * It's used by cpu_probe to distinguish between R3000A and R3081.
83 */
84static inline int cpu_has_confreg(void)
85{
86#ifdef CONFIG_CPU_R3000
87 extern unsigned long r3k_cache_size(unsigned long);
88 unsigned long size1, size2;
89 unsigned long cfg = read_c0_conf();
90
91 size1 = r3k_cache_size(ST0_ISC);
92 write_c0_conf(cfg ^ R30XX_CONF_AC);
93 size2 = r3k_cache_size(ST0_ISC);
94 write_c0_conf(cfg);
95 return size1 != size2;
96#else
97 return 0;
98#endif
99}
100
c094c99e
RM		 101static inline void set_elf_platform(int cpu, const char *plat)
102{
103 if (cpu == 0)
104 __elf_platform = plat;
105}
106
1da177e4
LT		 107/*
108 * Get the FPU Implementation/Revision.
109 */
110static inline unsigned long cpu_get_fpu_id(void)
111{
112 unsigned long tmp, fpu_id;
113
114 tmp = read_c0_status();
115 __enable_fpu();
116 fpu_id = read_32bit_cp1_register(CP1_REVISION);
117 write_c0_status(tmp);
118 return fpu_id;
119}
120
121/*
122 * Check the CPU has an FPU the official way.
123 */
124static inline int __cpu_has_fpu(void)
125{
8ff374b9 126 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
1da177e4
LT		 127}
128
91dfc423
GR		 129static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
130{
131#ifdef __NEED_VMBITS_PROBE
5b7efa89 132 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 133 back_to_back_c0_hazard();
5b7efa89 134 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 135#endif
136}
137
078a55fc 138static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 139{
140 switch (isa) {
141 case MIPS_CPU_ISA_M64R2:
142 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
143 case MIPS_CPU_ISA_M64R1:
144 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
145 case MIPS_CPU_ISA_V:
146 c->isa_level |= MIPS_CPU_ISA_V;
147 case MIPS_CPU_ISA_IV:
148 c->isa_level |= MIPS_CPU_ISA_IV;
149 case MIPS_CPU_ISA_III:
1990e542 150 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 151 break;
152
153 case MIPS_CPU_ISA_M32R2:
154 c->isa_level |= MIPS_CPU_ISA_M32R2;
155 case MIPS_CPU_ISA_M32R1:
156 c->isa_level |= MIPS_CPU_ISA_M32R1;
157 case MIPS_CPU_ISA_II:
158 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 159 break;
160 }
161}
162
078a55fc 163static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 164 "Unsupported ISA type, c0.config0: %d.";
165
166static inline unsigned int decode_config0(struct cpuinfo_mips *c)
167{
168 unsigned int config0;
169 int isa;
170
171 config0 = read_c0_config();
172
173 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
174 c->options |= MIPS_CPU_TLB;
175 isa = (config0 & MIPS_CONF_AT) >> 13;
176 switch (isa) {
177 case 0:
178 switch ((config0 & MIPS_CONF_AR) >> 10) {
179 case 0:
a96102be 180 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 181 break;
182 case 1:
a96102be 183 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 184 break;
185 default:
186 goto unknown;
187 }
188 break;
189 case 2:
190 switch ((config0 & MIPS_CONF_AR) >> 10) {
191 case 0:
a96102be 192 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 193 break;
194 case 1:
a96102be 195 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 196 break;
197 default:
198 goto unknown;
199 }
200 break;
201 default:
202 goto unknown;
203 }
204
205 return config0 & MIPS_CONF_M;
206
207unknown:
208 panic(unknown_isa, config0);
209}
210
211static inline unsigned int decode_config1(struct cpuinfo_mips *c)
212{
213 unsigned int config1;
214
215 config1 = read_c0_config1();
216
217 if (config1 & MIPS_CONF1_MD)
218 c->ases |= MIPS_ASE_MDMX;
219 if (config1 & MIPS_CONF1_WR)
220 c->options |= MIPS_CPU_WATCH;
221 if (config1 & MIPS_CONF1_CA)
222 c->ases |= MIPS_ASE_MIPS16;
223 if (config1 & MIPS_CONF1_EP)
224 c->options |= MIPS_CPU_EJTAG;
225 if (config1 & MIPS_CONF1_FP) {
226 c->options |= MIPS_CPU_FPU;
227 c->options |= MIPS_CPU_32FPR;
228 }
229 if (cpu_has_tlb)
230 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
231
232 return config1 & MIPS_CONF_M;
233}
234
235static inline unsigned int decode_config2(struct cpuinfo_mips *c)
236{
237 unsigned int config2;
238
239 config2 = read_c0_config2();
240
241 if (config2 & MIPS_CONF2_SL)
242 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
243
244 return config2 & MIPS_CONF_M;
245}
246
247static inline unsigned int decode_config3(struct cpuinfo_mips *c)
248{
249 unsigned int config3;
250
251 config3 = read_c0_config3();
252
b2ab4f08 253 if (config3 & MIPS_CONF3_SM) {
2fa36399 254 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 255 c->options |= MIPS_CPU_RIXI;
256 }
257 if (config3 & MIPS_CONF3_RXI)
258 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 259 if (config3 & MIPS_CONF3_DSP)
260 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 261 if (config3 & MIPS_CONF3_DSP2P)
262 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 263 if (config3 & MIPS_CONF3_VINT)
264 c->options |= MIPS_CPU_VINT;
265 if (config3 & MIPS_CONF3_VEIC)
266 c->options |= MIPS_CPU_VEIC;
267 if (config3 & MIPS_CONF3_MT)
268 c->ases |= MIPS_ASE_MIPSMT;
269 if (config3 & MIPS_CONF3_ULRI)
270 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 271 if (config3 & MIPS_CONF3_ISA)
272 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 273 if (config3 & MIPS_CONF3_VZ)
274 c->ases |= MIPS_ASE_VZ;
2fa36399
KC		 275
276 return config3 & MIPS_CONF_M;
277}
278
279static inline unsigned int decode_config4(struct cpuinfo_mips *c)
280{
281 unsigned int config4;
282
283 config4 = read_c0_config4();
284
285 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
286 && cpu_has_tlb)
287 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
288
289 c->kscratch_mask = (config4 >> 16) & 0xff;
290
291 return config4 & MIPS_CONF_M;
292}
293
8b8a7634
RB		 294static inline unsigned int decode_config5(struct cpuinfo_mips *c)
295{
296 unsigned int config5;
297
298 config5 = read_c0_config5();
299 config5 &= ~MIPS_CONF5_UFR;
300 write_c0_config5(config5);
301
302 return config5 & MIPS_CONF_M;
303}
304
078a55fc 305static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 306{
307 int ok;
308
309 /* MIPS32 or MIPS64 compliant CPU. */
310 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
311 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
312
313 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
314
315 ok = decode_config0(c); /* Read Config registers. */
70342287 316 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 317 if (ok)
318 ok = decode_config1(c);
319 if (ok)
320 ok = decode_config2(c);
321 if (ok)
322 ok = decode_config3(c);
323 if (ok)
324 ok = decode_config4(c);
8b8a7634
RB		 325 if (ok)
326 ok = decode_config5(c);
2fa36399
KC		 327
328 mips_probe_watch_registers(c);
329
330 if (cpu_has_mips_r2)
331 c->core = read_c0_ebase() & 0x3ff;
332}
333
02cf2119 334#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 335 | MIPS_CPU_COUNTER)
336
cea7e2df 337static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 338{
8ff374b9 339 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 340 case PRID_IMP_R2000:
341 c->cputype = CPU_R2000;
cea7e2df 342 __cpu_name[cpu] = "R2000";
02cf2119 343 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 344 MIPS_CPU_NOFPUEX;
1da177e4
LT		 345 if (__cpu_has_fpu())
346 c->options |= MIPS_CPU_FPU;
347 c->tlbsize = 64;
348 break;
349 case PRID_IMP_R3000:
8ff374b9 350 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 351 if (cpu_has_confreg()) {
1da177e4 352 c->cputype = CPU_R3081E;
cea7e2df
RB		 353 __cpu_name[cpu] = "R3081";
354 } else {
1da177e4 355 c->cputype = CPU_R3000A;
cea7e2df
RB		 356 __cpu_name[cpu] = "R3000A";
357 }
cea7e2df 358 } else {
1da177e4 359 c->cputype = CPU_R3000;
cea7e2df
RB		 360 __cpu_name[cpu] = "R3000";
361 }
02cf2119 362 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 363 MIPS_CPU_NOFPUEX;
1da177e4
LT		 364 if (__cpu_has_fpu())
365 c->options |= MIPS_CPU_FPU;
366 c->tlbsize = 64;
367 break;
368 case PRID_IMP_R4000:
369 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 370 if ((c->processor_id & PRID_REV_MASK) >=
371 PRID_REV_R4400) {
1da177e4 372 c->cputype = CPU_R4400PC;
cea7e2df
RB		 373 __cpu_name[cpu] = "R4400PC";
374 } else {
1da177e4 375 c->cputype = CPU_R4000PC;
cea7e2df
RB		 376 __cpu_name[cpu] = "R4000PC";
377 }
1da177e4 378 } else {
8ff374b9
MR		 379 if ((c->processor_id & PRID_REV_MASK) >=
380 PRID_REV_R4400) {
1da177e4 381 c->cputype = CPU_R4400SC;
cea7e2df
RB		 382 __cpu_name[cpu] = "R4400SC";
383 } else {
1da177e4 384 c->cputype = CPU_R4000SC;
cea7e2df
RB		 385 __cpu_name[cpu] = "R4000SC";
386 }
1da177e4
LT		 387 }
388
a96102be 389 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 391 MIPS_CPU_WATCH | MIPS_CPU_VCE |
392 MIPS_CPU_LLSC;
1da177e4
LT		 393 c->tlbsize = 48;
394 break;
395 case PRID_IMP_VR41XX:
9f91e506
YY		 396 set_isa(c, MIPS_CPU_ISA_III);
397 c->options = R4K_OPTS;
398 c->tlbsize = 32;
1da177e4 399 switch (c->processor_id & 0xf0) {
1da177e4
LT		 400 case PRID_REV_VR4111:
401 c->cputype = CPU_VR4111;
cea7e2df 402 __cpu_name[cpu] = "NEC VR4111";
1da177e4 403 break;
1da177e4
LT		 404 case PRID_REV_VR4121:
405 c->cputype = CPU_VR4121;
cea7e2df 406 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 407 break;
408 case PRID_REV_VR4122:
cea7e2df 409 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 410 c->cputype = CPU_VR4122;
cea7e2df
RB		 411 __cpu_name[cpu] = "NEC VR4122";
412 } else {
1da177e4 413 c->cputype = CPU_VR4181A;
cea7e2df
RB		 414 __cpu_name[cpu] = "NEC VR4181A";
415 }
1da177e4
LT		 416 break;
417 case PRID_REV_VR4130:
cea7e2df 418 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 419 c->cputype = CPU_VR4131;
cea7e2df
RB		 420 __cpu_name[cpu] = "NEC VR4131";
421 } else {
1da177e4 422 c->cputype = CPU_VR4133;
9f91e506 423 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 424 __cpu_name[cpu] = "NEC VR4133";
425 }
1da177e4
LT		 426 break;
427 default:
428 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
429 c->cputype = CPU_VR41XX;
cea7e2df 430 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 431 break;
432 }
1da177e4
LT		 433 break;
434 case PRID_IMP_R4300:
435 c->cputype = CPU_R4300;
cea7e2df 436 __cpu_name[cpu] = "R4300";
a96102be 437 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 438 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 439 MIPS_CPU_LLSC;
1da177e4
LT		 440 c->tlbsize = 32;
441 break;
442 case PRID_IMP_R4600:
443 c->cputype = CPU_R4600;
cea7e2df 444 __cpu_name[cpu] = "R4600";
a96102be 445 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 446 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
447 MIPS_CPU_LLSC;
1da177e4
LT		 448 c->tlbsize = 48;
449 break;
450 #if 0
03751e79 451 case PRID_IMP_R4650:
1da177e4
LT		 452 /*
453 * This processor doesn't have an MMU, so it's not
454 * "real easy" to run Linux on it. It is left purely
455 * for documentation. Commented out because it shares
456 * it's c0_prid id number with the TX3900.
457 */
a3dddd56 458 c->cputype = CPU_R4650;
cea7e2df 459 __cpu_name[cpu] = "R4650";
a96102be 460 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 461 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 462 c->tlbsize = 48;
1da177e4
LT		 463 break;
464 #endif
465 case PRID_IMP_TX39:
02cf2119 466 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 467
468 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
469 c->cputype = CPU_TX3927;
cea7e2df 470 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 471 c->tlbsize = 64;
472 } else {
8ff374b9 473 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 474 case PRID_REV_TX3912:
475 c->cputype = CPU_TX3912;
cea7e2df 476 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 477 c->tlbsize = 32;
478 break;
479 case PRID_REV_TX3922:
480 c->cputype = CPU_TX3922;
cea7e2df 481 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 482 c->tlbsize = 64;
483 break;
1da177e4
LT		 484 }
485 }
486 break;
487 case PRID_IMP_R4700:
488 c->cputype = CPU_R4700;
cea7e2df 489 __cpu_name[cpu] = "R4700";
a96102be 490 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 491 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 492 MIPS_CPU_LLSC;
1da177e4
LT		 493 c->tlbsize = 48;
494 break;
495 case PRID_IMP_TX49:
496 c->cputype = CPU_TX49XX;
cea7e2df 497 __cpu_name[cpu] = "R49XX";
a96102be 498 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 499 c->options = R4K_OPTS | MIPS_CPU_LLSC;
500 if (!(c->processor_id & 0x08))
501 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
502 c->tlbsize = 48;
503 break;
504 case PRID_IMP_R5000:
505 c->cputype = CPU_R5000;
cea7e2df 506 __cpu_name[cpu] = "R5000";
a96102be 507 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 508 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 509 MIPS_CPU_LLSC;
1da177e4
LT		 510 c->tlbsize = 48;
511 break;
512 case PRID_IMP_R5432:
513 c->cputype = CPU_R5432;
cea7e2df 514 __cpu_name[cpu] = "R5432";
a96102be 515 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 516 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 517 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 518 c->tlbsize = 48;
519 break;
520 case PRID_IMP_R5500:
521 c->cputype = CPU_R5500;
cea7e2df 522 __cpu_name[cpu] = "R5500";
a96102be 523 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 524 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 525 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 526 c->tlbsize = 48;
527 break;
528 case PRID_IMP_NEVADA:
529 c->cputype = CPU_NEVADA;
cea7e2df 530 __cpu_name[cpu] = "Nevada";
a96102be 531 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 532 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 533 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 534 c->tlbsize = 48;
535 break;
536 case PRID_IMP_R6000:
537 c->cputype = CPU_R6000;
cea7e2df 538 __cpu_name[cpu] = "R6000";
a96102be 539 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 540 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 541 MIPS_CPU_LLSC;
1da177e4
LT		 542 c->tlbsize = 32;
543 break;
544 case PRID_IMP_R6000A:
545 c->cputype = CPU_R6000A;
cea7e2df 546 __cpu_name[cpu] = "R6000A";
a96102be 547 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 548 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 549 MIPS_CPU_LLSC;
1da177e4
LT		 550 c->tlbsize = 32;
551 break;
552 case PRID_IMP_RM7000:
553 c->cputype = CPU_RM7000;
cea7e2df 554 __cpu_name[cpu] = "RM7000";
a96102be 555 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 556 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 557 MIPS_CPU_LLSC;
1da177e4 558 /*
70342287 559 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 560 * the RM7000 v2.0 indicates if the TLB has 48 or 64
561 * entries.
562 *
70342287
RB		 563 * 29 1 => 64 entry JTLB
564 * 0 => 48 entry JTLB
1da177e4
LT		 565 */
566 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
567 break;
568 case PRID_IMP_RM9000:
569 c->cputype = CPU_RM9000;
cea7e2df 570 __cpu_name[cpu] = "RM9000";
a96102be 571 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 572 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 573 MIPS_CPU_LLSC;
1da177e4
LT		 574 /*
575 * Bit 29 in the info register of the RM9000
576 * indicates if the TLB has 48 or 64 entries.
577 *
70342287
RB		 578 * 29 1 => 64 entry JTLB
579 * 0 => 48 entry JTLB
1da177e4
LT		 580 */
581 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
582 break;
583 case PRID_IMP_R8000:
584 c->cputype = CPU_R8000;
cea7e2df 585 __cpu_name[cpu] = "RM8000";
a96102be 586 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 587 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 588 MIPS_CPU_FPU | MIPS_CPU_32FPR |
589 MIPS_CPU_LLSC;
1da177e4
LT		 590 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
591 break;
592 case PRID_IMP_R10000:
593 c->cputype = CPU_R10000;
cea7e2df 594 __cpu_name[cpu] = "R10000";
a96102be 595 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 596 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 597 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 598 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 599 MIPS_CPU_LLSC;
1da177e4
LT		 600 c->tlbsize = 64;
601 break;
602 case PRID_IMP_R12000:
603 c->cputype = CPU_R12000;
cea7e2df 604 __cpu_name[cpu] = "R12000";
a96102be 605 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 606 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 607 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 608 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 609 MIPS_CPU_LLSC;
1da177e4
LT		 610 c->tlbsize = 64;
611 break;
44d921b2
K		 612 case PRID_IMP_R14000:
613 c->cputype = CPU_R14000;
cea7e2df 614 __cpu_name[cpu] = "R14000";
a96102be 615 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 616 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 617 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 618 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 619 MIPS_CPU_LLSC;
44d921b2
K		 620 c->tlbsize = 64;
621 break;
2a21c730
FZ		 622 case PRID_IMP_LOONGSON2:
623 c->cputype = CPU_LOONGSON2;
cea7e2df 624 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 625
626 switch (c->processor_id & PRID_REV_MASK) {
627 case PRID_REV_LOONGSON2E:
628 set_elf_platform(cpu, "loongson2e");
629 break;
630 case PRID_REV_LOONGSON2F:
631 set_elf_platform(cpu, "loongson2f");
632 break;
633 }
634
a96102be 635 set_isa(c, MIPS_CPU_ISA_III);
2a21c730
FZ		 636 c->options = R4K_OPTS |
637 MIPS_CPU_FPU | MIPS_CPU_LLSC |
638 MIPS_CPU_32FPR;
639 c->tlbsize = 64;
640 break;
2fa36399
KC		 641 case PRID_IMP_LOONGSON1:
642 decode_configs(c);
b4672d37 643
2fa36399 644 c->cputype = CPU_LOONGSON1;
1da177e4 645
2fa36399
KC		 646 switch (c->processor_id & PRID_REV_MASK) {
647 case PRID_REV_LOONGSON1B:
648 __cpu_name[cpu] = "Loongson 1B";
b4672d37 649 break;
b4672d37 650 }
4194318c 651
2fa36399 652 break;
1da177e4 653 }
1da177e4
LT		 654}
655
cea7e2df 656static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 657{
4194318c 658 decode_configs(c);
8ff374b9 659 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 660 case PRID_IMP_4KC:
661 c->cputype = CPU_4KC;
cea7e2df 662 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 663 break;
664 case PRID_IMP_4KEC:
2b07bd02
RB		 665 case PRID_IMP_4KECR2:
666 c->cputype = CPU_4KEC;
cea7e2df 667 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 668 break;
1da177e4 669 case PRID_IMP_4KSC:
8afcb5d8 670 case PRID_IMP_4KSD:
1da177e4 671 c->cputype = CPU_4KSC;
cea7e2df 672 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 673 break;
674 case PRID_IMP_5KC:
675 c->cputype = CPU_5KC;
cea7e2df 676 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 677 break;
78d4803f
LY		 678 case PRID_IMP_5KE:
679 c->cputype = CPU_5KE;
680 __cpu_name[cpu] = "MIPS 5KE";
681 break;
1da177e4
LT		 682 case PRID_IMP_20KC:
683 c->cputype = CPU_20KC;
cea7e2df 684 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 685 break;
686 case PRID_IMP_24K:
687 c->cputype = CPU_24K;
cea7e2df 688 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 689 break;
42f3caef
JC		 690 case PRID_IMP_24KE:
691 c->cputype = CPU_24K;
692 __cpu_name[cpu] = "MIPS 24KEc";
693 break;
1da177e4
LT		 694 case PRID_IMP_25KF:
695 c->cputype = CPU_25KF;
cea7e2df 696 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 697 break;
bbc7f22f
RB		 698 case PRID_IMP_34K:
699 c->cputype = CPU_34K;
cea7e2df 700 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 701 break;
c620953c
CD		 702 case PRID_IMP_74K:
703 c->cputype = CPU_74K;
cea7e2df 704 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 705 break;
113c62d9
SH		 706 case PRID_IMP_M14KC:
707 c->cputype = CPU_M14KC;
708 __cpu_name[cpu] = "MIPS M14Kc";
709 break;
f8fa4811
SH		 710 case PRID_IMP_M14KEC:
711 c->cputype = CPU_M14KEC;
712 __cpu_name[cpu] = "MIPS M14KEc";
713 break;
39b8d525
RB		 714 case PRID_IMP_1004K:
715 c->cputype = CPU_1004K;
cea7e2df 716 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 717 break;
006a851b
SH		 718 case PRID_IMP_1074K:
719 c->cputype = CPU_74K;
720 __cpu_name[cpu] = "MIPS 1074Kc";
721 break;
1da177e4 722 }
0b6d497f
CD		 723
724 spram_config();
1da177e4
LT		 725}
726
cea7e2df 727static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 728{
4194318c 729 decode_configs(c);
8ff374b9 730 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 731 case PRID_IMP_AU1_REV1:
732 case PRID_IMP_AU1_REV2:
270717a8 733 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 734 switch ((c->processor_id >> 24) & 0xff) {
735 case 0:
cea7e2df 736 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 737 break;
738 case 1:
cea7e2df 739 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 740 break;
741 case 2:
cea7e2df 742 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 743 break;
744 case 3:
cea7e2df 745 __cpu_name[cpu] = "Au1550";
1da177e4 746 break;
e3ad1c23 747 case 4:
cea7e2df 748 __cpu_name[cpu] = "Au1200";
8ff374b9 749 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 750 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 751 break;
752 case 5:
cea7e2df 753 __cpu_name[cpu] = "Au1210";
e3ad1c23 754 break;
1da177e4 755 default:
270717a8 756 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 757 break;
758 }
1da177e4
LT		 759 break;
760 }
761}
762
cea7e2df 763static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 764{
4194318c 765 decode_configs(c);
02cf2119 766
8ff374b9 767 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 768 case PRID_IMP_SB1:
769 c->cputype = CPU_SB1;
cea7e2df 770 __cpu_name[cpu] = "SiByte SB1";
1da177e4 771 /* FPU in pass1 is known to have issues. */
8ff374b9 772 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 773 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 774 break;
93ce2f52
AI		 775 case PRID_IMP_SB1A:
776 c->cputype = CPU_SB1A;
cea7e2df 777 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 778 break;
1da177e4
LT		 779 }
780}
781
cea7e2df 782static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 783{
4194318c 784 decode_configs(c);
8ff374b9 785 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 786 case PRID_IMP_SR71000:
787 c->cputype = CPU_SR71000;
cea7e2df 788 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 789 c->scache.ways = 8;
790 c->tlbsize = 64;
791 break;
792 }
793}
794
cea7e2df 795static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 796{
797 decode_configs(c);
8ff374b9 798 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 799 case PRID_IMP_PR4450:
800 c->cputype = CPU_PR4450;
cea7e2df 801 __cpu_name[cpu] = "Philips PR4450";
a96102be 802 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 803 break;
bdf21b18
PP		 804 }
805}
806
cea7e2df 807static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 808{
809 decode_configs(c);
8ff374b9 810 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 811 case PRID_IMP_BMIPS32_REV4:
812 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 813 c->cputype = CPU_BMIPS32;
814 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 815 set_elf_platform(cpu, "bmips32");
602977b0
KC		 816 break;
817 case PRID_IMP_BMIPS3300:
818 case PRID_IMP_BMIPS3300_ALT:
819 case PRID_IMP_BMIPS3300_BUG:
820 c->cputype = CPU_BMIPS3300;
821 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 822 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 823 break;
824 case PRID_IMP_BMIPS43XX: {
8ff374b9 825 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 826
827 if (rev >= PRID_REV_BMIPS4380_LO &&
828 rev <= PRID_REV_BMIPS4380_HI) {
829 c->cputype = CPU_BMIPS4380;
830 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 831 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 832 } else {
833 c->cputype = CPU_BMIPS4350;
834 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 835 set_elf_platform(cpu, "bmips4350");
602977b0 836 }
0de663ef 837 break;
602977b0
KC		 838 }
839 case PRID_IMP_BMIPS5000:
840 c->cputype = CPU_BMIPS5000;
841 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 842 set_elf_platform(cpu, "bmips5000");
602977b0 843 c->options |= MIPS_CPU_ULRI;
0de663ef 844 break;
1c0c13eb
AJ		 845 }
846}
847
0dd4781b
DD		 848static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
849{
850 decode_configs(c);
8ff374b9 851 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 852 case PRID_IMP_CAVIUM_CN38XX:
853 case PRID_IMP_CAVIUM_CN31XX:
854 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 855 c->cputype = CPU_CAVIUM_OCTEON;
856 __cpu_name[cpu] = "Cavium Octeon";
857 goto platform;
0dd4781b
DD		 858 case PRID_IMP_CAVIUM_CN58XX:
859 case PRID_IMP_CAVIUM_CN56XX:
860 case PRID_IMP_CAVIUM_CN50XX:
861 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 862 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
863 __cpu_name[cpu] = "Cavium Octeon+";
864platform:
c094c99e 865 set_elf_platform(cpu, "octeon");
0dd4781b 866 break;
a1431b61 867 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 868 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 869 case PRID_IMP_CAVIUM_CN66XX:
870 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 871 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 872 c->cputype = CPU_CAVIUM_OCTEON2;
873 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 874 set_elf_platform(cpu, "octeon2");
0e56b385 875 break;
af04bb85
DD		 876 case PRID_IMP_CAVIUM_CN70XX:
877 case PRID_IMP_CAVIUM_CN78XX:
878 c->cputype = CPU_CAVIUM_OCTEON3;
879 __cpu_name[cpu] = "Cavium Octeon III";
880 set_elf_platform(cpu, "octeon3");
881 break;
0dd4781b
DD		 882 default:
883 printk(KERN_INFO "Unknown Octeon chip!\n");
884 c->cputype = CPU_UNKNOWN;
885 break;
886 }
887}
888
83ccf69d
LPC		 889static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
890{
891 decode_configs(c);
892 /* JZRISC does not implement the CP0 counter. */
893 c->options &= ~MIPS_CPU_COUNTER;
8ff374b9 894 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 895 case PRID_IMP_JZRISC:
896 c->cputype = CPU_JZRISC;
897 __cpu_name[cpu] = "Ingenic JZRISC";
898 break;
899 default:
900 panic("Unknown Ingenic Processor ID!");
901 break;
902 }
903}
904
a7117c6b
J		 905static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
906{
907 decode_configs(c);
908
8ff374b9 909 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 910 c->cputype = CPU_ALCHEMY;
911 __cpu_name[cpu] = "Au1300";
912 /* following stuff is not for Alchemy */
913 return;
914 }
915
70342287
RB		 916 c->options = (MIPS_CPU_TLB |
917 MIPS_CPU_4KEX |
a7117c6b 918 MIPS_CPU_COUNTER |
70342287
RB		 919 MIPS_CPU_DIVEC |
920 MIPS_CPU_WATCH |
921 MIPS_CPU_EJTAG |
a7117c6b
J		 922 MIPS_CPU_LLSC);
923
8ff374b9 924 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f
J		 925 case PRID_IMP_NETLOGIC_XLP2XX:
926 c->cputype = CPU_XLP;
927 __cpu_name[cpu] = "Broadcom XLPII";
928 break;
929
2aa54b20
J		 930 case PRID_IMP_NETLOGIC_XLP8XX:
931 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 932 c->cputype = CPU_XLP;
933 __cpu_name[cpu] = "Netlogic XLP";
934 break;
935
a7117c6b
J		 936 case PRID_IMP_NETLOGIC_XLR732:
937 case PRID_IMP_NETLOGIC_XLR716:
938 case PRID_IMP_NETLOGIC_XLR532:
939 case PRID_IMP_NETLOGIC_XLR308:
940 case PRID_IMP_NETLOGIC_XLR532C:
941 case PRID_IMP_NETLOGIC_XLR516C:
942 case PRID_IMP_NETLOGIC_XLR508C:
943 case PRID_IMP_NETLOGIC_XLR308C:
944 c->cputype = CPU_XLR;
945 __cpu_name[cpu] = "Netlogic XLR";
946 break;
947
948 case PRID_IMP_NETLOGIC_XLS608:
949 case PRID_IMP_NETLOGIC_XLS408:
950 case PRID_IMP_NETLOGIC_XLS404:
951 case PRID_IMP_NETLOGIC_XLS208:
952 case PRID_IMP_NETLOGIC_XLS204:
953 case PRID_IMP_NETLOGIC_XLS108:
954 case PRID_IMP_NETLOGIC_XLS104:
955 case PRID_IMP_NETLOGIC_XLS616B:
956 case PRID_IMP_NETLOGIC_XLS608B:
957 case PRID_IMP_NETLOGIC_XLS416B:
958 case PRID_IMP_NETLOGIC_XLS412B:
959 case PRID_IMP_NETLOGIC_XLS408B:
960 case PRID_IMP_NETLOGIC_XLS404B:
961 c->cputype = CPU_XLR;
962 __cpu_name[cpu] = "Netlogic XLS";
963 break;
964
965 default:
a3d4fb2d 966 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 967 c->processor_id);
968 c->cputype = CPU_XLR;
969 break;
970 }
971
a3d4fb2d 972 if (c->cputype == CPU_XLP) {
a96102be 973 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 974 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
975 /* This will be updated again after all threads are woken up */
976 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
977 } else {
a96102be 978 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 979 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
980 }
7777b939 981 c->kscratch_mask = 0xf;
a7117c6b
J		 982}
983
949e51be
DD		 984#ifdef CONFIG_64BIT
985/* For use by uaccess.h */
986u64 __ua_limit;
987EXPORT_SYMBOL(__ua_limit);
988#endif
989
9966db25 990const char *__cpu_name[NR_CPUS];
874fd3b5 991const char *__elf_platform;
9966db25 992
078a55fc 993void cpu_probe(void)
1da177e4
LT		 994{
995 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 996 unsigned int cpu = smp_processor_id();
1da177e4 997
70342287 998 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 999 c->fpu_id = FPIR_IMP_NONE;
1000 c->cputype = CPU_UNKNOWN;
1001
1002 c->processor_id = read_c0_prid();
8ff374b9 1003 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1004 case PRID_COMP_LEGACY:
cea7e2df 1005 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1006 break;
1007 case PRID_COMP_MIPS:
cea7e2df 1008 cpu_probe_mips(c, cpu);
1da177e4
LT		 1009 break;
1010 case PRID_COMP_ALCHEMY:
cea7e2df 1011 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1012 break;
1013 case PRID_COMP_SIBYTE:
cea7e2df 1014 cpu_probe_sibyte(c, cpu);
1da177e4 1015 break;
1c0c13eb 1016 case PRID_COMP_BROADCOM:
cea7e2df 1017 cpu_probe_broadcom(c, cpu);
1c0c13eb 1018 break;
1da177e4 1019 case PRID_COMP_SANDCRAFT:
cea7e2df 1020 cpu_probe_sandcraft(c, cpu);
1da177e4 1021 break;
a92b0588 1022 case PRID_COMP_NXP:
cea7e2df 1023 cpu_probe_nxp(c, cpu);
a3dddd56 1024 break;
0dd4781b
DD		 1025 case PRID_COMP_CAVIUM:
1026 cpu_probe_cavium(c, cpu);
1027 break;
83ccf69d
LPC		 1028 case PRID_COMP_INGENIC:
1029 cpu_probe_ingenic(c, cpu);
1030 break;
a7117c6b
J		 1031 case PRID_COMP_NETLOGIC:
1032 cpu_probe_netlogic(c, cpu);
1033 break;
1da177e4 1034 }
dec8b1ca 1035
cea7e2df
RB		 1036 BUG_ON(!__cpu_name[cpu]);
1037 BUG_ON(c->cputype == CPU_UNKNOWN);
1038
dec8b1ca
FBH		 1039 /*
1040 * Platform code can force the cpu type to optimize code
1041 * generation. In that case be sure the cpu type is correctly
1042 * manually setup otherwise it could trigger some nasty bugs.
1043 */
1044 BUG_ON(current_cpu_type() != c->cputype);
1045
0103d23f
KC		 1046 if (mips_fpu_disabled)
1047 c->options &= ~MIPS_CPU_FPU;
1048
1049 if (mips_dsp_disabled)
ee80f7c7 1050 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1051
4194318c 1052 if (c->options & MIPS_CPU_FPU) {
1da177e4 1053 c->fpu_id = cpu_get_fpu_id();
4194318c 1054
adb37892
DCZ		 1055 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1056 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
4194318c
RB		 1057 if (c->fpu_id & MIPS_FPIR_3D)
1058 c->ases |= MIPS_ASE_MIPS3D;
1059 }
1060 }
9966db25 1061
da4b62cd 1062 if (cpu_has_mips_r2) {
f6771dbb 1063 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1064 /* R2 has Performance Counter Interrupt indicator */
1065 c->options |= MIPS_CPU_PCI;
1066 }
f6771dbb
RB		 1067 else
1068 c->srsets = 1;
91dfc423
GR		 1069
1070 cpu_probe_vmbits(c);
949e51be
DD		 1071
1072#ifdef CONFIG_64BIT
1073 if (cpu == 0)
1074 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1075#endif
1da177e4
LT		 1076}
1077
078a55fc 1078void cpu_report(void)
1da177e4
LT		 1079{
1080 struct cpuinfo_mips *c = &current_cpu_data;
1081
9966db25
RB		 1082 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1083 c->processor_id, cpu_name_string());
1da177e4 1084 if (c->options & MIPS_CPU_FPU)
9966db25 1085 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 1086}
Linux kernel - Deliverables
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