[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c

/*
 * Processor capabilities determination functions.
 *
 * Copyright (C) xxxx  the Anonymous
 * Copyright (C) 2003  Maciej W. Rozycki
 * Copyright (C) 1994 - 2003 Ralf Baechle
 * Copyright (C) 2001 MIPS Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ptrace.h>
#include <linux/stddef.h>

#include <asm/bugs.h>
#include <asm/cpu.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>

/*
 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
 * the implementation of the "wait" feature differs between CPU families. This
 * points to the function that implements CPU specific wait.
 * The wait instruction stops the pipeline and reduces the power consumption of
 * the CPU very much.
 */
void (*cpu_wait)(void) = NULL;

static void r3081_wait(void)
{
	unsigned long cfg = read_c0_conf();
	write_c0_conf(cfg | R30XX_CONF_HALT);
}

static void r39xx_wait(void)
{
	unsigned long cfg = read_c0_conf();
	write_c0_conf(cfg | TX39_CONF_HALT);
}

static void r4k_wait(void)
{
	__asm__(".set\tmips3\n\t"
		"wait\n\t"
		".set\tmips0");
}

/* The Au1xxx wait is available only if using 32khz counter or
 * external timer source, but specifically not CP0 Counter. */
static void au1k_wait(void)
{
	unsigned long addr;
	/* using the wait instruction makes CP0 counter unusable */
	__asm__("la %0,au1k_wait\n\t"
		".set mips3\n\t"
		"cache 0x14,0(%0)\n\t"
		"cache 0x14,32(%0)\n\t"
		"sync\n\t"
		"nop\n\t"
		"wait\n\t"
		"nop\n\t"
		"nop\n\t"
		"nop\n\t"
		"nop\n\t"
		".set mips0\n\t"
		: : "r" (addr));
}

static inline void check_wait(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	printk("Checking for 'wait' instruction... ");
	switch (c->cputype) {
	case CPU_R3081:
	case CPU_R3081E:
		cpu_wait = r3081_wait;
		printk(" available.\n");
		break;
	case CPU_TX3927:
		cpu_wait = r39xx_wait;
		printk(" available.\n");
		break;
	case CPU_R4200:
/*	case CPU_R4300: */
	case CPU_R4600:
	case CPU_R4640:
	case CPU_R4650:
	case CPU_R4700:
	case CPU_R5000:
	case CPU_NEVADA:
	case CPU_RM7000:
	case CPU_RM9000:
	case CPU_TX49XX:
	case CPU_4KC:
	case CPU_4KEC:
	case CPU_4KSC:
	case CPU_5KC:
/*	case CPU_20KC:*/
	case CPU_24K:
	case CPU_25KF:
		cpu_wait = r4k_wait;
		printk(" available.\n");
		break;
	case CPU_AU1000:
	case CPU_AU1100:
	case CPU_AU1500:
	case CPU_AU1550:
	case CPU_AU1200:
		{
			extern int allow_au1k_wait; /* au1000/common/time.c */
			if (allow_au1k_wait) {
				cpu_wait = au1k_wait;
				printk(" available.\n");
			} else
				printk(" unavailable.\n");
		}
		break;
	default:
		printk(" unavailable.\n");
		break;
	}
}

void __init check_bugs32(void)
{
	check_wait();
}

/*
 * Probe whether cpu has config register by trying to play with
 * alternate cache bit and see whether it matters.
 * It's used by cpu_probe to distinguish between R3000A and R3081.
 */
static inline int cpu_has_confreg(void)
{
#ifdef CONFIG_CPU_R3000
	extern unsigned long r3k_cache_size(unsigned long);
	unsigned long size1, size2;
	unsigned long cfg = read_c0_conf();

	size1 = r3k_cache_size(ST0_ISC);
	write_c0_conf(cfg ^ R30XX_CONF_AC);
	size2 = r3k_cache_size(ST0_ISC);
	write_c0_conf(cfg);
	return size1 != size2;
#else
	return 0;
#endif
}

/*
 * Get the FPU Implementation/Revision.
 */
static inline unsigned long cpu_get_fpu_id(void)
{
	unsigned long tmp, fpu_id;

	tmp = read_c0_status();
	__enable_fpu();
	fpu_id = read_32bit_cp1_register(CP1_REVISION);
	write_c0_status(tmp);
	return fpu_id;
}

/*
 * Check the CPU has an FPU the official way.
 */
static inline int __cpu_has_fpu(void)
{
	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
}

#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
		| MIPS_CPU_COUNTER)

static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
{
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_R2000:
		c->cputype = CPU_R2000;
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
		if (__cpu_has_fpu())
			c->options |= MIPS_CPU_FPU;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R3000:
		if ((c->processor_id & 0xff) == PRID_REV_R3000A)
			if (cpu_has_confreg())
				c->cputype = CPU_R3081E;
			else
				c->cputype = CPU_R3000A;
		else
			c->cputype = CPU_R3000;
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
		if (__cpu_has_fpu())
			c->options |= MIPS_CPU_FPU;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R4000:
		if (read_c0_config() & CONF_SC) {
			if ((c->processor_id & 0xff) >= PRID_REV_R4400)
				c->cputype = CPU_R4400PC;
			else
				c->cputype = CPU_R4000PC;
		} else {
			if ((c->processor_id & 0xff) >= PRID_REV_R4400)
				c->cputype = CPU_R4400SC;
			else
				c->cputype = CPU_R4000SC;
		}

		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_VCE |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_VR41XX:
		switch (c->processor_id & 0xf0) {
		case PRID_REV_VR4111:
			c->cputype = CPU_VR4111;
			break;
		case PRID_REV_VR4121:
			c->cputype = CPU_VR4121;
			break;
		case PRID_REV_VR4122:
			if ((c->processor_id & 0xf) < 0x3)
				c->cputype = CPU_VR4122;
			else
				c->cputype = CPU_VR4181A;
			break;
		case PRID_REV_VR4130:
			if ((c->processor_id & 0xf) < 0x4)
				c->cputype = CPU_VR4131;
			else
				c->cputype = CPU_VR4133;
			break;
		default:
			printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
			c->cputype = CPU_VR41XX;
			break;
		}
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R4300:
		c->cputype = CPU_R4300;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R4600:
		c->cputype = CPU_R4600;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	#if 0
 	case PRID_IMP_R4650:
		/*
		 * This processor doesn't have an MMU, so it's not
		 * "real easy" to run Linux on it. It is left purely
		 * for documentation.  Commented out because it shares
		 * it's c0_prid id number with the TX3900.
		 */
 		c->cputype = CPU_R4650;
	 	c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
	        c->tlbsize = 48;
		break;
	#endif
	case PRID_IMP_TX39:
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB;

		if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
			c->cputype = CPU_TX3927;
			c->tlbsize = 64;
		} else {
			switch (c->processor_id & 0xff) {
			case PRID_REV_TX3912:
				c->cputype = CPU_TX3912;
				c->tlbsize = 32;
				break;
			case PRID_REV_TX3922:
				c->cputype = CPU_TX3922;
				c->tlbsize = 64;
				break;
			default:
				c->cputype = CPU_UNKNOWN;
				break;
			}
		}
		break;
	case PRID_IMP_R4700:
		c->cputype = CPU_R4700;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_TX49:
		c->cputype = CPU_TX49XX;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_LLSC;
		if (!(c->processor_id & 0x08))
			c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5000:
		c->cputype = CPU_R5000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5432:
		c->cputype = CPU_R5432;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5500:
		c->cputype = CPU_R5500;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_NEVADA:
		c->cputype = CPU_NEVADA;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R6000:
		c->cputype = CPU_R6000;
		c->isa_level = MIPS_CPU_ISA_II;
		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R6000A:
		c->cputype = CPU_R6000A;
		c->isa_level = MIPS_CPU_ISA_II;
		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_RM7000:
		c->cputype = CPU_RM7000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		/*
		 * Undocumented RM7000:  Bit 29 in the info register of
		 * the RM7000 v2.0 indicates if the TLB has 48 or 64
		 * entries.
		 *
		 * 29      1 =>    64 entry JTLB
		 *         0 =>    48 entry JTLB
		 */
		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
		break;
	case PRID_IMP_RM9000:
		c->cputype = CPU_RM9000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		/*
		 * Bit 29 in the info register of the RM9000
		 * indicates if the TLB has 48 or 64 entries.
		 *
		 * 29      1 =>    64 entry JTLB
		 *         0 =>    48 entry JTLB
		 */
		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
		break;
	case PRID_IMP_R8000:
		c->cputype = CPU_R8000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
		break;
	case PRID_IMP_R10000:
		c->cputype = CPU_R10000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R12000:
		c->cputype = CPU_R12000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
	}
}

static inline void decode_config1(struct cpuinfo_mips *c)
{
	unsigned long config0 = read_c0_config();
	unsigned long config1;

	if ((config0 & (1 << 31)) == 0)
		return;			/* actually wort a panic() */

	/* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
	c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
		MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
	config1 = read_c0_config1();
	if (config1 & (1 << 3))
		c->options |= MIPS_CPU_WATCH;
	if (config1 & (1 << 2))
		c->options |= MIPS_CPU_MIPS16;
	if (config1 & (1 << 1))
		c->options |= MIPS_CPU_EJTAG;
	if (config1 & 1) {
		c->options |= MIPS_CPU_FPU;
		c->options |= MIPS_CPU_32FPR;
	}
	c->scache.flags = MIPS_CACHE_NOT_PRESENT;

	c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
}

static inline void cpu_probe_mips(struct cpuinfo_mips *c)
{
	decode_config1(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_4KC:
		c->cputype = CPU_4KC;
		c->isa_level = MIPS_CPU_ISA_M32;
		break;
	case PRID_IMP_4KEC:
		c->cputype = CPU_4KEC;
		c->isa_level = MIPS_CPU_ISA_M32;
		break;
	case PRID_IMP_4KSC:
		c->cputype = CPU_4KSC;
		c->isa_level = MIPS_CPU_ISA_M32;
		break;
	case PRID_IMP_5KC:
		c->cputype = CPU_5KC;
		c->isa_level = MIPS_CPU_ISA_M64;
		break;
	case PRID_IMP_20KC:
		c->cputype = CPU_20KC;
		c->isa_level = MIPS_CPU_ISA_M64;
		break;
	case PRID_IMP_24K:
		c->cputype = CPU_24K;
		c->isa_level = MIPS_CPU_ISA_M32;
		break;
	case PRID_IMP_25KF:
		c->cputype = CPU_25KF;
		c->isa_level = MIPS_CPU_ISA_M64;
		/* Probe for L2 cache */
		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
		break;
	}
}

static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
{
	decode_config1(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_AU1_REV1:
	case PRID_IMP_AU1_REV2:
		switch ((c->processor_id >> 24) & 0xff) {
		case 0:
 			c->cputype = CPU_AU1000;
			break;
		case 1:
			c->cputype = CPU_AU1500;
			break;
		case 2:
			c->cputype = CPU_AU1100;
			break;
		case 3:
			c->cputype = CPU_AU1550;
			break;
		case 4:
			c->cputype = CPU_AU1200;
			break;
		default:
			panic("Unknown Au Core!");
			break;
		}
		c->isa_level = MIPS_CPU_ISA_M32;
		break;
	}
}

static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
{
	decode_config1(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_SB1:
		c->cputype = CPU_SB1;
		c->isa_level = MIPS_CPU_ISA_M64;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		             MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
		             MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
		/* FPU in pass1 is known to have issues. */
		c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
#endif
		break;
	}
}

static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
{
	decode_config1(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_SR71000:
		c->cputype = CPU_SR71000;
		c->isa_level = MIPS_CPU_ISA_M64;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		             MIPS_CPU_4KTLB | MIPS_CPU_FPU |
		             MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
		c->scache.ways = 8;
		c->tlbsize = 64;
		break;
	}
}

__init void cpu_probe(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	c->processor_id	= PRID_IMP_UNKNOWN;
	c->fpu_id	= FPIR_IMP_NONE;
	c->cputype	= CPU_UNKNOWN;

	c->processor_id = read_c0_prid();
	switch (c->processor_id & 0xff0000) {
	case PRID_COMP_LEGACY:
		cpu_probe_legacy(c);
		break;
	case PRID_COMP_MIPS:
		cpu_probe_mips(c);
		break;
	case PRID_COMP_ALCHEMY:
		cpu_probe_alchemy(c);
		break;
	case PRID_COMP_SIBYTE:
		cpu_probe_sibyte(c);
		break;

	case PRID_COMP_SANDCRAFT:
		cpu_probe_sandcraft(c);
		break;
	default:
		c->cputype = CPU_UNKNOWN;
	}
	if (c->options & MIPS_CPU_FPU)
		c->fpu_id = cpu_get_fpu_id();
}

__init void cpu_report(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	printk("CPU revision is: %08x\n", c->processor_id);
	if (c->options & MIPS_CPU_FPU)
		printk("FPU revision is: %08x\n", c->fpu_id);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Processor capabilities determination functions.
	3	*
	4	* Copyright (C) xxxx the Anonymous
	5	* Copyright (C) 2003 Maciej W. Rozycki
	6	* Copyright (C) 1994 - 2003 Ralf Baechle
	7	* Copyright (C) 2001 MIPS Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14	#include <linux/config.h>
	15	#include <linux/init.h>
	16	#include <linux/kernel.h>
	17	#include <linux/ptrace.h>
	18	#include <linux/stddef.h>
	19
	20	#include <asm/bugs.h>
	21	#include <asm/cpu.h>
	22	#include <asm/fpu.h>
	23	#include <asm/mipsregs.h>
	24	#include <asm/system.h>
	25
	26	/*
	27	* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
	28	* the implementation of the "wait" feature differs between CPU families. This
	29	* points to the function that implements CPU specific wait.
	30	* The wait instruction stops the pipeline and reduces the power consumption of
	31	* the CPU very much.
	32	*/
	33	void (*cpu_wait)(void) = NULL;
	34
	35	static void r3081_wait(void)
	36	{
	37	unsigned long cfg = read_c0_conf();
	38	write_c0_conf(cfg \| R30XX_CONF_HALT);
	39	}
	40
	41	static void r39xx_wait(void)
	42	{
	43	unsigned long cfg = read_c0_conf();
	44	write_c0_conf(cfg \| TX39_CONF_HALT);
	45	}
	46
	47	static void r4k_wait(void)
	48	{
	49	__asm__(".set\tmips3\n\t"
	50	"wait\n\t"
	51	".set\tmips0");
	52	}
	53
494900af PP	54	/* The Au1xxx wait is available only if using 32khz counter or
	55	* external timer source, but specifically not CP0 Counter. */
	56	static void au1k_wait(void)
1da177e4	57	{
494900af	58	unsigned long addr;
1da177e4	59	/* using the wait instruction makes CP0 counter unusable */
494900af PP	60	__asm__("la %0,au1k_wait\n\t"
	61	".set mips3\n\t"
	62	"cache 0x14,0(%0)\n\t"
	63	"cache 0x14,32(%0)\n\t"
	64	"sync\n\t"
	65	"nop\n\t"
1da177e4 LT	66	"wait\n\t"
	67	"nop\n\t"
	68	"nop\n\t"
	69	"nop\n\t"
	70	"nop\n\t"
494900af PP	71	".set mips0\n\t"
494900af PP	72	: : "r" (addr));
1da177e4 LT	73	}
	74
	75	static inline void check_wait(void)
	76	{
	77	struct cpuinfo_mips *c = &current_cpu_data;
	78
	79	printk("Checking for 'wait' instruction... ");
	80	switch (c->cputype) {
	81	case CPU_R3081:
	82	case CPU_R3081E:
	83	cpu_wait = r3081_wait;
	84	printk(" available.\n");
	85	break;
	86	case CPU_TX3927:
	87	cpu_wait = r39xx_wait;
	88	printk(" available.\n");
	89	break;
	90	case CPU_R4200:
	91	/* case CPU_R4300: */
	92	case CPU_R4600:
	93	case CPU_R4640:
	94	case CPU_R4650:
	95	case CPU_R4700:
	96	case CPU_R5000:
	97	case CPU_NEVADA:
	98	case CPU_RM7000:
	99	case CPU_RM9000:
	100	case CPU_TX49XX:
	101	case CPU_4KC:
	102	case CPU_4KEC:
	103	case CPU_4KSC:
	104	case CPU_5KC:
	105	/* case CPU_20KC:*/
	106	case CPU_24K:
	107	case CPU_25KF:
	108	cpu_wait = r4k_wait;
	109	printk(" available.\n");
	110	break;
1da177e4 LT	111	case CPU_AU1000:
	112	case CPU_AU1100:
	113	case CPU_AU1500:
e3ad1c23 PP	114	case CPU_AU1550:
e3ad1c23 PP	115	case CPU_AU1200:
494900af PP	116	{
	117	extern int allow_au1k_wait; /* au1000/common/time.c */
	118	if (allow_au1k_wait) {
	119	cpu_wait = au1k_wait;
	120	printk(" available.\n");
	121	} else
	122	printk(" unavailable.\n");
1da177e4 LT	123	}
1da177e4 LT	124	break;
1da177e4 LT	125	default:
	126	printk(" unavailable.\n");
	127	break;
	128	}
	129	}
	130
	131	void __init check_bugs32(void)
	132	{
	133	check_wait();
	134	}
	135
	136	/*
	137	* Probe whether cpu has config register by trying to play with
	138	* alternate cache bit and see whether it matters.
	139	* It's used by cpu_probe to distinguish between R3000A and R3081.
	140	*/
	141	static inline int cpu_has_confreg(void)
	142	{
	143	#ifdef CONFIG_CPU_R3000
	144	extern unsigned long r3k_cache_size(unsigned long);
	145	unsigned long size1, size2;
	146	unsigned long cfg = read_c0_conf();
	147
	148	size1 = r3k_cache_size(ST0_ISC);
	149	write_c0_conf(cfg ^ R30XX_CONF_AC);
	150	size2 = r3k_cache_size(ST0_ISC);
	151	write_c0_conf(cfg);
	152	return size1 != size2;
	153	#else
	154	return 0;
	155	#endif
	156	}
	157
	158	/*
	159	* Get the FPU Implementation/Revision.
	160	*/
	161	static inline unsigned long cpu_get_fpu_id(void)
	162	{
	163	unsigned long tmp, fpu_id;
	164
	165	tmp = read_c0_status();
	166	__enable_fpu();
	167	fpu_id = read_32bit_cp1_register(CP1_REVISION);
	168	write_c0_status(tmp);
	169	return fpu_id;
	170	}
	171
	172	/*
	173	* Check the CPU has an FPU the official way.
	174	*/
	175	static inline int __cpu_has_fpu(void)
	176	{
	177	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
	178	}
	179
	180	#define R4K_OPTS (MIPS_CPU_TLB \| MIPS_CPU_4KEX \| MIPS_CPU_4KTLB \
	181	\| MIPS_CPU_COUNTER)
	182
	183	static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
	184	{
	185	switch (c->processor_id & 0xff00) {
	186	case PRID_IMP_R2000:
	187	c->cputype = CPU_R2000;
	188	c->isa_level = MIPS_CPU_ISA_I;
189	c->options = MIPS_CPU_TLB \| MIPS_CPU_NOFPUEX;
190	if (__cpu_has_fpu())
191	c->options \|= MIPS_CPU_FPU;
192	c->tlbsize = 64;
193	break;
194	case PRID_IMP_R3000:
195	if ((c->processor_id & 0xff) == PRID_REV_R3000A)
196	if (cpu_has_confreg())
197	c->cputype = CPU_R3081E;
198	else
199	c->cputype = CPU_R3000A;
200	else
201	c->cputype = CPU_R3000;
202	c->isa_level = MIPS_CPU_ISA_I;
203	c->options = MIPS_CPU_TLB \| MIPS_CPU_NOFPUEX;
204	if (__cpu_has_fpu())
205	c->options \|= MIPS_CPU_FPU;
206	c->tlbsize = 64;
207	break;
208	case PRID_IMP_R4000:
209	if (read_c0_config() & CONF_SC) {
210	if ((c->processor_id & 0xff) >= PRID_REV_R4400)
211	c->cputype = CPU_R4400PC;
212	else
213	c->cputype = CPU_R4000PC;
214	} else {
215	if ((c->processor_id & 0xff) >= PRID_REV_R4400)
216	c->cputype = CPU_R4400SC;
217	else
218	c->cputype = CPU_R4000SC;
219	}
220
221	c->isa_level = MIPS_CPU_ISA_III;
222	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
223	MIPS_CPU_WATCH \| MIPS_CPU_VCE \|
224	MIPS_CPU_LLSC;
225	c->tlbsize = 48;
226	break;
227	case PRID_IMP_VR41XX:
228	switch (c->processor_id & 0xf0) {
1da177e4 LT	229	case PRID_REV_VR4111:
	230	c->cputype = CPU_VR4111;
	231	break;
1da177e4 LT	232	case PRID_REV_VR4121:
	233	c->cputype = CPU_VR4121;
	234	break;
	235	case PRID_REV_VR4122:
	236	if ((c->processor_id & 0xf) < 0x3)
	237	c->cputype = CPU_VR4122;
	238	else
	239	c->cputype = CPU_VR4181A;
	240	break;
	241	case PRID_REV_VR4130:
	242	if ((c->processor_id & 0xf) < 0x4)
	243	c->cputype = CPU_VR4131;
	244	else
	245	c->cputype = CPU_VR4133;
	246	break;
	247	default:
	248	printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
	249	c->cputype = CPU_VR41XX;
	250	break;
	251	}
	252	c->isa_level = MIPS_CPU_ISA_III;
	253	c->options = R4K_OPTS;
	254	c->tlbsize = 32;
	255	break;
	256	case PRID_IMP_R4300:
	257	c->cputype = CPU_R4300;
	258	c->isa_level = MIPS_CPU_ISA_III;
	259	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	260	MIPS_CPU_LLSC;
	261	c->tlbsize = 32;
	262	break;
	263	case PRID_IMP_R4600:
	264	c->cputype = CPU_R4600;
	265	c->isa_level = MIPS_CPU_ISA_III;
	266	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_LLSC;
	267	c->tlbsize = 48;
	268	break;
	269	#if 0
	270	case PRID_IMP_R4650:
	271	/*
	272	* This processor doesn't have an MMU, so it's not
	273	* "real easy" to run Linux on it. It is left purely
	274	* for documentation. Commented out because it shares
	275	* it's c0_prid id number with the TX3900.
	276	*/
	277	c->cputype = CPU_R4650;
	278	c->isa_level = MIPS_CPU_ISA_III;
	279	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_LLSC;
	280	c->tlbsize = 48;
	281	break;
	282	#endif
	283	case PRID_IMP_TX39:
	284	c->isa_level = MIPS_CPU_ISA_I;
	285	c->options = MIPS_CPU_TLB;
	286
	287	if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
	288	c->cputype = CPU_TX3927;
	289	c->tlbsize = 64;
	290	} else {
	291	switch (c->processor_id & 0xff) {
	292	case PRID_REV_TX3912:
	293	c->cputype = CPU_TX3912;
	294	c->tlbsize = 32;
	295	break;
296	case PRID_REV_TX3922:
297	c->cputype = CPU_TX3922;
298	c->tlbsize = 64;
299	break;
300	default:
301	c->cputype = CPU_UNKNOWN;
302	break;
303	}
304	}
305	break;
306	case PRID_IMP_R4700:
307	c->cputype = CPU_R4700;
308	c->isa_level = MIPS_CPU_ISA_III;
309	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
310	MIPS_CPU_LLSC;
311	c->tlbsize = 48;
312	break;
313	case PRID_IMP_TX49:
314	c->cputype = CPU_TX49XX;
315	c->isa_level = MIPS_CPU_ISA_III;
316	c->options = R4K_OPTS \| MIPS_CPU_LLSC;
317	if (!(c->processor_id & 0x08))
318	c->options \|= MIPS_CPU_FPU \| MIPS_CPU_32FPR;
319	c->tlbsize = 48;
320	break;
321	case PRID_IMP_R5000:
322	c->cputype = CPU_R5000;
323	c->isa_level = MIPS_CPU_ISA_IV;
324	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
325	MIPS_CPU_LLSC;
326	c->tlbsize = 48;
327	break;
328	case PRID_IMP_R5432:
329	c->cputype = CPU_R5432;
330	c->isa_level = MIPS_CPU_ISA_IV;
331	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
332	MIPS_CPU_WATCH \| MIPS_CPU_LLSC;
333	c->tlbsize = 48;
334	break;
335	case PRID_IMP_R5500:
336	c->cputype = CPU_R5500;
337	c->isa_level = MIPS_CPU_ISA_IV;
338	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
339	MIPS_CPU_WATCH \| MIPS_CPU_LLSC;
340	c->tlbsize = 48;
341	break;
342	case PRID_IMP_NEVADA:
343	c->cputype = CPU_NEVADA;
344	c->isa_level = MIPS_CPU_ISA_IV;
345	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
346	MIPS_CPU_DIVEC \| MIPS_CPU_LLSC;
347	c->tlbsize = 48;
348	break;
349	case PRID_IMP_R6000:
350	c->cputype = CPU_R6000;
351	c->isa_level = MIPS_CPU_ISA_II;
352	c->options = MIPS_CPU_TLB \| MIPS_CPU_FPU \|
353	MIPS_CPU_LLSC;
354	c->tlbsize = 32;
355	break;
356	case PRID_IMP_R6000A:
357	c->cputype = CPU_R6000A;
358	c->isa_level = MIPS_CPU_ISA_II;
359	c->options = MIPS_CPU_TLB \| MIPS_CPU_FPU \|
360	MIPS_CPU_LLSC;
361	c->tlbsize = 32;
362	break;
363	case PRID_IMP_RM7000:
364	c->cputype = CPU_RM7000;
365	c->isa_level = MIPS_CPU_ISA_IV;
366	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
367	MIPS_CPU_LLSC;
368	/*
369	* Undocumented RM7000: Bit 29 in the info register of
370	* the RM7000 v2.0 indicates if the TLB has 48 or 64
371	* entries.
372	*
373	* 29 1 => 64 entry JTLB
374	* 0 => 48 entry JTLB
375	*/
376	c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
377	break;
378	case PRID_IMP_RM9000:
379	c->cputype = CPU_RM9000;
380	c->isa_level = MIPS_CPU_ISA_IV;
381	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
382	MIPS_CPU_LLSC;
383	/*
384	* Bit 29 in the info register of the RM9000
385	* indicates if the TLB has 48 or 64 entries.
386	*
387	* 29 1 => 64 entry JTLB
388	* 0 => 48 entry JTLB
389	*/
390	c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
391	break;
392	case PRID_IMP_R8000:
393	c->cputype = CPU_R8000;
394	c->isa_level = MIPS_CPU_ISA_IV;
395	c->options = MIPS_CPU_TLB \| MIPS_CPU_4KEX \|
396	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
397	MIPS_CPU_LLSC;
398	c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
399	break;
400	case PRID_IMP_R10000:
401	c->cputype = CPU_R10000;
402	c->isa_level = MIPS_CPU_ISA_IV;
403	c->options = MIPS_CPU_TLB \| MIPS_CPU_4KEX \|
404	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
405	MIPS_CPU_COUNTER \| MIPS_CPU_WATCH \|
406	MIPS_CPU_LLSC;
407	c->tlbsize = 64;
408	break;
409	case PRID_IMP_R12000:
410	c->cputype = CPU_R12000;
411	c->isa_level = MIPS_CPU_ISA_IV;
412	c->options = MIPS_CPU_TLB \| MIPS_CPU_4KEX \|
413	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
414	MIPS_CPU_COUNTER \| MIPS_CPU_WATCH \|
415	MIPS_CPU_LLSC;
416	c->tlbsize = 64;
417	break;
418	}
419	}
420
421	static inline void decode_config1(struct cpuinfo_mips *c)
422	{
423	unsigned long config0 = read_c0_config();
424	unsigned long config1;
425
426	if ((config0 & (1 << 31)) == 0)
427	return; /* actually wort a panic() */
428
429	/* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
430	c->options = MIPS_CPU_TLB \| MIPS_CPU_4KEX \|
431	MIPS_CPU_4KTLB \| MIPS_CPU_COUNTER \| MIPS_CPU_DIVEC \|
432	MIPS_CPU_LLSC \| MIPS_CPU_MCHECK;
433	config1 = read_c0_config1();
434	if (config1 & (1 << 3))
435	c->options \|= MIPS_CPU_WATCH;
436	if (config1 & (1 << 2))
437	c->options \|= MIPS_CPU_MIPS16;
438	if (config1 & (1 << 1))
439	c->options \|= MIPS_CPU_EJTAG;
440	if (config1 & 1) {
441	c->options \|= MIPS_CPU_FPU;
442	c->options \|= MIPS_CPU_32FPR;
443	}
444	c->scache.flags = MIPS_CACHE_NOT_PRESENT;
445
446	c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
447	}
448
449	static inline void cpu_probe_mips(struct cpuinfo_mips *c)
450	{
451	decode_config1(c);
452	switch (c->processor_id & 0xff00) {
453	case PRID_IMP_4KC:
454	c->cputype = CPU_4KC;
455	c->isa_level = MIPS_CPU_ISA_M32;
456	break;
457	case PRID_IMP_4KEC:
458	c->cputype = CPU_4KEC;
459	c->isa_level = MIPS_CPU_ISA_M32;
460	break;
461	case PRID_IMP_4KSC:
462	c->cputype = CPU_4KSC;
463	c->isa_level = MIPS_CPU_ISA_M32;
464	break;
465	case PRID_IMP_5KC:
466	c->cputype = CPU_5KC;
467	c->isa_level = MIPS_CPU_ISA_M64;
468	break;
469	case PRID_IMP_20KC:
470	c->cputype = CPU_20KC;
471	c->isa_level = MIPS_CPU_ISA_M64;
472	break;
473	case PRID_IMP_24K:
474	c->cputype = CPU_24K;
475	c->isa_level = MIPS_CPU_ISA_M32;
476	break;
477	case PRID_IMP_25KF:
478	c->cputype = CPU_25KF;
479	c->isa_level = MIPS_CPU_ISA_M64;
480	/* Probe for L2 cache */
481	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
482	break;
483	}
484	}
485
486	static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
487	{
488	decode_config1(c);
489	switch (c->processor_id & 0xff00) {
490	case PRID_IMP_AU1_REV1:
491	case PRID_IMP_AU1_REV2:
492	switch ((c->processor_id >> 24) & 0xff) {
493	case 0:
494	c->cputype = CPU_AU1000;
495	break;
496	case 1:
497	c->cputype = CPU_AU1500;
498	break;
499	case 2:
500	c->cputype = CPU_AU1100;
501	break;
502	case 3:
503	c->cputype = CPU_AU1550;
504	break;
e3ad1c23 PP	505	case 4:
	506	c->cputype = CPU_AU1200;
	507	break;
1da177e4 LT	508	default:
	509	panic("Unknown Au Core!");
	510	break;
	511	}
	512	c->isa_level = MIPS_CPU_ISA_M32;
	513	break;
	514	}
	515	}
	516
	517	static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
	518	{
	519	decode_config1(c);
	520	switch (c->processor_id & 0xff00) {
	521	case PRID_IMP_SB1:
	522	c->cputype = CPU_SB1;
	523	c->isa_level = MIPS_CPU_ISA_M64;
	524	c->options = MIPS_CPU_TLB \| MIPS_CPU_4KEX \|
	525	MIPS_CPU_COUNTER \| MIPS_CPU_DIVEC \|
	526	MIPS_CPU_MCHECK \| MIPS_CPU_EJTAG \|
	527	MIPS_CPU_WATCH \| MIPS_CPU_LLSC;
	528	#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
	529	/* FPU in pass1 is known to have issues. */
	530	c->options \|= MIPS_CPU_FPU \| MIPS_CPU_32FPR;
	531	#endif
	532	break;
	533	}
	534	}
	535
	536	static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
	537	{
	538	decode_config1(c);
	539	switch (c->processor_id & 0xff00) {
	540	case PRID_IMP_SR71000:
	541	c->cputype = CPU_SR71000;
	542	c->isa_level = MIPS_CPU_ISA_M64;
	543	c->options = MIPS_CPU_TLB \| MIPS_CPU_4KEX \|
	544	MIPS_CPU_4KTLB \| MIPS_CPU_FPU \|
	545	MIPS_CPU_COUNTER \| MIPS_CPU_MCHECK;
	546	c->scache.ways = 8;
	547	c->tlbsize = 64;
	548	break;
	549	}
	550	}
	551
	552	__init void cpu_probe(void)
	553	{
	554	struct cpuinfo_mips *c = &current_cpu_data;
	555
	556	c->processor_id = PRID_IMP_UNKNOWN;
	557	c->fpu_id = FPIR_IMP_NONE;
	558	c->cputype = CPU_UNKNOWN;
	559
	560	c->processor_id = read_c0_prid();
	561	switch (c->processor_id & 0xff0000) {
	562	case PRID_COMP_LEGACY:
	563	cpu_probe_legacy(c);
	564	break;
	565	case PRID_COMP_MIPS:
	566	cpu_probe_mips(c);
	567	break;
	568	case PRID_COMP_ALCHEMY:
	569	cpu_probe_alchemy(c);
	570	break;
	571	case PRID_COMP_SIBYTE:
572	cpu_probe_sibyte(c);
573	break;
574
575	case PRID_COMP_SANDCRAFT:
576	cpu_probe_sandcraft(c);
577	break;
578	default:
579	c->cputype = CPU_UNKNOWN;
580	}
581	if (c->options & MIPS_CPU_FPU)
582	c->fpu_id = cpu_get_fpu_id();
583	}
584
585	__init void cpu_report(void)
586	{
587	struct cpuinfo_mips *c = &current_cpu_data;
588
589	printk("CPU revision is: %08x\n", c->processor_id);
590	if (c->options & MIPS_CPU_FPU)
591	printk("FPU revision is: %08x\n", c->fpu_id);
592	}