Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Processor capabilities determination functions. | |
3 | * | |
4 | * Copyright (C) xxxx the Anonymous | |
010b853b | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
4194318c | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
4194318c | 7 | * Copyright (C) 2001, 2004 MIPS Inc. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ptrace.h> | |
17 | #include <linux/stddef.h> | |
18 | ||
5759906c | 19 | #include <asm/bugs.h> |
1da177e4 LT |
20 | #include <asm/cpu.h> |
21 | #include <asm/fpu.h> | |
22 | #include <asm/mipsregs.h> | |
23 | #include <asm/system.h> | |
654f57bf | 24 | #include <asm/watch.h> |
1da177e4 LT |
25 | |
26 | /* | |
27 | * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, | |
28 | * the implementation of the "wait" feature differs between CPU families. This | |
29 | * points to the function that implements CPU specific wait. | |
30 | * The wait instruction stops the pipeline and reduces the power consumption of | |
31 | * the CPU very much. | |
32 | */ | |
33 | void (*cpu_wait)(void) = NULL; | |
34 | ||
35 | static void r3081_wait(void) | |
36 | { | |
37 | unsigned long cfg = read_c0_conf(); | |
38 | write_c0_conf(cfg | R30XX_CONF_HALT); | |
39 | } | |
40 | ||
41 | static void r39xx_wait(void) | |
42 | { | |
60a6c377 AN |
43 | local_irq_disable(); |
44 | if (!need_resched()) | |
45 | write_c0_conf(read_c0_conf() | TX39_CONF_HALT); | |
46 | local_irq_enable(); | |
1da177e4 LT |
47 | } |
48 | ||
c65a5480 | 49 | extern void r4k_wait(void); |
60a6c377 AN |
50 | |
51 | /* | |
52 | * This variant is preferable as it allows testing need_resched and going to | |
53 | * sleep depending on the outcome atomically. Unfortunately the "It is | |
54 | * implementation-dependent whether the pipeline restarts when a non-enabled | |
55 | * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes | |
56 | * using this version a gamble. | |
57 | */ | |
8531a35e | 58 | void r4k_wait_irqoff(void) |
60a6c377 AN |
59 | { |
60 | local_irq_disable(); | |
61 | if (!need_resched()) | |
8531a35e KK |
62 | __asm__(" .set push \n" |
63 | " .set mips3 \n" | |
60a6c377 | 64 | " wait \n" |
8531a35e | 65 | " .set pop \n"); |
60a6c377 | 66 | local_irq_enable(); |
8531a35e KK |
67 | __asm__(" .globl __pastwait \n" |
68 | "__pastwait: \n"); | |
69 | return; | |
1da177e4 LT |
70 | } |
71 | ||
5a812999 RB |
72 | /* |
73 | * The RM7000 variant has to handle erratum 38. The workaround is to not | |
74 | * have any pending stores when the WAIT instruction is executed. | |
75 | */ | |
76 | static void rm7k_wait_irqoff(void) | |
77 | { | |
78 | local_irq_disable(); | |
79 | if (!need_resched()) | |
80 | __asm__( | |
81 | " .set push \n" | |
82 | " .set mips3 \n" | |
83 | " .set noat \n" | |
84 | " mfc0 $1, $12 \n" | |
85 | " sync \n" | |
86 | " mtc0 $1, $12 # stalls until W stage \n" | |
87 | " wait \n" | |
88 | " mtc0 $1, $12 # stalls until W stage \n" | |
89 | " .set pop \n"); | |
90 | local_irq_enable(); | |
91 | } | |
92 | ||
494900af PP |
93 | /* The Au1xxx wait is available only if using 32khz counter or |
94 | * external timer source, but specifically not CP0 Counter. */ | |
fe359bf5 | 95 | int allow_au1k_wait; |
10f650db | 96 | |
494900af | 97 | static void au1k_wait(void) |
1da177e4 | 98 | { |
1da177e4 | 99 | /* using the wait instruction makes CP0 counter unusable */ |
60a6c377 AN |
100 | __asm__(" .set mips3 \n" |
101 | " cache 0x14, 0(%0) \n" | |
102 | " cache 0x14, 32(%0) \n" | |
103 | " sync \n" | |
104 | " nop \n" | |
105 | " wait \n" | |
106 | " nop \n" | |
107 | " nop \n" | |
108 | " nop \n" | |
109 | " nop \n" | |
110 | " .set mips0 \n" | |
10f650db | 111 | : : "r" (au1k_wait)); |
1da177e4 LT |
112 | } |
113 | ||
55d04dff RB |
114 | static int __initdata nowait = 0; |
115 | ||
f49a747c | 116 | static int __init wait_disable(char *s) |
55d04dff RB |
117 | { |
118 | nowait = 1; | |
119 | ||
120 | return 1; | |
121 | } | |
122 | ||
123 | __setup("nowait", wait_disable); | |
124 | ||
c65a5480 | 125 | void __init check_wait(void) |
1da177e4 LT |
126 | { |
127 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
128 | ||
55d04dff | 129 | if (nowait) { |
c2379230 | 130 | printk("Wait instruction disabled.\n"); |
55d04dff RB |
131 | return; |
132 | } | |
133 | ||
1da177e4 LT |
134 | switch (c->cputype) { |
135 | case CPU_R3081: | |
136 | case CPU_R3081E: | |
137 | cpu_wait = r3081_wait; | |
1da177e4 LT |
138 | break; |
139 | case CPU_TX3927: | |
140 | cpu_wait = r39xx_wait; | |
1da177e4 LT |
141 | break; |
142 | case CPU_R4200: | |
143 | /* case CPU_R4300: */ | |
144 | case CPU_R4600: | |
145 | case CPU_R4640: | |
146 | case CPU_R4650: | |
147 | case CPU_R4700: | |
148 | case CPU_R5000: | |
149 | case CPU_NEVADA: | |
1da177e4 LT |
150 | case CPU_4KC: |
151 | case CPU_4KEC: | |
152 | case CPU_4KSC: | |
153 | case CPU_5KC: | |
1da177e4 | 154 | case CPU_25KF: |
4b3e975e | 155 | case CPU_PR4450: |
1c0c13eb | 156 | case CPU_BCM3302: |
0dd4781b | 157 | case CPU_CAVIUM_OCTEON: |
4b3e975e RB |
158 | cpu_wait = r4k_wait; |
159 | break; | |
160 | ||
5a812999 RB |
161 | case CPU_RM7000: |
162 | cpu_wait = rm7k_wait_irqoff; | |
163 | break; | |
164 | ||
4b3e975e | 165 | case CPU_24K: |
bbc7f22f | 166 | case CPU_34K: |
39b8d525 | 167 | case CPU_1004K: |
4b3e975e RB |
168 | cpu_wait = r4k_wait; |
169 | if (read_c0_config7() & MIPS_CONF7_WII) | |
170 | cpu_wait = r4k_wait_irqoff; | |
171 | break; | |
172 | ||
c620953c | 173 | case CPU_74K: |
1da177e4 | 174 | cpu_wait = r4k_wait; |
4b3e975e RB |
175 | if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) |
176 | cpu_wait = r4k_wait_irqoff; | |
1da177e4 | 177 | break; |
4b3e975e | 178 | |
60a6c377 AN |
179 | case CPU_TX49XX: |
180 | cpu_wait = r4k_wait_irqoff; | |
60a6c377 | 181 | break; |
1da177e4 LT |
182 | case CPU_AU1000: |
183 | case CPU_AU1100: | |
184 | case CPU_AU1500: | |
e3ad1c23 PP |
185 | case CPU_AU1550: |
186 | case CPU_AU1200: | |
237cfee1 ML |
187 | case CPU_AU1210: |
188 | case CPU_AU1250: | |
c2379230 | 189 | if (allow_au1k_wait) |
fe359bf5 | 190 | cpu_wait = au1k_wait; |
1da177e4 | 191 | break; |
c8eae71d RB |
192 | case CPU_20KC: |
193 | /* | |
194 | * WAIT on Rev1.0 has E1, E2, E3 and E16. | |
195 | * WAIT on Rev2.0 and Rev3.0 has E16. | |
196 | * Rev3.1 WAIT is nop, why bother | |
197 | */ | |
198 | if ((c->processor_id & 0xff) <= 0x64) | |
199 | break; | |
200 | ||
50da469a RB |
201 | /* |
202 | * Another rev is incremeting c0_count at a reduced clock | |
203 | * rate while in WAIT mode. So we basically have the choice | |
204 | * between using the cp0 timer as clocksource or avoiding | |
205 | * the WAIT instruction. Until more details are known, | |
206 | * disable the use of WAIT for 20Kc entirely. | |
207 | cpu_wait = r4k_wait; | |
208 | */ | |
c8eae71d | 209 | break; |
441ee341 | 210 | case CPU_RM9000: |
c2379230 | 211 | if ((c->processor_id & 0x00ff) >= 0x40) |
441ee341 | 212 | cpu_wait = r4k_wait; |
441ee341 | 213 | break; |
1da177e4 | 214 | default: |
1da177e4 LT |
215 | break; |
216 | } | |
217 | } | |
218 | ||
9267a30d MSJ |
219 | static inline void check_errata(void) |
220 | { | |
221 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
222 | ||
223 | switch (c->cputype) { | |
224 | case CPU_34K: | |
225 | /* | |
226 | * Erratum "RPS May Cause Incorrect Instruction Execution" | |
227 | * This code only handles VPE0, any SMP/SMTC/RTOS code | |
228 | * making use of VPE1 will be responsable for that VPE. | |
229 | */ | |
230 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) | |
231 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); | |
232 | break; | |
233 | default: | |
234 | break; | |
235 | } | |
236 | } | |
237 | ||
1da177e4 LT |
238 | void __init check_bugs32(void) |
239 | { | |
9267a30d | 240 | check_errata(); |
1da177e4 LT |
241 | } |
242 | ||
243 | /* | |
244 | * Probe whether cpu has config register by trying to play with | |
245 | * alternate cache bit and see whether it matters. | |
246 | * It's used by cpu_probe to distinguish between R3000A and R3081. | |
247 | */ | |
248 | static inline int cpu_has_confreg(void) | |
249 | { | |
250 | #ifdef CONFIG_CPU_R3000 | |
251 | extern unsigned long r3k_cache_size(unsigned long); | |
252 | unsigned long size1, size2; | |
253 | unsigned long cfg = read_c0_conf(); | |
254 | ||
255 | size1 = r3k_cache_size(ST0_ISC); | |
256 | write_c0_conf(cfg ^ R30XX_CONF_AC); | |
257 | size2 = r3k_cache_size(ST0_ISC); | |
258 | write_c0_conf(cfg); | |
259 | return size1 != size2; | |
260 | #else | |
261 | return 0; | |
262 | #endif | |
263 | } | |
264 | ||
265 | /* | |
266 | * Get the FPU Implementation/Revision. | |
267 | */ | |
268 | static inline unsigned long cpu_get_fpu_id(void) | |
269 | { | |
270 | unsigned long tmp, fpu_id; | |
271 | ||
272 | tmp = read_c0_status(); | |
273 | __enable_fpu(); | |
274 | fpu_id = read_32bit_cp1_register(CP1_REVISION); | |
275 | write_c0_status(tmp); | |
276 | return fpu_id; | |
277 | } | |
278 | ||
279 | /* | |
280 | * Check the CPU has an FPU the official way. | |
281 | */ | |
282 | static inline int __cpu_has_fpu(void) | |
283 | { | |
284 | return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); | |
285 | } | |
286 | ||
02cf2119 | 287 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
1da177e4 LT |
288 | | MIPS_CPU_COUNTER) |
289 | ||
cea7e2df | 290 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 LT |
291 | { |
292 | switch (c->processor_id & 0xff00) { | |
293 | case PRID_IMP_R2000: | |
294 | c->cputype = CPU_R2000; | |
cea7e2df | 295 | __cpu_name[cpu] = "R2000"; |
1da177e4 | 296 | c->isa_level = MIPS_CPU_ISA_I; |
02cf2119 RB |
297 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
298 | MIPS_CPU_NOFPUEX; | |
1da177e4 LT |
299 | if (__cpu_has_fpu()) |
300 | c->options |= MIPS_CPU_FPU; | |
301 | c->tlbsize = 64; | |
302 | break; | |
303 | case PRID_IMP_R3000: | |
cea7e2df RB |
304 | if ((c->processor_id & 0xff) == PRID_REV_R3000A) { |
305 | if (cpu_has_confreg()) { | |
1da177e4 | 306 | c->cputype = CPU_R3081E; |
cea7e2df RB |
307 | __cpu_name[cpu] = "R3081"; |
308 | } else { | |
1da177e4 | 309 | c->cputype = CPU_R3000A; |
cea7e2df RB |
310 | __cpu_name[cpu] = "R3000A"; |
311 | } | |
312 | break; | |
313 | } else { | |
1da177e4 | 314 | c->cputype = CPU_R3000; |
cea7e2df RB |
315 | __cpu_name[cpu] = "R3000"; |
316 | } | |
1da177e4 | 317 | c->isa_level = MIPS_CPU_ISA_I; |
02cf2119 RB |
318 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
319 | MIPS_CPU_NOFPUEX; | |
1da177e4 LT |
320 | if (__cpu_has_fpu()) |
321 | c->options |= MIPS_CPU_FPU; | |
322 | c->tlbsize = 64; | |
323 | break; | |
324 | case PRID_IMP_R4000: | |
325 | if (read_c0_config() & CONF_SC) { | |
cea7e2df | 326 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) { |
1da177e4 | 327 | c->cputype = CPU_R4400PC; |
cea7e2df RB |
328 | __cpu_name[cpu] = "R4400PC"; |
329 | } else { | |
1da177e4 | 330 | c->cputype = CPU_R4000PC; |
cea7e2df RB |
331 | __cpu_name[cpu] = "R4000PC"; |
332 | } | |
1da177e4 | 333 | } else { |
cea7e2df | 334 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) { |
1da177e4 | 335 | c->cputype = CPU_R4400SC; |
cea7e2df RB |
336 | __cpu_name[cpu] = "R4400SC"; |
337 | } else { | |
1da177e4 | 338 | c->cputype = CPU_R4000SC; |
cea7e2df RB |
339 | __cpu_name[cpu] = "R4000SC"; |
340 | } | |
1da177e4 LT |
341 | } |
342 | ||
343 | c->isa_level = MIPS_CPU_ISA_III; | |
344 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
345 | MIPS_CPU_WATCH | MIPS_CPU_VCE | | |
346 | MIPS_CPU_LLSC; | |
347 | c->tlbsize = 48; | |
348 | break; | |
349 | case PRID_IMP_VR41XX: | |
350 | switch (c->processor_id & 0xf0) { | |
1da177e4 LT |
351 | case PRID_REV_VR4111: |
352 | c->cputype = CPU_VR4111; | |
cea7e2df | 353 | __cpu_name[cpu] = "NEC VR4111"; |
1da177e4 | 354 | break; |
1da177e4 LT |
355 | case PRID_REV_VR4121: |
356 | c->cputype = CPU_VR4121; | |
cea7e2df | 357 | __cpu_name[cpu] = "NEC VR4121"; |
1da177e4 LT |
358 | break; |
359 | case PRID_REV_VR4122: | |
cea7e2df | 360 | if ((c->processor_id & 0xf) < 0x3) { |
1da177e4 | 361 | c->cputype = CPU_VR4122; |
cea7e2df RB |
362 | __cpu_name[cpu] = "NEC VR4122"; |
363 | } else { | |
1da177e4 | 364 | c->cputype = CPU_VR4181A; |
cea7e2df RB |
365 | __cpu_name[cpu] = "NEC VR4181A"; |
366 | } | |
1da177e4 LT |
367 | break; |
368 | case PRID_REV_VR4130: | |
cea7e2df | 369 | if ((c->processor_id & 0xf) < 0x4) { |
1da177e4 | 370 | c->cputype = CPU_VR4131; |
cea7e2df RB |
371 | __cpu_name[cpu] = "NEC VR4131"; |
372 | } else { | |
1da177e4 | 373 | c->cputype = CPU_VR4133; |
cea7e2df RB |
374 | __cpu_name[cpu] = "NEC VR4133"; |
375 | } | |
1da177e4 LT |
376 | break; |
377 | default: | |
378 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); | |
379 | c->cputype = CPU_VR41XX; | |
cea7e2df | 380 | __cpu_name[cpu] = "NEC Vr41xx"; |
1da177e4 LT |
381 | break; |
382 | } | |
383 | c->isa_level = MIPS_CPU_ISA_III; | |
384 | c->options = R4K_OPTS; | |
385 | c->tlbsize = 32; | |
386 | break; | |
387 | case PRID_IMP_R4300: | |
388 | c->cputype = CPU_R4300; | |
cea7e2df | 389 | __cpu_name[cpu] = "R4300"; |
1da177e4 LT |
390 | c->isa_level = MIPS_CPU_ISA_III; |
391 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
392 | MIPS_CPU_LLSC; | |
393 | c->tlbsize = 32; | |
394 | break; | |
395 | case PRID_IMP_R4600: | |
396 | c->cputype = CPU_R4600; | |
cea7e2df | 397 | __cpu_name[cpu] = "R4600"; |
1da177e4 | 398 | c->isa_level = MIPS_CPU_ISA_III; |
075e7502 TS |
399 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
400 | MIPS_CPU_LLSC; | |
1da177e4 LT |
401 | c->tlbsize = 48; |
402 | break; | |
403 | #if 0 | |
404 | case PRID_IMP_R4650: | |
405 | /* | |
406 | * This processor doesn't have an MMU, so it's not | |
407 | * "real easy" to run Linux on it. It is left purely | |
408 | * for documentation. Commented out because it shares | |
409 | * it's c0_prid id number with the TX3900. | |
410 | */ | |
a3dddd56 | 411 | c->cputype = CPU_R4650; |
cea7e2df | 412 | __cpu_name[cpu] = "R4650"; |
1da177e4 LT |
413 | c->isa_level = MIPS_CPU_ISA_III; |
414 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; | |
415 | c->tlbsize = 48; | |
416 | break; | |
417 | #endif | |
418 | case PRID_IMP_TX39: | |
419 | c->isa_level = MIPS_CPU_ISA_I; | |
02cf2119 | 420 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
1da177e4 LT |
421 | |
422 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { | |
423 | c->cputype = CPU_TX3927; | |
cea7e2df | 424 | __cpu_name[cpu] = "TX3927"; |
1da177e4 LT |
425 | c->tlbsize = 64; |
426 | } else { | |
427 | switch (c->processor_id & 0xff) { | |
428 | case PRID_REV_TX3912: | |
429 | c->cputype = CPU_TX3912; | |
cea7e2df | 430 | __cpu_name[cpu] = "TX3912"; |
1da177e4 LT |
431 | c->tlbsize = 32; |
432 | break; | |
433 | case PRID_REV_TX3922: | |
434 | c->cputype = CPU_TX3922; | |
cea7e2df | 435 | __cpu_name[cpu] = "TX3922"; |
1da177e4 LT |
436 | c->tlbsize = 64; |
437 | break; | |
1da177e4 LT |
438 | } |
439 | } | |
440 | break; | |
441 | case PRID_IMP_R4700: | |
442 | c->cputype = CPU_R4700; | |
cea7e2df | 443 | __cpu_name[cpu] = "R4700"; |
1da177e4 LT |
444 | c->isa_level = MIPS_CPU_ISA_III; |
445 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
446 | MIPS_CPU_LLSC; | |
447 | c->tlbsize = 48; | |
448 | break; | |
449 | case PRID_IMP_TX49: | |
450 | c->cputype = CPU_TX49XX; | |
cea7e2df | 451 | __cpu_name[cpu] = "R49XX"; |
1da177e4 LT |
452 | c->isa_level = MIPS_CPU_ISA_III; |
453 | c->options = R4K_OPTS | MIPS_CPU_LLSC; | |
454 | if (!(c->processor_id & 0x08)) | |
455 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; | |
456 | c->tlbsize = 48; | |
457 | break; | |
458 | case PRID_IMP_R5000: | |
459 | c->cputype = CPU_R5000; | |
cea7e2df | 460 | __cpu_name[cpu] = "R5000"; |
1da177e4 LT |
461 | c->isa_level = MIPS_CPU_ISA_IV; |
462 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
463 | MIPS_CPU_LLSC; | |
464 | c->tlbsize = 48; | |
465 | break; | |
466 | case PRID_IMP_R5432: | |
467 | c->cputype = CPU_R5432; | |
cea7e2df | 468 | __cpu_name[cpu] = "R5432"; |
1da177e4 LT |
469 | c->isa_level = MIPS_CPU_ISA_IV; |
470 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
471 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; | |
472 | c->tlbsize = 48; | |
473 | break; | |
474 | case PRID_IMP_R5500: | |
475 | c->cputype = CPU_R5500; | |
cea7e2df | 476 | __cpu_name[cpu] = "R5500"; |
1da177e4 LT |
477 | c->isa_level = MIPS_CPU_ISA_IV; |
478 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
479 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; | |
480 | c->tlbsize = 48; | |
481 | break; | |
482 | case PRID_IMP_NEVADA: | |
483 | c->cputype = CPU_NEVADA; | |
cea7e2df | 484 | __cpu_name[cpu] = "Nevada"; |
1da177e4 LT |
485 | c->isa_level = MIPS_CPU_ISA_IV; |
486 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
487 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; | |
488 | c->tlbsize = 48; | |
489 | break; | |
490 | case PRID_IMP_R6000: | |
491 | c->cputype = CPU_R6000; | |
cea7e2df | 492 | __cpu_name[cpu] = "R6000"; |
1da177e4 LT |
493 | c->isa_level = MIPS_CPU_ISA_II; |
494 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | | |
495 | MIPS_CPU_LLSC; | |
496 | c->tlbsize = 32; | |
497 | break; | |
498 | case PRID_IMP_R6000A: | |
499 | c->cputype = CPU_R6000A; | |
cea7e2df | 500 | __cpu_name[cpu] = "R6000A"; |
1da177e4 LT |
501 | c->isa_level = MIPS_CPU_ISA_II; |
502 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | | |
503 | MIPS_CPU_LLSC; | |
504 | c->tlbsize = 32; | |
505 | break; | |
506 | case PRID_IMP_RM7000: | |
507 | c->cputype = CPU_RM7000; | |
cea7e2df | 508 | __cpu_name[cpu] = "RM7000"; |
1da177e4 LT |
509 | c->isa_level = MIPS_CPU_ISA_IV; |
510 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
511 | MIPS_CPU_LLSC; | |
512 | /* | |
513 | * Undocumented RM7000: Bit 29 in the info register of | |
514 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 | |
515 | * entries. | |
516 | * | |
517 | * 29 1 => 64 entry JTLB | |
518 | * 0 => 48 entry JTLB | |
519 | */ | |
520 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
521 | break; | |
522 | case PRID_IMP_RM9000: | |
523 | c->cputype = CPU_RM9000; | |
cea7e2df | 524 | __cpu_name[cpu] = "RM9000"; |
1da177e4 LT |
525 | c->isa_level = MIPS_CPU_ISA_IV; |
526 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
527 | MIPS_CPU_LLSC; | |
528 | /* | |
529 | * Bit 29 in the info register of the RM9000 | |
530 | * indicates if the TLB has 48 or 64 entries. | |
531 | * | |
532 | * 29 1 => 64 entry JTLB | |
533 | * 0 => 48 entry JTLB | |
534 | */ | |
535 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
536 | break; | |
537 | case PRID_IMP_R8000: | |
538 | c->cputype = CPU_R8000; | |
cea7e2df | 539 | __cpu_name[cpu] = "RM8000"; |
1da177e4 LT |
540 | c->isa_level = MIPS_CPU_ISA_IV; |
541 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | | |
542 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
543 | MIPS_CPU_LLSC; | |
544 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ | |
545 | break; | |
546 | case PRID_IMP_R10000: | |
547 | c->cputype = CPU_R10000; | |
cea7e2df | 548 | __cpu_name[cpu] = "R10000"; |
1da177e4 | 549 | c->isa_level = MIPS_CPU_ISA_IV; |
8b36612a | 550 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
1da177e4 LT |
551 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
552 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
553 | MIPS_CPU_LLSC; | |
554 | c->tlbsize = 64; | |
555 | break; | |
556 | case PRID_IMP_R12000: | |
557 | c->cputype = CPU_R12000; | |
cea7e2df | 558 | __cpu_name[cpu] = "R12000"; |
1da177e4 | 559 | c->isa_level = MIPS_CPU_ISA_IV; |
8b36612a | 560 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
1da177e4 LT |
561 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
562 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
563 | MIPS_CPU_LLSC; | |
564 | c->tlbsize = 64; | |
565 | break; | |
44d921b2 K |
566 | case PRID_IMP_R14000: |
567 | c->cputype = CPU_R14000; | |
cea7e2df | 568 | __cpu_name[cpu] = "R14000"; |
44d921b2 K |
569 | c->isa_level = MIPS_CPU_ISA_IV; |
570 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | | |
571 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
572 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
573 | MIPS_CPU_LLSC; | |
574 | c->tlbsize = 64; | |
575 | break; | |
2a21c730 FZ |
576 | case PRID_IMP_LOONGSON2: |
577 | c->cputype = CPU_LOONGSON2; | |
cea7e2df | 578 | __cpu_name[cpu] = "ICT Loongson-2"; |
2a21c730 FZ |
579 | c->isa_level = MIPS_CPU_ISA_III; |
580 | c->options = R4K_OPTS | | |
581 | MIPS_CPU_FPU | MIPS_CPU_LLSC | | |
582 | MIPS_CPU_32FPR; | |
583 | c->tlbsize = 64; | |
584 | break; | |
1da177e4 LT |
585 | } |
586 | } | |
587 | ||
234fcd14 | 588 | static char unknown_isa[] __cpuinitdata = KERN_ERR \ |
b4672d37 RB |
589 | "Unsupported ISA type, c0.config0: %d."; |
590 | ||
4194318c | 591 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
1da177e4 | 592 | { |
4194318c RB |
593 | unsigned int config0; |
594 | int isa; | |
1da177e4 | 595 | |
4194318c RB |
596 | config0 = read_c0_config(); |
597 | ||
598 | if (((config0 & MIPS_CONF_MT) >> 7) == 1) | |
02cf2119 | 599 | c->options |= MIPS_CPU_TLB; |
4194318c RB |
600 | isa = (config0 & MIPS_CONF_AT) >> 13; |
601 | switch (isa) { | |
602 | case 0: | |
3a01c49a | 603 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
b4672d37 RB |
604 | case 0: |
605 | c->isa_level = MIPS_CPU_ISA_M32R1; | |
606 | break; | |
607 | case 1: | |
608 | c->isa_level = MIPS_CPU_ISA_M32R2; | |
609 | break; | |
610 | default: | |
611 | goto unknown; | |
612 | } | |
4194318c RB |
613 | break; |
614 | case 2: | |
3a01c49a | 615 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
b4672d37 RB |
616 | case 0: |
617 | c->isa_level = MIPS_CPU_ISA_M64R1; | |
618 | break; | |
619 | case 1: | |
620 | c->isa_level = MIPS_CPU_ISA_M64R2; | |
621 | break; | |
622 | default: | |
623 | goto unknown; | |
624 | } | |
4194318c RB |
625 | break; |
626 | default: | |
b4672d37 | 627 | goto unknown; |
4194318c RB |
628 | } |
629 | ||
630 | return config0 & MIPS_CONF_M; | |
b4672d37 RB |
631 | |
632 | unknown: | |
633 | panic(unknown_isa, config0); | |
4194318c RB |
634 | } |
635 | ||
636 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) | |
637 | { | |
638 | unsigned int config1; | |
1da177e4 | 639 | |
1da177e4 | 640 | config1 = read_c0_config1(); |
4194318c RB |
641 | |
642 | if (config1 & MIPS_CONF1_MD) | |
643 | c->ases |= MIPS_ASE_MDMX; | |
644 | if (config1 & MIPS_CONF1_WR) | |
1da177e4 | 645 | c->options |= MIPS_CPU_WATCH; |
4194318c RB |
646 | if (config1 & MIPS_CONF1_CA) |
647 | c->ases |= MIPS_ASE_MIPS16; | |
648 | if (config1 & MIPS_CONF1_EP) | |
1da177e4 | 649 | c->options |= MIPS_CPU_EJTAG; |
4194318c | 650 | if (config1 & MIPS_CONF1_FP) { |
1da177e4 LT |
651 | c->options |= MIPS_CPU_FPU; |
652 | c->options |= MIPS_CPU_32FPR; | |
653 | } | |
4194318c RB |
654 | if (cpu_has_tlb) |
655 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; | |
656 | ||
657 | return config1 & MIPS_CONF_M; | |
658 | } | |
659 | ||
660 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) | |
661 | { | |
662 | unsigned int config2; | |
663 | ||
664 | config2 = read_c0_config2(); | |
665 | ||
666 | if (config2 & MIPS_CONF2_SL) | |
667 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | |
668 | ||
669 | return config2 & MIPS_CONF_M; | |
670 | } | |
671 | ||
672 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) | |
673 | { | |
674 | unsigned int config3; | |
675 | ||
676 | config3 = read_c0_config3(); | |
677 | ||
678 | if (config3 & MIPS_CONF3_SM) | |
679 | c->ases |= MIPS_ASE_SMARTMIPS; | |
e50c0a8f RB |
680 | if (config3 & MIPS_CONF3_DSP) |
681 | c->ases |= MIPS_ASE_DSP; | |
8f40611d RB |
682 | if (config3 & MIPS_CONF3_VINT) |
683 | c->options |= MIPS_CPU_VINT; | |
684 | if (config3 & MIPS_CONF3_VEIC) | |
685 | c->options |= MIPS_CPU_VEIC; | |
686 | if (config3 & MIPS_CONF3_MT) | |
e0daad44 | 687 | c->ases |= MIPS_ASE_MIPSMT; |
a3692020 RB |
688 | if (config3 & MIPS_CONF3_ULRI) |
689 | c->options |= MIPS_CPU_ULRI; | |
4194318c RB |
690 | |
691 | return config3 & MIPS_CONF_M; | |
692 | } | |
693 | ||
234fcd14 | 694 | static void __cpuinit decode_configs(struct cpuinfo_mips *c) |
4194318c | 695 | { |
558ce124 RB |
696 | int ok; |
697 | ||
4194318c | 698 | /* MIPS32 or MIPS64 compliant CPU. */ |
02cf2119 RB |
699 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | |
700 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; | |
4194318c | 701 | |
1da177e4 LT |
702 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; |
703 | ||
558ce124 RB |
704 | ok = decode_config0(c); /* Read Config registers. */ |
705 | BUG_ON(!ok); /* Arch spec violation! */ | |
706 | if (ok) | |
707 | ok = decode_config1(c); | |
708 | if (ok) | |
709 | ok = decode_config2(c); | |
710 | if (ok) | |
711 | ok = decode_config3(c); | |
712 | ||
713 | mips_probe_watch_registers(c); | |
1da177e4 LT |
714 | } |
715 | ||
0b6d497f CD |
716 | #ifdef CONFIG_CPU_MIPSR2 |
717 | extern void spram_config(void); | |
718 | #else | |
719 | static inline void spram_config(void) {} | |
720 | #endif | |
721 | ||
cea7e2df | 722 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 723 | { |
4194318c | 724 | decode_configs(c); |
1da177e4 LT |
725 | switch (c->processor_id & 0xff00) { |
726 | case PRID_IMP_4KC: | |
727 | c->cputype = CPU_4KC; | |
cea7e2df | 728 | __cpu_name[cpu] = "MIPS 4Kc"; |
1da177e4 LT |
729 | break; |
730 | case PRID_IMP_4KEC: | |
731 | c->cputype = CPU_4KEC; | |
cea7e2df | 732 | __cpu_name[cpu] = "MIPS 4KEc"; |
1da177e4 | 733 | break; |
2b07bd02 RB |
734 | case PRID_IMP_4KECR2: |
735 | c->cputype = CPU_4KEC; | |
cea7e2df | 736 | __cpu_name[cpu] = "MIPS 4KEc"; |
2b07bd02 | 737 | break; |
1da177e4 | 738 | case PRID_IMP_4KSC: |
8afcb5d8 | 739 | case PRID_IMP_4KSD: |
1da177e4 | 740 | c->cputype = CPU_4KSC; |
cea7e2df | 741 | __cpu_name[cpu] = "MIPS 4KSc"; |
1da177e4 LT |
742 | break; |
743 | case PRID_IMP_5KC: | |
744 | c->cputype = CPU_5KC; | |
cea7e2df | 745 | __cpu_name[cpu] = "MIPS 5Kc"; |
1da177e4 LT |
746 | break; |
747 | case PRID_IMP_20KC: | |
748 | c->cputype = CPU_20KC; | |
cea7e2df | 749 | __cpu_name[cpu] = "MIPS 20Kc"; |
1da177e4 LT |
750 | break; |
751 | case PRID_IMP_24K: | |
e50c0a8f | 752 | case PRID_IMP_24KE: |
1da177e4 | 753 | c->cputype = CPU_24K; |
cea7e2df | 754 | __cpu_name[cpu] = "MIPS 24Kc"; |
1da177e4 LT |
755 | break; |
756 | case PRID_IMP_25KF: | |
757 | c->cputype = CPU_25KF; | |
cea7e2df | 758 | __cpu_name[cpu] = "MIPS 25Kc"; |
1da177e4 | 759 | break; |
bbc7f22f RB |
760 | case PRID_IMP_34K: |
761 | c->cputype = CPU_34K; | |
cea7e2df | 762 | __cpu_name[cpu] = "MIPS 34Kc"; |
bbc7f22f | 763 | break; |
c620953c CD |
764 | case PRID_IMP_74K: |
765 | c->cputype = CPU_74K; | |
cea7e2df | 766 | __cpu_name[cpu] = "MIPS 74Kc"; |
c620953c | 767 | break; |
39b8d525 RB |
768 | case PRID_IMP_1004K: |
769 | c->cputype = CPU_1004K; | |
cea7e2df | 770 | __cpu_name[cpu] = "MIPS 1004Kc"; |
39b8d525 | 771 | break; |
1da177e4 | 772 | } |
0b6d497f CD |
773 | |
774 | spram_config(); | |
1da177e4 LT |
775 | } |
776 | ||
cea7e2df | 777 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 778 | { |
4194318c | 779 | decode_configs(c); |
1da177e4 LT |
780 | switch (c->processor_id & 0xff00) { |
781 | case PRID_IMP_AU1_REV1: | |
782 | case PRID_IMP_AU1_REV2: | |
783 | switch ((c->processor_id >> 24) & 0xff) { | |
784 | case 0: | |
a3dddd56 | 785 | c->cputype = CPU_AU1000; |
cea7e2df | 786 | __cpu_name[cpu] = "Au1000"; |
1da177e4 LT |
787 | break; |
788 | case 1: | |
789 | c->cputype = CPU_AU1500; | |
cea7e2df | 790 | __cpu_name[cpu] = "Au1500"; |
1da177e4 LT |
791 | break; |
792 | case 2: | |
793 | c->cputype = CPU_AU1100; | |
cea7e2df | 794 | __cpu_name[cpu] = "Au1100"; |
1da177e4 LT |
795 | break; |
796 | case 3: | |
797 | c->cputype = CPU_AU1550; | |
cea7e2df | 798 | __cpu_name[cpu] = "Au1550"; |
1da177e4 | 799 | break; |
e3ad1c23 PP |
800 | case 4: |
801 | c->cputype = CPU_AU1200; | |
cea7e2df RB |
802 | __cpu_name[cpu] = "Au1200"; |
803 | if ((c->processor_id & 0xff) == 2) { | |
237cfee1 | 804 | c->cputype = CPU_AU1250; |
cea7e2df RB |
805 | __cpu_name[cpu] = "Au1250"; |
806 | } | |
237cfee1 ML |
807 | break; |
808 | case 5: | |
809 | c->cputype = CPU_AU1210; | |
cea7e2df | 810 | __cpu_name[cpu] = "Au1210"; |
e3ad1c23 | 811 | break; |
1da177e4 LT |
812 | default: |
813 | panic("Unknown Au Core!"); | |
814 | break; | |
815 | } | |
1da177e4 LT |
816 | break; |
817 | } | |
818 | } | |
819 | ||
cea7e2df | 820 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 821 | { |
4194318c | 822 | decode_configs(c); |
02cf2119 | 823 | |
1da177e4 LT |
824 | switch (c->processor_id & 0xff00) { |
825 | case PRID_IMP_SB1: | |
826 | c->cputype = CPU_SB1; | |
cea7e2df | 827 | __cpu_name[cpu] = "SiByte SB1"; |
1da177e4 | 828 | /* FPU in pass1 is known to have issues. */ |
aa32374a | 829 | if ((c->processor_id & 0xff) < 0x02) |
010b853b | 830 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
1da177e4 | 831 | break; |
93ce2f52 AI |
832 | case PRID_IMP_SB1A: |
833 | c->cputype = CPU_SB1A; | |
cea7e2df | 834 | __cpu_name[cpu] = "SiByte SB1A"; |
93ce2f52 | 835 | break; |
1da177e4 LT |
836 | } |
837 | } | |
838 | ||
cea7e2df | 839 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 840 | { |
4194318c | 841 | decode_configs(c); |
1da177e4 LT |
842 | switch (c->processor_id & 0xff00) { |
843 | case PRID_IMP_SR71000: | |
844 | c->cputype = CPU_SR71000; | |
cea7e2df | 845 | __cpu_name[cpu] = "Sandcraft SR71000"; |
1da177e4 LT |
846 | c->scache.ways = 8; |
847 | c->tlbsize = 64; | |
848 | break; | |
849 | } | |
850 | } | |
851 | ||
cea7e2df | 852 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
bdf21b18 PP |
853 | { |
854 | decode_configs(c); | |
855 | switch (c->processor_id & 0xff00) { | |
856 | case PRID_IMP_PR4450: | |
857 | c->cputype = CPU_PR4450; | |
cea7e2df | 858 | __cpu_name[cpu] = "Philips PR4450"; |
e7958bb9 | 859 | c->isa_level = MIPS_CPU_ISA_M32R1; |
bdf21b18 | 860 | break; |
bdf21b18 PP |
861 | } |
862 | } | |
863 | ||
cea7e2df | 864 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
1c0c13eb AJ |
865 | { |
866 | decode_configs(c); | |
867 | switch (c->processor_id & 0xff00) { | |
868 | case PRID_IMP_BCM3302: | |
869 | c->cputype = CPU_BCM3302; | |
cea7e2df | 870 | __cpu_name[cpu] = "Broadcom BCM3302"; |
1c0c13eb AJ |
871 | break; |
872 | case PRID_IMP_BCM4710: | |
873 | c->cputype = CPU_BCM4710; | |
cea7e2df | 874 | __cpu_name[cpu] = "Broadcom BCM4710"; |
1c0c13eb AJ |
875 | break; |
876 | } | |
877 | } | |
878 | ||
0dd4781b DD |
879 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
880 | { | |
881 | decode_configs(c); | |
882 | switch (c->processor_id & 0xff00) { | |
883 | case PRID_IMP_CAVIUM_CN38XX: | |
884 | case PRID_IMP_CAVIUM_CN31XX: | |
885 | case PRID_IMP_CAVIUM_CN30XX: | |
886 | case PRID_IMP_CAVIUM_CN58XX: | |
887 | case PRID_IMP_CAVIUM_CN56XX: | |
888 | case PRID_IMP_CAVIUM_CN50XX: | |
889 | case PRID_IMP_CAVIUM_CN52XX: | |
890 | c->cputype = CPU_CAVIUM_OCTEON; | |
891 | __cpu_name[cpu] = "Cavium Octeon"; | |
892 | break; | |
893 | default: | |
894 | printk(KERN_INFO "Unknown Octeon chip!\n"); | |
895 | c->cputype = CPU_UNKNOWN; | |
896 | break; | |
897 | } | |
898 | } | |
899 | ||
9966db25 RB |
900 | const char *__cpu_name[NR_CPUS]; |
901 | ||
234fcd14 | 902 | __cpuinit void cpu_probe(void) |
1da177e4 LT |
903 | { |
904 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
9966db25 | 905 | unsigned int cpu = smp_processor_id(); |
1da177e4 LT |
906 | |
907 | c->processor_id = PRID_IMP_UNKNOWN; | |
908 | c->fpu_id = FPIR_IMP_NONE; | |
909 | c->cputype = CPU_UNKNOWN; | |
910 | ||
911 | c->processor_id = read_c0_prid(); | |
912 | switch (c->processor_id & 0xff0000) { | |
913 | case PRID_COMP_LEGACY: | |
cea7e2df | 914 | cpu_probe_legacy(c, cpu); |
1da177e4 LT |
915 | break; |
916 | case PRID_COMP_MIPS: | |
cea7e2df | 917 | cpu_probe_mips(c, cpu); |
1da177e4 LT |
918 | break; |
919 | case PRID_COMP_ALCHEMY: | |
cea7e2df | 920 | cpu_probe_alchemy(c, cpu); |
1da177e4 LT |
921 | break; |
922 | case PRID_COMP_SIBYTE: | |
cea7e2df | 923 | cpu_probe_sibyte(c, cpu); |
1da177e4 | 924 | break; |
1c0c13eb | 925 | case PRID_COMP_BROADCOM: |
cea7e2df | 926 | cpu_probe_broadcom(c, cpu); |
1c0c13eb | 927 | break; |
1da177e4 | 928 | case PRID_COMP_SANDCRAFT: |
cea7e2df | 929 | cpu_probe_sandcraft(c, cpu); |
1da177e4 | 930 | break; |
a92b0588 | 931 | case PRID_COMP_NXP: |
cea7e2df | 932 | cpu_probe_nxp(c, cpu); |
a3dddd56 | 933 | break; |
0dd4781b DD |
934 | case PRID_COMP_CAVIUM: |
935 | cpu_probe_cavium(c, cpu); | |
936 | break; | |
1da177e4 | 937 | } |
dec8b1ca | 938 | |
cea7e2df RB |
939 | BUG_ON(!__cpu_name[cpu]); |
940 | BUG_ON(c->cputype == CPU_UNKNOWN); | |
941 | ||
dec8b1ca FBH |
942 | /* |
943 | * Platform code can force the cpu type to optimize code | |
944 | * generation. In that case be sure the cpu type is correctly | |
945 | * manually setup otherwise it could trigger some nasty bugs. | |
946 | */ | |
947 | BUG_ON(current_cpu_type() != c->cputype); | |
948 | ||
4194318c | 949 | if (c->options & MIPS_CPU_FPU) { |
1da177e4 | 950 | c->fpu_id = cpu_get_fpu_id(); |
4194318c | 951 | |
e7958bb9 | 952 | if (c->isa_level == MIPS_CPU_ISA_M32R1 || |
b4672d37 RB |
953 | c->isa_level == MIPS_CPU_ISA_M32R2 || |
954 | c->isa_level == MIPS_CPU_ISA_M64R1 || | |
955 | c->isa_level == MIPS_CPU_ISA_M64R2) { | |
4194318c RB |
956 | if (c->fpu_id & MIPS_FPIR_3D) |
957 | c->ases |= MIPS_ASE_MIPS3D; | |
958 | } | |
959 | } | |
9966db25 | 960 | |
f6771dbb RB |
961 | if (cpu_has_mips_r2) |
962 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; | |
963 | else | |
964 | c->srsets = 1; | |
1da177e4 LT |
965 | } |
966 | ||
234fcd14 | 967 | __cpuinit void cpu_report(void) |
1da177e4 LT |
968 | { |
969 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
970 | ||
9966db25 RB |
971 | printk(KERN_INFO "CPU revision is: %08x (%s)\n", |
972 | c->processor_id, cpu_name_string()); | |
1da177e4 | 973 | if (c->options & MIPS_CPU_FPU) |
9966db25 | 974 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); |
1da177e4 | 975 | } |