[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c

/*
 * Processor capabilities determination functions.
 *
 * Copyright (C) xxxx  the Anonymous
 * Copyright (C) 2003, 2004  Maciej W. Rozycki
 * Copyright (C) 1994 - 2003 Ralf Baechle
 * Copyright (C) 2001, 2004  MIPS Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ptrace.h>
#include <linux/stddef.h>

#include <asm/cpu.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>

/*
 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
 * the implementation of the "wait" feature differs between CPU families. This
 * points to the function that implements CPU specific wait.
 * The wait instruction stops the pipeline and reduces the power consumption of
 * the CPU very much.
 */
void (*cpu_wait)(void) = NULL;

static void r3081_wait(void)
{
	unsigned long cfg = read_c0_conf();
	write_c0_conf(cfg | R30XX_CONF_HALT);
}

static void r39xx_wait(void)
{
	unsigned long cfg = read_c0_conf();
	write_c0_conf(cfg | TX39_CONF_HALT);
}

static void r4k_wait(void)
{
	__asm__(".set\tmips3\n\t"
		"wait\n\t"
		".set\tmips0");
}

/* The Au1xxx wait is available only if using 32khz counter or
 * external timer source, but specifically not CP0 Counter. */
int allow_au1k_wait;

static void au1k_wait(void)
{
	/* using the wait instruction makes CP0 counter unusable */
	__asm__(".set mips3\n\t"
		"cache 0x14, 0(%0)\n\t"
		"cache 0x14, 32(%0)\n\t"
		"sync\n\t"
		"nop\n\t"
		"wait\n\t"
		"nop\n\t"
		"nop\n\t"
		"nop\n\t"
		"nop\n\t"
		".set mips0\n\t"
		: : "r" (au1k_wait));
}

static int __initdata nowait = 0;

int __init wait_disable(char *s)
{
	nowait = 1;

	return 1;
}

__setup("nowait", wait_disable);

static inline void check_wait(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	printk("Checking for 'wait' instruction... ");
	if (nowait) {
		printk (" disabled.\n");
		return;
	}

	switch (c->cputype) {
	case CPU_R3081:
	case CPU_R3081E:
		cpu_wait = r3081_wait;
		printk(" available.\n");
		break;
	case CPU_TX3927:
		cpu_wait = r39xx_wait;
		printk(" available.\n");
		break;
	case CPU_R4200:
/*	case CPU_R4300: */
	case CPU_R4600:
	case CPU_R4640:
	case CPU_R4650:
	case CPU_R4700:
	case CPU_R5000:
	case CPU_NEVADA:
	case CPU_RM7000:
	case CPU_RM9000:
	case CPU_TX49XX:
	case CPU_4KC:
	case CPU_4KEC:
	case CPU_4KSC:
	case CPU_5KC:
/*	case CPU_20KC:*/
	case CPU_24K:
	case CPU_25KF:
	case CPU_34K:
		cpu_wait = r4k_wait;
		printk(" available.\n");
		break;
	case CPU_AU1000:
	case CPU_AU1100:
	case CPU_AU1500:
	case CPU_AU1550:
	case CPU_AU1200:
		if (allow_au1k_wait) {
			cpu_wait = au1k_wait;
			printk(" available.\n");
		} else
			printk(" unavailable.\n");
		break;
	default:
		printk(" unavailable.\n");
		break;
	}
}

void __init check_bugs32(void)
{
	check_wait();
}

/*
 * Probe whether cpu has config register by trying to play with
 * alternate cache bit and see whether it matters.
 * It's used by cpu_probe to distinguish between R3000A and R3081.
 */
static inline int cpu_has_confreg(void)
{
#ifdef CONFIG_CPU_R3000
	extern unsigned long r3k_cache_size(unsigned long);
	unsigned long size1, size2;
	unsigned long cfg = read_c0_conf();

	size1 = r3k_cache_size(ST0_ISC);
	write_c0_conf(cfg ^ R30XX_CONF_AC);
	size2 = r3k_cache_size(ST0_ISC);
	write_c0_conf(cfg);
	return size1 != size2;
#else
	return 0;
#endif
}

/*
 * Get the FPU Implementation/Revision.
 */
static inline unsigned long cpu_get_fpu_id(void)
{
	unsigned long tmp, fpu_id;

	tmp = read_c0_status();
	__enable_fpu();
	fpu_id = read_32bit_cp1_register(CP1_REVISION);
	write_c0_status(tmp);
	return fpu_id;
}

/*
 * Check the CPU has an FPU the official way.
 */
static inline int __cpu_has_fpu(void)
{
	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
}

#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
		| MIPS_CPU_COUNTER)

static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
{
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_R2000:
		c->cputype = CPU_R2000;
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
		if (__cpu_has_fpu())
			c->options |= MIPS_CPU_FPU;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R3000:
		if ((c->processor_id & 0xff) == PRID_REV_R3000A)
			if (cpu_has_confreg())
				c->cputype = CPU_R3081E;
			else
				c->cputype = CPU_R3000A;
		else
			c->cputype = CPU_R3000;
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
		if (__cpu_has_fpu())
			c->options |= MIPS_CPU_FPU;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R4000:
		if (read_c0_config() & CONF_SC) {
			if ((c->processor_id & 0xff) >= PRID_REV_R4400)
				c->cputype = CPU_R4400PC;
			else
				c->cputype = CPU_R4000PC;
		} else {
			if ((c->processor_id & 0xff) >= PRID_REV_R4400)
				c->cputype = CPU_R4400SC;
			else
				c->cputype = CPU_R4000SC;
		}

		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_VCE |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_VR41XX:
		switch (c->processor_id & 0xf0) {
		case PRID_REV_VR4111:
			c->cputype = CPU_VR4111;
			break;
		case PRID_REV_VR4121:
			c->cputype = CPU_VR4121;
			break;
		case PRID_REV_VR4122:
			if ((c->processor_id & 0xf) < 0x3)
				c->cputype = CPU_VR4122;
			else
				c->cputype = CPU_VR4181A;
			break;
		case PRID_REV_VR4130:
			if ((c->processor_id & 0xf) < 0x4)
				c->cputype = CPU_VR4131;
			else
				c->cputype = CPU_VR4133;
			break;
		default:
			printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
			c->cputype = CPU_VR41XX;
			break;
		}
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R4300:
		c->cputype = CPU_R4300;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R4600:
		c->cputype = CPU_R4600;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	#if 0
 	case PRID_IMP_R4650:
		/*
		 * This processor doesn't have an MMU, so it's not
		 * "real easy" to run Linux on it. It is left purely
		 * for documentation.  Commented out because it shares
		 * it's c0_prid id number with the TX3900.
		 */
 		c->cputype = CPU_R4650;
	 	c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
	        c->tlbsize = 48;
		break;
	#endif
	case PRID_IMP_TX39:
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB;

		if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
			c->cputype = CPU_TX3927;
			c->tlbsize = 64;
		} else {
			switch (c->processor_id & 0xff) {
			case PRID_REV_TX3912:
				c->cputype = CPU_TX3912;
				c->tlbsize = 32;
				break;
			case PRID_REV_TX3922:
				c->cputype = CPU_TX3922;
				c->tlbsize = 64;
				break;
			default:
				c->cputype = CPU_UNKNOWN;
				break;
			}
		}
		break;
	case PRID_IMP_R4700:
		c->cputype = CPU_R4700;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_TX49:
		c->cputype = CPU_TX49XX;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_LLSC;
		if (!(c->processor_id & 0x08))
			c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5000:
		c->cputype = CPU_R5000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5432:
		c->cputype = CPU_R5432;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5500:
		c->cputype = CPU_R5500;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_NEVADA:
		c->cputype = CPU_NEVADA;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R6000:
		c->cputype = CPU_R6000;
		c->isa_level = MIPS_CPU_ISA_II;
		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R6000A:
		c->cputype = CPU_R6000A;
		c->isa_level = MIPS_CPU_ISA_II;
		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_RM7000:
		c->cputype = CPU_RM7000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		/*
		 * Undocumented RM7000:  Bit 29 in the info register of
		 * the RM7000 v2.0 indicates if the TLB has 48 or 64
		 * entries.
		 *
		 * 29      1 =>    64 entry JTLB
		 *         0 =>    48 entry JTLB
		 */
		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
		break;
	case PRID_IMP_RM9000:
		c->cputype = CPU_RM9000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		/*
		 * Bit 29 in the info register of the RM9000
		 * indicates if the TLB has 48 or 64 entries.
		 *
		 * 29      1 =>    64 entry JTLB
		 *         0 =>    48 entry JTLB
		 */
		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
		break;
	case PRID_IMP_R8000:
		c->cputype = CPU_R8000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
		break;
	case PRID_IMP_R10000:
		c->cputype = CPU_R10000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R12000:
		c->cputype = CPU_R12000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
	}
}

static inline unsigned int decode_config0(struct cpuinfo_mips *c)
{
	unsigned int config0;
	int isa;

	config0 = read_c0_config();

	if (((config0 & MIPS_CONF_MT) >> 7) == 1)
		c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB;
	isa = (config0 & MIPS_CONF_AT) >> 13;
	switch (isa) {
	case 0:
		c->isa_level = MIPS_CPU_ISA_M32;
		break;
	case 2:
		c->isa_level = MIPS_CPU_ISA_M64;
		break;
	default:
		panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
	}

	return config0 & MIPS_CONF_M;
}

static inline unsigned int decode_config1(struct cpuinfo_mips *c)
{
	unsigned int config1;

	config1 = read_c0_config1();

	if (config1 & MIPS_CONF1_MD)
		c->ases |= MIPS_ASE_MDMX;
	if (config1 & MIPS_CONF1_WR)
		c->options |= MIPS_CPU_WATCH;
	if (config1 & MIPS_CONF1_CA)
		c->ases |= MIPS_ASE_MIPS16;
	if (config1 & MIPS_CONF1_EP)
		c->options |= MIPS_CPU_EJTAG;
	if (config1 & MIPS_CONF1_FP) {
		c->options |= MIPS_CPU_FPU;
		c->options |= MIPS_CPU_32FPR;
	}
	if (cpu_has_tlb)
		c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;

	return config1 & MIPS_CONF_M;
}

static inline unsigned int decode_config2(struct cpuinfo_mips *c)
{
	unsigned int config2;

	config2 = read_c0_config2();

	if (config2 & MIPS_CONF2_SL)
		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;

	return config2 & MIPS_CONF_M;
}

static inline unsigned int decode_config3(struct cpuinfo_mips *c)
{
	unsigned int config3;

	config3 = read_c0_config3();

	if (config3 & MIPS_CONF3_SM)
		c->ases |= MIPS_ASE_SMARTMIPS;
	if (config3 & MIPS_CONF3_DSP)
		c->ases |= MIPS_ASE_DSP;
	if (config3 & MIPS_CONF3_VINT)
		c->options |= MIPS_CPU_VINT;
	if (config3 & MIPS_CONF3_VEIC)
		c->options |= MIPS_CPU_VEIC;
	if (config3 & MIPS_CONF3_MT)
                c->ases |= MIPS_ASE_MIPSMT;

	return config3 & MIPS_CONF_M;
}

static inline void decode_configs(struct cpuinfo_mips *c)
{
	/* MIPS32 or MIPS64 compliant CPU.  */
	c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
		     MIPS_CPU_LLSC | MIPS_CPU_MCHECK;

	c->scache.flags = MIPS_CACHE_NOT_PRESENT;

	/* Read Config registers.  */
	if (!decode_config0(c))
		return;			/* actually worth a panic() */
	if (!decode_config1(c))
		return;
	if (!decode_config2(c))
		return;
	if (!decode_config3(c))
		return;
}

static inline void cpu_probe_mips(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_4KC:
		c->cputype = CPU_4KC;
		break;
	case PRID_IMP_4KEC:
		c->cputype = CPU_4KEC;
		break;
	case PRID_IMP_4KECR2:
		c->cputype = CPU_4KEC;
		break;
	case PRID_IMP_4KSC:
		c->cputype = CPU_4KSC;
		break;
	case PRID_IMP_5KC:
		c->cputype = CPU_5KC;
		break;
	case PRID_IMP_20KC:
		c->cputype = CPU_20KC;
		break;
	case PRID_IMP_24K:
	case PRID_IMP_24KE:
		c->cputype = CPU_24K;
		break;
	case PRID_IMP_25KF:
		c->cputype = CPU_25KF;
		/* Probe for L2 cache */
		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
		break;
	case PRID_IMP_34K:
		c->cputype = CPU_34K;
		c->isa_level = MIPS_CPU_ISA_M32;
		break;
	}
}

static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_AU1_REV1:
	case PRID_IMP_AU1_REV2:
		switch ((c->processor_id >> 24) & 0xff) {
		case 0:
 			c->cputype = CPU_AU1000;
			break;
		case 1:
			c->cputype = CPU_AU1500;
			break;
		case 2:
			c->cputype = CPU_AU1100;
			break;
		case 3:
			c->cputype = CPU_AU1550;
			break;
		case 4:
			c->cputype = CPU_AU1200;
			break;
		default:
			panic("Unknown Au Core!");
			break;
		}
		break;
	}
}

static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_SB1:
		c->cputype = CPU_SB1;
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
		/* FPU in pass1 is known to have issues. */
		c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
#endif
		break;
	}
}

static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_SR71000:
		c->cputype = CPU_SR71000;
		c->scache.ways = 8;
		c->tlbsize = 64;
		break;
	}
}

__init void cpu_probe(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	c->processor_id	= PRID_IMP_UNKNOWN;
	c->fpu_id	= FPIR_IMP_NONE;
	c->cputype	= CPU_UNKNOWN;

	c->processor_id = read_c0_prid();
	switch (c->processor_id & 0xff0000) {
	case PRID_COMP_LEGACY:
		cpu_probe_legacy(c);
		break;
	case PRID_COMP_MIPS:
		cpu_probe_mips(c);
		break;
	case PRID_COMP_ALCHEMY:
		cpu_probe_alchemy(c);
		break;
	case PRID_COMP_SIBYTE:
		cpu_probe_sibyte(c);
		break;
	case PRID_COMP_SANDCRAFT:
		cpu_probe_sandcraft(c);
		break;
	default:
		c->cputype = CPU_UNKNOWN;
	}
	if (c->options & MIPS_CPU_FPU) {
		c->fpu_id = cpu_get_fpu_id();

		if (c->isa_level == MIPS_CPU_ISA_M32 ||
		    c->isa_level == MIPS_CPU_ISA_M64) {
			if (c->fpu_id & MIPS_FPIR_3D)
				c->ases |= MIPS_ASE_MIPS3D;
		}
	}
}

__init void cpu_report(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	printk("CPU revision is: %08x\n", c->processor_id);
	if (c->options & MIPS_CPU_FPU)
		printk("FPU revision is: %08x\n", c->fpu_id);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Processor capabilities determination functions.
	3	*
	4	* Copyright (C) xxxx the Anonymous
4194318c	5	* Copyright (C) 2003, 2004 Maciej W. Rozycki
1da177e4	6	* Copyright (C) 1994 - 2003 Ralf Baechle
4194318c	7	* Copyright (C) 2001, 2004 MIPS Inc.
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14	#include <linux/config.h>
	15	#include <linux/init.h>
	16	#include <linux/kernel.h>
	17	#include <linux/ptrace.h>
	18	#include <linux/stddef.h>
	19
1da177e4 LT	20	#include <asm/cpu.h>
	21	#include <asm/fpu.h>
	22	#include <asm/mipsregs.h>
	23	#include <asm/system.h>
	24
	25	/*
	26	* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
	27	* the implementation of the "wait" feature differs between CPU families. This
	28	* points to the function that implements CPU specific wait.
	29	* The wait instruction stops the pipeline and reduces the power consumption of
	30	* the CPU very much.
	31	*/
	32	void (*cpu_wait)(void) = NULL;
	33
	34	static void r3081_wait(void)
	35	{
	36	unsigned long cfg = read_c0_conf();
	37	write_c0_conf(cfg \| R30XX_CONF_HALT);
	38	}
	39
	40	static void r39xx_wait(void)
	41	{
	42	unsigned long cfg = read_c0_conf();
	43	write_c0_conf(cfg \| TX39_CONF_HALT);
	44	}
	45
	46	static void r4k_wait(void)
	47	{
	48	__asm__(".set\tmips3\n\t"
	49	"wait\n\t"
	50	".set\tmips0");
	51	}
	52
494900af PP	53	/* The Au1xxx wait is available only if using 32khz counter or
494900af PP	54	* external timer source, but specifically not CP0 Counter. */
fe359bf5	55	int allow_au1k_wait;
10f650db	56
494900af	57	static void au1k_wait(void)
1da177e4	58	{
1da177e4	59	/* using the wait instruction makes CP0 counter unusable */
10f650db RB	60	__asm__(".set mips3\n\t"
	61	"cache 0x14, 0(%0)\n\t"
	62	"cache 0x14, 32(%0)\n\t"
494900af PP	63	"sync\n\t"
494900af PP	64	"nop\n\t"
1da177e4 LT	65	"wait\n\t"
	66	"nop\n\t"
	67	"nop\n\t"
	68	"nop\n\t"
	69	"nop\n\t"
494900af	70	".set mips0\n\t"
10f650db	71	: : "r" (au1k_wait));
1da177e4 LT	72	}
1da177e4 LT	73
55d04dff RB	74	static int __initdata nowait = 0;
	75
	76	int __init wait_disable(char *s)
	77	{
	78	nowait = 1;
	79
	80	return 1;
	81	}
	82
	83	__setup("nowait", wait_disable);
	84
1da177e4 LT	85	static inline void check_wait(void)
	86	{
	87	struct cpuinfo_mips *c = &current_cpu_data;
	88
	89	printk("Checking for 'wait' instruction... ");
55d04dff RB	90	if (nowait) {
	91	printk (" disabled.\n");
	92	return;
	93	}
	94
1da177e4 LT	95	switch (c->cputype) {
	96	case CPU_R3081:
	97	case CPU_R3081E:
	98	cpu_wait = r3081_wait;
	99	printk(" available.\n");
	100	break;
	101	case CPU_TX3927:
	102	cpu_wait = r39xx_wait;
	103	printk(" available.\n");
	104	break;
	105	case CPU_R4200:
	106	/* case CPU_R4300: */
	107	case CPU_R4600:
	108	case CPU_R4640:
	109	case CPU_R4650:
	110	case CPU_R4700:
	111	case CPU_R5000:
	112	case CPU_NEVADA:
	113	case CPU_RM7000:
	114	case CPU_RM9000:
	115	case CPU_TX49XX:
	116	case CPU_4KC:
	117	case CPU_4KEC:
	118	case CPU_4KSC:
	119	case CPU_5KC:
	120	/* case CPU_20KC:*/
	121	case CPU_24K:
	122	case CPU_25KF:
bbc7f22f	123	case CPU_34K:
1da177e4 LT	124	cpu_wait = r4k_wait;
	125	printk(" available.\n");
	126	break;
1da177e4 LT	127	case CPU_AU1000:
	128	case CPU_AU1100:
	129	case CPU_AU1500:
e3ad1c23 PP	130	case CPU_AU1550:
e3ad1c23 PP	131	case CPU_AU1200:
fe359bf5 PP	132	if (allow_au1k_wait) {
	133	cpu_wait = au1k_wait;
	134	printk(" available.\n");
	135	} else
	136	printk(" unavailable.\n");
1da177e4	137	break;
1da177e4 LT	138	default:
	139	printk(" unavailable.\n");
	140	break;
	141	}
	142	}
	143
	144	void __init check_bugs32(void)
	145	{
	146	check_wait();
	147	}
	148
	149	/*
	150	* Probe whether cpu has config register by trying to play with
	151	* alternate cache bit and see whether it matters.
	152	* It's used by cpu_probe to distinguish between R3000A and R3081.
	153	*/
	154	static inline int cpu_has_confreg(void)
	155	{
	156	#ifdef CONFIG_CPU_R3000
	157	extern unsigned long r3k_cache_size(unsigned long);
	158	unsigned long size1, size2;
	159	unsigned long cfg = read_c0_conf();
	160
	161	size1 = r3k_cache_size(ST0_ISC);
	162	write_c0_conf(cfg ^ R30XX_CONF_AC);
	163	size2 = r3k_cache_size(ST0_ISC);
	164	write_c0_conf(cfg);
	165	return size1 != size2;
	166	#else
	167	return 0;
	168	#endif
	169	}
	170
	171	/*
	172	* Get the FPU Implementation/Revision.
	173	*/
	174	static inline unsigned long cpu_get_fpu_id(void)
	175	{
	176	unsigned long tmp, fpu_id;
	177
	178	tmp = read_c0_status();
	179	__enable_fpu();
	180	fpu_id = read_32bit_cp1_register(CP1_REVISION);
	181	write_c0_status(tmp);
	182	return fpu_id;
	183	}
	184
	185	/*
	186	* Check the CPU has an FPU the official way.
	187	*/
	188	static inline int __cpu_has_fpu(void)
	189	{
	190	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
	191	}
	192
	193	#define R4K_OPTS (MIPS_CPU_TLB \| MIPS_CPU_4KEX \| MIPS_CPU_4KTLB \
	194	\| MIPS_CPU_COUNTER)
	195
	196	static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
	197	{
	198	switch (c->processor_id & 0xff00) {
	199	case PRID_IMP_R2000:
	200	c->cputype = CPU_R2000;
	201	c->isa_level = MIPS_CPU_ISA_I;
202	c->options = MIPS_CPU_TLB \| MIPS_CPU_NOFPUEX;
203	if (__cpu_has_fpu())
204	c->options \|= MIPS_CPU_FPU;
205	c->tlbsize = 64;
206	break;
207	case PRID_IMP_R3000:
208	if ((c->processor_id & 0xff) == PRID_REV_R3000A)
209	if (cpu_has_confreg())
210	c->cputype = CPU_R3081E;
211	else
212	c->cputype = CPU_R3000A;
213	else
214	c->cputype = CPU_R3000;
215	c->isa_level = MIPS_CPU_ISA_I;
216	c->options = MIPS_CPU_TLB \| MIPS_CPU_NOFPUEX;
217	if (__cpu_has_fpu())
218	c->options \|= MIPS_CPU_FPU;
219	c->tlbsize = 64;
220	break;
221	case PRID_IMP_R4000:
222	if (read_c0_config() & CONF_SC) {
223	if ((c->processor_id & 0xff) >= PRID_REV_R4400)
224	c->cputype = CPU_R4400PC;
225	else
226	c->cputype = CPU_R4000PC;
227	} else {
228	if ((c->processor_id & 0xff) >= PRID_REV_R4400)
229	c->cputype = CPU_R4400SC;
230	else
231	c->cputype = CPU_R4000SC;
232	}
233
234	c->isa_level = MIPS_CPU_ISA_III;
235	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
236	MIPS_CPU_WATCH \| MIPS_CPU_VCE \|
237	MIPS_CPU_LLSC;
238	c->tlbsize = 48;
239	break;
240	case PRID_IMP_VR41XX:
241	switch (c->processor_id & 0xf0) {
1da177e4 LT	242	case PRID_REV_VR4111:
	243	c->cputype = CPU_VR4111;
	244	break;
1da177e4 LT	245	case PRID_REV_VR4121:
	246	c->cputype = CPU_VR4121;
	247	break;
	248	case PRID_REV_VR4122:
	249	if ((c->processor_id & 0xf) < 0x3)
	250	c->cputype = CPU_VR4122;
	251	else
	252	c->cputype = CPU_VR4181A;
	253	break;
	254	case PRID_REV_VR4130:
	255	if ((c->processor_id & 0xf) < 0x4)
	256	c->cputype = CPU_VR4131;
	257	else
	258	c->cputype = CPU_VR4133;
	259	break;
	260	default:
	261	printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
	262	c->cputype = CPU_VR41XX;
	263	break;
	264	}
	265	c->isa_level = MIPS_CPU_ISA_III;
	266	c->options = R4K_OPTS;
	267	c->tlbsize = 32;
	268	break;
	269	case PRID_IMP_R4300:
	270	c->cputype = CPU_R4300;
	271	c->isa_level = MIPS_CPU_ISA_III;
	272	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	273	MIPS_CPU_LLSC;
	274	c->tlbsize = 32;
	275	break;
	276	case PRID_IMP_R4600:
	277	c->cputype = CPU_R4600;
	278	c->isa_level = MIPS_CPU_ISA_III;
	279	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_LLSC;
	280	c->tlbsize = 48;
	281	break;
	282	#if 0
	283	case PRID_IMP_R4650:
	284	/*
	285	* This processor doesn't have an MMU, so it's not
	286	* "real easy" to run Linux on it. It is left purely
	287	* for documentation. Commented out because it shares
	288	* it's c0_prid id number with the TX3900.
	289	*/
	290	c->cputype = CPU_R4650;
	291	c->isa_level = MIPS_CPU_ISA_III;
	292	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_LLSC;
	293	c->tlbsize = 48;
	294	break;
	295	#endif
	296	case PRID_IMP_TX39:
	297	c->isa_level = MIPS_CPU_ISA_I;
	298	c->options = MIPS_CPU_TLB;
	299
	300	if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
	301	c->cputype = CPU_TX3927;
	302	c->tlbsize = 64;
	303	} else {
	304	switch (c->processor_id & 0xff) {
	305	case PRID_REV_TX3912:
	306	c->cputype = CPU_TX3912;
	307	c->tlbsize = 32;
	308	break;
309	case PRID_REV_TX3922:
310	c->cputype = CPU_TX3922;
311	c->tlbsize = 64;
312	break;
313	default:
314	c->cputype = CPU_UNKNOWN;
315	break;
316	}
317	}
318	break;
319	case PRID_IMP_R4700:
320	c->cputype = CPU_R4700;
321	c->isa_level = MIPS_CPU_ISA_III;
322	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
323	MIPS_CPU_LLSC;
324	c->tlbsize = 48;
325	break;
326	case PRID_IMP_TX49:
327	c->cputype = CPU_TX49XX;
328	c->isa_level = MIPS_CPU_ISA_III;
329	c->options = R4K_OPTS \| MIPS_CPU_LLSC;
330	if (!(c->processor_id & 0x08))
331	c->options \|= MIPS_CPU_FPU \| MIPS_CPU_32FPR;
332	c->tlbsize = 48;
333	break;
334	case PRID_IMP_R5000:
335	c->cputype = CPU_R5000;
336	c->isa_level = MIPS_CPU_ISA_IV;
337	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
338	MIPS_CPU_LLSC;
339	c->tlbsize = 48;
340	break;
341	case PRID_IMP_R5432:
342	c->cputype = CPU_R5432;
343	c->isa_level = MIPS_CPU_ISA_IV;
344	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
345	MIPS_CPU_WATCH \| MIPS_CPU_LLSC;
346	c->tlbsize = 48;
347	break;
348	case PRID_IMP_R5500:
349	c->cputype = CPU_R5500;
350	c->isa_level = MIPS_CPU_ISA_IV;
351	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
352	MIPS_CPU_WATCH \| MIPS_CPU_LLSC;
353	c->tlbsize = 48;
354	break;
355	case PRID_IMP_NEVADA:
356	c->cputype = CPU_NEVADA;
357	c->isa_level = MIPS_CPU_ISA_IV;
358	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
359	MIPS_CPU_DIVEC \| MIPS_CPU_LLSC;
360	c->tlbsize = 48;
361	break;
362	case PRID_IMP_R6000:
363	c->cputype = CPU_R6000;
364	c->isa_level = MIPS_CPU_ISA_II;
365	c->options = MIPS_CPU_TLB \| MIPS_CPU_FPU \|
366	MIPS_CPU_LLSC;
367	c->tlbsize = 32;
368	break;
369	case PRID_IMP_R6000A:
370	c->cputype = CPU_R6000A;
371	c->isa_level = MIPS_CPU_ISA_II;
372	c->options = MIPS_CPU_TLB \| MIPS_CPU_FPU \|
373	MIPS_CPU_LLSC;
374	c->tlbsize = 32;
375	break;
376	case PRID_IMP_RM7000:
377	c->cputype = CPU_RM7000;
378	c->isa_level = MIPS_CPU_ISA_IV;
379	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
380	MIPS_CPU_LLSC;
381	/*
382	* Undocumented RM7000: Bit 29 in the info register of
383	* the RM7000 v2.0 indicates if the TLB has 48 or 64
384	* entries.
385	*
386	* 29 1 => 64 entry JTLB
387	* 0 => 48 entry JTLB
388	*/
389	c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
390	break;
391	case PRID_IMP_RM9000:
392	c->cputype = CPU_RM9000;
393	c->isa_level = MIPS_CPU_ISA_IV;
394	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
395	MIPS_CPU_LLSC;
396	/*
397	* Bit 29 in the info register of the RM9000
398	* indicates if the TLB has 48 or 64 entries.
399	*
400	* 29 1 => 64 entry JTLB
401	* 0 => 48 entry JTLB
402	*/
403	c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
404	break;
405	case PRID_IMP_R8000:
406	c->cputype = CPU_R8000;
407	c->isa_level = MIPS_CPU_ISA_IV;
408	c->options = MIPS_CPU_TLB \| MIPS_CPU_4KEX \|
409	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
410	MIPS_CPU_LLSC;
411	c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
412	break;
413	case PRID_IMP_R10000:
414	c->cputype = CPU_R10000;
415	c->isa_level = MIPS_CPU_ISA_IV;
416	c->options = MIPS_CPU_TLB \| MIPS_CPU_4KEX \|
417	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
418	MIPS_CPU_COUNTER \| MIPS_CPU_WATCH \|
419	MIPS_CPU_LLSC;
420	c->tlbsize = 64;
421	break;
422	case PRID_IMP_R12000:
423	c->cputype = CPU_R12000;
424	c->isa_level = MIPS_CPU_ISA_IV;
425	c->options = MIPS_CPU_TLB \| MIPS_CPU_4KEX \|
426	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
427	MIPS_CPU_COUNTER \| MIPS_CPU_WATCH \|
428	MIPS_CPU_LLSC;
429	c->tlbsize = 64;
430	break;
431	}
432	}
433
4194318c	434	static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4	435	{
4194318c RB	436	unsigned int config0;
4194318c RB	437	int isa;
1da177e4	438
4194318c RB	439	config0 = read_c0_config();
	440
	441	if (((config0 & MIPS_CONF_MT) >> 7) == 1)
d5b6f1db	442	c->options \|= MIPS_CPU_TLB \| MIPS_CPU_4KTLB;
4194318c RB	443	isa = (config0 & MIPS_CONF_AT) >> 13;
	444	switch (isa) {
	445	case 0:
	446	c->isa_level = MIPS_CPU_ISA_M32;
	447	break;
	448	case 2:
	449	c->isa_level = MIPS_CPU_ISA_M64;
	450	break;
	451	default:
	452	panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
	453	}
	454
	455	return config0 & MIPS_CONF_M;
	456	}
	457
	458	static inline unsigned int decode_config1(struct cpuinfo_mips *c)
	459	{
	460	unsigned int config1;
1da177e4	461
1da177e4	462	config1 = read_c0_config1();
4194318c RB	463
	464	if (config1 & MIPS_CONF1_MD)
	465	c->ases \|= MIPS_ASE_MDMX;
	466	if (config1 & MIPS_CONF1_WR)
1da177e4	467	c->options \|= MIPS_CPU_WATCH;
4194318c RB	468	if (config1 & MIPS_CONF1_CA)
	469	c->ases \|= MIPS_ASE_MIPS16;
	470	if (config1 & MIPS_CONF1_EP)
1da177e4	471	c->options \|= MIPS_CPU_EJTAG;
4194318c	472	if (config1 & MIPS_CONF1_FP) {
1da177e4 LT	473	c->options \|= MIPS_CPU_FPU;
	474	c->options \|= MIPS_CPU_32FPR;
	475	}
4194318c RB	476	if (cpu_has_tlb)
	477	c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
	478
	479	return config1 & MIPS_CONF_M;
	480	}
	481
	482	static inline unsigned int decode_config2(struct cpuinfo_mips *c)
	483	{
	484	unsigned int config2;
	485
	486	config2 = read_c0_config2();
	487
	488	if (config2 & MIPS_CONF2_SL)
	489	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
	490
	491	return config2 & MIPS_CONF_M;
	492	}
	493
	494	static inline unsigned int decode_config3(struct cpuinfo_mips *c)
	495	{
	496	unsigned int config3;
	497
	498	config3 = read_c0_config3();
	499
	500	if (config3 & MIPS_CONF3_SM)
	501	c->ases \|= MIPS_ASE_SMARTMIPS;
e50c0a8f RB	502	if (config3 & MIPS_CONF3_DSP)
e50c0a8f RB	503	c->ases \|= MIPS_ASE_DSP;
8f40611d RB	504	if (config3 & MIPS_CONF3_VINT)
	505	c->options \|= MIPS_CPU_VINT;
	506	if (config3 & MIPS_CONF3_VEIC)
	507	c->options \|= MIPS_CPU_VEIC;
	508	if (config3 & MIPS_CONF3_MT)
	509	c->ases \|= MIPS_ASE_MIPSMT;
4194318c RB	510
	511	return config3 & MIPS_CONF_M;
	512	}
	513
	514	static inline void decode_configs(struct cpuinfo_mips *c)
	515	{
	516	/* MIPS32 or MIPS64 compliant CPU. */
	517	c->options = MIPS_CPU_4KEX \| MIPS_CPU_COUNTER \| MIPS_CPU_DIVEC \|
	518	MIPS_CPU_LLSC \| MIPS_CPU_MCHECK;
	519
1da177e4 LT	520	c->scache.flags = MIPS_CACHE_NOT_PRESENT;
1da177e4 LT	521
4194318c RB	522	/* Read Config registers. */
	523	if (!decode_config0(c))
	524	return; /* actually worth a panic() */
	525	if (!decode_config1(c))
	526	return;
	527	if (!decode_config2(c))
	528	return;
	529	if (!decode_config3(c))
	530	return;
1da177e4 LT	531	}
	532
	533	static inline void cpu_probe_mips(struct cpuinfo_mips *c)
	534	{
4194318c	535	decode_configs(c);
1da177e4 LT	536	switch (c->processor_id & 0xff00) {
	537	case PRID_IMP_4KC:
	538	c->cputype = CPU_4KC;
1da177e4 LT	539	break;
	540	case PRID_IMP_4KEC:
	541	c->cputype = CPU_4KEC;
1da177e4	542	break;
2b07bd02 RB	543	case PRID_IMP_4KECR2:
2b07bd02 RB	544	c->cputype = CPU_4KEC;
2b07bd02	545	break;
1da177e4 LT	546	case PRID_IMP_4KSC:
1da177e4 LT	547	c->cputype = CPU_4KSC;
1da177e4 LT	548	break;
	549	case PRID_IMP_5KC:
	550	c->cputype = CPU_5KC;
1da177e4 LT	551	break;
	552	case PRID_IMP_20KC:
	553	c->cputype = CPU_20KC;
1da177e4 LT	554	break;
1da177e4 LT	555	case PRID_IMP_24K:
e50c0a8f	556	case PRID_IMP_24KE:
1da177e4	557	c->cputype = CPU_24K;
1da177e4 LT	558	break;
	559	case PRID_IMP_25KF:
	560	c->cputype = CPU_25KF;
1da177e4 LT	561	/* Probe for L2 cache */
	562	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
	563	break;
bbc7f22f RB	564	case PRID_IMP_34K:
	565	c->cputype = CPU_34K;
	566	c->isa_level = MIPS_CPU_ISA_M32;
	567	break;
1da177e4 LT	568	}
	569	}
	570
	571	static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
	572	{
4194318c	573	decode_configs(c);
1da177e4 LT	574	switch (c->processor_id & 0xff00) {
	575	case PRID_IMP_AU1_REV1:
	576	case PRID_IMP_AU1_REV2:
	577	switch ((c->processor_id >> 24) & 0xff) {
	578	case 0:
	579	c->cputype = CPU_AU1000;
	580	break;
	581	case 1:
	582	c->cputype = CPU_AU1500;
	583	break;
	584	case 2:
	585	c->cputype = CPU_AU1100;
	586	break;
	587	case 3:
	588	c->cputype = CPU_AU1550;
	589	break;
e3ad1c23 PP	590	case 4:
	591	c->cputype = CPU_AU1200;
	592	break;
1da177e4 LT	593	default:
	594	panic("Unknown Au Core!");
	595	break;
	596	}
1da177e4 LT	597	break;
	598	}
	599	}
	600
	601	static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
	602	{
4194318c	603	decode_configs(c);
1da177e4 LT	604	switch (c->processor_id & 0xff00) {
	605	case PRID_IMP_SB1:
	606	c->cputype = CPU_SB1;
4194318c	607	#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1da177e4	608	/* FPU in pass1 is known to have issues. */
4194318c	609	c->options &= ~(MIPS_CPU_FPU \| MIPS_CPU_32FPR);
1da177e4 LT	610	#endif
	611	break;
	612	}
	613	}
	614
	615	static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
	616	{
4194318c	617	decode_configs(c);
1da177e4 LT	618	switch (c->processor_id & 0xff00) {
	619	case PRID_IMP_SR71000:
	620	c->cputype = CPU_SR71000;
1da177e4 LT	621	c->scache.ways = 8;
	622	c->tlbsize = 64;
	623	break;
	624	}
	625	}
	626
	627	__init void cpu_probe(void)
	628	{
	629	struct cpuinfo_mips *c = &current_cpu_data;
	630
	631	c->processor_id = PRID_IMP_UNKNOWN;
	632	c->fpu_id = FPIR_IMP_NONE;
	633	c->cputype = CPU_UNKNOWN;
	634
	635	c->processor_id = read_c0_prid();
	636	switch (c->processor_id & 0xff0000) {
	637	case PRID_COMP_LEGACY:
	638	cpu_probe_legacy(c);
	639	break;
	640	case PRID_COMP_MIPS:
	641	cpu_probe_mips(c);
	642	break;
	643	case PRID_COMP_ALCHEMY:
	644	cpu_probe_alchemy(c);
	645	break;
	646	case PRID_COMP_SIBYTE:
	647	cpu_probe_sibyte(c);
	648	break;
1da177e4 LT	649	case PRID_COMP_SANDCRAFT:
	650	cpu_probe_sandcraft(c);
	651	break;
	652	default:
	653	c->cputype = CPU_UNKNOWN;
	654	}
4194318c	655	if (c->options & MIPS_CPU_FPU) {
1da177e4	656	c->fpu_id = cpu_get_fpu_id();
4194318c RB	657
	658	if (c->isa_level == MIPS_CPU_ISA_M32 \|\|
	659	c->isa_level == MIPS_CPU_ISA_M64) {
	660	if (c->fpu_id & MIPS_FPIR_3D)
	661	c->ases \|= MIPS_ASE_MIPS3D;
	662	}
	663	}
1da177e4 LT	664	}
	665
	666	__init void cpu_report(void)
	667	{
	668	struct cpuinfo_mips *c = &current_cpu_data;
	669
	670	printk("CPU revision is: %08x\n", c->processor_id);
	671	if (c->options & MIPS_CPU_FPU)
	672	printk("FPU revision is: %08x\n", c->fpu_id);
	673	}