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[MIPS] Enable support for the userlocal hardware register
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
4194318c 7 * Copyright (C) 2001, 2004 MIPS Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
17#include <linux/stddef.h>
18
5759906c 19#include <asm/bugs.h>
1da177e4
LT		 20#include <asm/cpu.h>
21#include <asm/fpu.h>
22#include <asm/mipsregs.h>
23#include <asm/system.h>
24
25/*
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
27 * the implementation of the "wait" feature differs between CPU families. This
28 * points to the function that implements CPU specific wait.
29 * The wait instruction stops the pipeline and reduces the power consumption of
30 * the CPU very much.
31 */
32void (*cpu_wait)(void) = NULL;
33
34static void r3081_wait(void)
35{
36 unsigned long cfg = read_c0_conf();
37 write_c0_conf(cfg | R30XX_CONF_HALT);
38}
39
40static void r39xx_wait(void)
41{
60a6c377
AN		 42 local_irq_disable();
43 if (!need_resched())
44 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
45 local_irq_enable();
1da177e4
LT		 46}
47
60a6c377
AN		 48/*
49 * There is a race when WAIT instruction executed with interrupt
50 * enabled.
51 * But it is implementation-dependent wheter the pipelie restarts when
52 * a non-enabled interrupt is requested.
53 */
1da177e4
LT		 54static void r4k_wait(void)
55{
60a6c377
AN		 56 __asm__(" .set mips3 \n"
57 " wait \n"
58 " .set mips0 \n");
59}
60
61/*
62 * This variant is preferable as it allows testing need_resched and going to
63 * sleep depending on the outcome atomically. Unfortunately the "It is
64 * implementation-dependent whether the pipeline restarts when a non-enabled
65 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
66 * using this version a gamble.
67 */
68static void r4k_wait_irqoff(void)
69{
70 local_irq_disable();
71 if (!need_resched())
72 __asm__(" .set mips3 \n"
73 " wait \n"
74 " .set mips0 \n");
75 local_irq_enable();
1da177e4
LT		 76}
77
494900af
PP		 78/* The Au1xxx wait is available only if using 32khz counter or
79 * external timer source, but specifically not CP0 Counter. */
fe359bf5 80int allow_au1k_wait;
10f650db 81
494900af 82static void au1k_wait(void)
1da177e4 83{
1da177e4 84 /* using the wait instruction makes CP0 counter unusable */
60a6c377
AN		 85 __asm__(" .set mips3 \n"
86 " cache 0x14, 0(%0) \n"
87 " cache 0x14, 32(%0) \n"
88 " sync \n"
89 " nop \n"
90 " wait \n"
91 " nop \n"
92 " nop \n"
93 " nop \n"
94 " nop \n"
95 " .set mips0 \n"
10f650db 96 : : "r" (au1k_wait));
1da177e4
LT		 97}
98
55d04dff
RB		 99static int __initdata nowait = 0;
100
f49a747c 101static int __init wait_disable(char *s)
55d04dff
RB		 102{
103 nowait = 1;
104
105 return 1;
106}
107
108__setup("nowait", wait_disable);
109
1da177e4
LT		 110static inline void check_wait(void)
111{
112 struct cpuinfo_mips *c = &current_cpu_data;
113
55d04dff 114 if (nowait) {
c2379230 115 printk("Wait instruction disabled.\n");
55d04dff
RB		 116 return;
117 }
118
1da177e4
LT		 119 switch (c->cputype) {
120 case CPU_R3081:
121 case CPU_R3081E:
122 cpu_wait = r3081_wait;
1da177e4
LT		 123 break;
124 case CPU_TX3927:
125 cpu_wait = r39xx_wait;
1da177e4
LT		 126 break;
127 case CPU_R4200:
128/* case CPU_R4300: */
129 case CPU_R4600:
130 case CPU_R4640:
131 case CPU_R4650:
132 case CPU_R4700:
133 case CPU_R5000:
134 case CPU_NEVADA:
135 case CPU_RM7000:
1da177e4
LT		 136 case CPU_4KC:
137 case CPU_4KEC:
138 case CPU_4KSC:
139 case CPU_5KC:
1da177e4 140 case CPU_25KF:
4b3e975e
RB		 141 case CPU_PR4450:
142 cpu_wait = r4k_wait;
143 break;
144
145 case CPU_24K:
bbc7f22f 146 case CPU_34K:
4b3e975e
RB		 147 cpu_wait = r4k_wait;
148 if (read_c0_config7() & MIPS_CONF7_WII)
149 cpu_wait = r4k_wait_irqoff;
150 break;
151
c620953c 152 case CPU_74K:
1da177e4 153 cpu_wait = r4k_wait;
4b3e975e
RB		 154 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
155 cpu_wait = r4k_wait_irqoff;
1da177e4 156 break;
4b3e975e 157
60a6c377
AN		 158 case CPU_TX49XX:
159 cpu_wait = r4k_wait_irqoff;
60a6c377 160 break;
1da177e4
LT		 161 case CPU_AU1000:
162 case CPU_AU1100:
163 case CPU_AU1500:
e3ad1c23
PP		 164 case CPU_AU1550:
165 case CPU_AU1200:
c2379230 166 if (allow_au1k_wait)
fe359bf5 167 cpu_wait = au1k_wait;
1da177e4 168 break;
c8eae71d
RB		 169 case CPU_20KC:
170 /*
171 * WAIT on Rev1.0 has E1, E2, E3 and E16.
172 * WAIT on Rev2.0 and Rev3.0 has E16.
173 * Rev3.1 WAIT is nop, why bother
174 */
175 if ((c->processor_id & 0xff) <= 0x64)
176 break;
177
178 cpu_wait = r4k_wait;
179 break;
441ee341 180 case CPU_RM9000:
c2379230 181 if ((c->processor_id & 0x00ff) >= 0x40)
441ee341 182 cpu_wait = r4k_wait;
441ee341 183 break;
1da177e4 184 default:
1da177e4
LT		 185 break;
186 }
187}
188
189void __init check_bugs32(void)
190{
191 check_wait();
192}
193
194/*
195 * Probe whether cpu has config register by trying to play with
196 * alternate cache bit and see whether it matters.
197 * It's used by cpu_probe to distinguish between R3000A and R3081.
198 */
199static inline int cpu_has_confreg(void)
200{
201#ifdef CONFIG_CPU_R3000
202 extern unsigned long r3k_cache_size(unsigned long);
203 unsigned long size1, size2;
204 unsigned long cfg = read_c0_conf();
205
206 size1 = r3k_cache_size(ST0_ISC);
207 write_c0_conf(cfg ^ R30XX_CONF_AC);
208 size2 = r3k_cache_size(ST0_ISC);
209 write_c0_conf(cfg);
210 return size1 != size2;
211#else
212 return 0;
213#endif
214}
215
216/*
217 * Get the FPU Implementation/Revision.
218 */
219static inline unsigned long cpu_get_fpu_id(void)
220{
221 unsigned long tmp, fpu_id;
222
223 tmp = read_c0_status();
224 __enable_fpu();
225 fpu_id = read_32bit_cp1_register(CP1_REVISION);
226 write_c0_status(tmp);
227 return fpu_id;
228}
229
230/*
231 * Check the CPU has an FPU the official way.
232 */
233static inline int __cpu_has_fpu(void)
234{
235 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
236}
237
02cf2119 238#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 239 | MIPS_CPU_COUNTER)
240
241static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
242{
243 switch (c->processor_id & 0xff00) {
244 case PRID_IMP_R2000:
245 c->cputype = CPU_R2000;
246 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 247 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
248 MIPS_CPU_NOFPUEX;
1da177e4
LT		 249 if (__cpu_has_fpu())
250 c->options |= MIPS_CPU_FPU;
251 c->tlbsize = 64;
252 break;
253 case PRID_IMP_R3000:
254 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
255 if (cpu_has_confreg())
256 c->cputype = CPU_R3081E;
257 else
258 c->cputype = CPU_R3000A;
259 else
260 c->cputype = CPU_R3000;
261 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 262 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
263 MIPS_CPU_NOFPUEX;
1da177e4
LT		 264 if (__cpu_has_fpu())
265 c->options |= MIPS_CPU_FPU;
266 c->tlbsize = 64;
267 break;
268 case PRID_IMP_R4000:
269 if (read_c0_config() & CONF_SC) {
270 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
271 c->cputype = CPU_R4400PC;
272 else
273 c->cputype = CPU_R4000PC;
274 } else {
275 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
276 c->cputype = CPU_R4400SC;
277 else
278 c->cputype = CPU_R4000SC;
279 }
280
281 c->isa_level = MIPS_CPU_ISA_III;
282 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
283 MIPS_CPU_WATCH | MIPS_CPU_VCE |
284 MIPS_CPU_LLSC;
285 c->tlbsize = 48;
286 break;
287 case PRID_IMP_VR41XX:
288 switch (c->processor_id & 0xf0) {
1da177e4
LT		 289 case PRID_REV_VR4111:
290 c->cputype = CPU_VR4111;
291 break;
1da177e4
LT		 292 case PRID_REV_VR4121:
293 c->cputype = CPU_VR4121;
294 break;
295 case PRID_REV_VR4122:
296 if ((c->processor_id & 0xf) < 0x3)
297 c->cputype = CPU_VR4122;
298 else
299 c->cputype = CPU_VR4181A;
300 break;
301 case PRID_REV_VR4130:
302 if ((c->processor_id & 0xf) < 0x4)
303 c->cputype = CPU_VR4131;
304 else
305 c->cputype = CPU_VR4133;
306 break;
307 default:
308 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
309 c->cputype = CPU_VR41XX;
310 break;
311 }
312 c->isa_level = MIPS_CPU_ISA_III;
313 c->options = R4K_OPTS;
314 c->tlbsize = 32;
315 break;
316 case PRID_IMP_R4300:
317 c->cputype = CPU_R4300;
318 c->isa_level = MIPS_CPU_ISA_III;
319 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
320 MIPS_CPU_LLSC;
321 c->tlbsize = 32;
322 break;
323 case PRID_IMP_R4600:
324 c->cputype = CPU_R4600;
325 c->isa_level = MIPS_CPU_ISA_III;
075e7502
TS		 326 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
327 MIPS_CPU_LLSC;
1da177e4
LT		 328 c->tlbsize = 48;
329 break;
330 #if 0
331 case PRID_IMP_R4650:
332 /*
333 * This processor doesn't have an MMU, so it's not
334 * "real easy" to run Linux on it. It is left purely
335 * for documentation. Commented out because it shares
336 * it's c0_prid id number with the TX3900.
337 */
a3dddd56 338 c->cputype = CPU_R4650;
1da177e4
LT		 339 c->isa_level = MIPS_CPU_ISA_III;
340 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
341 c->tlbsize = 48;
342 break;
343 #endif
344 case PRID_IMP_TX39:
345 c->isa_level = MIPS_CPU_ISA_I;
02cf2119 346 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 347
348 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
349 c->cputype = CPU_TX3927;
350 c->tlbsize = 64;
351 } else {
352 switch (c->processor_id & 0xff) {
353 case PRID_REV_TX3912:
354 c->cputype = CPU_TX3912;
355 c->tlbsize = 32;
356 break;
357 case PRID_REV_TX3922:
358 c->cputype = CPU_TX3922;
359 c->tlbsize = 64;
360 break;
361 default:
362 c->cputype = CPU_UNKNOWN;
363 break;
364 }
365 }
366 break;
367 case PRID_IMP_R4700:
368 c->cputype = CPU_R4700;
369 c->isa_level = MIPS_CPU_ISA_III;
370 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
371 MIPS_CPU_LLSC;
372 c->tlbsize = 48;
373 break;
374 case PRID_IMP_TX49:
375 c->cputype = CPU_TX49XX;
376 c->isa_level = MIPS_CPU_ISA_III;
377 c->options = R4K_OPTS | MIPS_CPU_LLSC;
378 if (!(c->processor_id & 0x08))
379 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
380 c->tlbsize = 48;
381 break;
382 case PRID_IMP_R5000:
383 c->cputype = CPU_R5000;
384 c->isa_level = MIPS_CPU_ISA_IV;
385 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
386 MIPS_CPU_LLSC;
387 c->tlbsize = 48;
388 break;
389 case PRID_IMP_R5432:
390 c->cputype = CPU_R5432;
391 c->isa_level = MIPS_CPU_ISA_IV;
392 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
393 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
394 c->tlbsize = 48;
395 break;
396 case PRID_IMP_R5500:
397 c->cputype = CPU_R5500;
398 c->isa_level = MIPS_CPU_ISA_IV;
399 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
400 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
401 c->tlbsize = 48;
402 break;
403 case PRID_IMP_NEVADA:
404 c->cputype = CPU_NEVADA;
405 c->isa_level = MIPS_CPU_ISA_IV;
406 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
407 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
408 c->tlbsize = 48;
409 break;
410 case PRID_IMP_R6000:
411 c->cputype = CPU_R6000;
412 c->isa_level = MIPS_CPU_ISA_II;
413 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
414 MIPS_CPU_LLSC;
415 c->tlbsize = 32;
416 break;
417 case PRID_IMP_R6000A:
418 c->cputype = CPU_R6000A;
419 c->isa_level = MIPS_CPU_ISA_II;
420 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
421 MIPS_CPU_LLSC;
422 c->tlbsize = 32;
423 break;
424 case PRID_IMP_RM7000:
425 c->cputype = CPU_RM7000;
426 c->isa_level = MIPS_CPU_ISA_IV;
427 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
428 MIPS_CPU_LLSC;
429 /*
430 * Undocumented RM7000: Bit 29 in the info register of
431 * the RM7000 v2.0 indicates if the TLB has 48 or 64
432 * entries.
433 *
434 * 29 1 => 64 entry JTLB
435 * 0 => 48 entry JTLB
436 */
437 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
438 break;
439 case PRID_IMP_RM9000:
440 c->cputype = CPU_RM9000;
441 c->isa_level = MIPS_CPU_ISA_IV;
442 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
443 MIPS_CPU_LLSC;
444 /*
445 * Bit 29 in the info register of the RM9000
446 * indicates if the TLB has 48 or 64 entries.
447 *
448 * 29 1 => 64 entry JTLB
449 * 0 => 48 entry JTLB
450 */
451 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
452 break;
453 case PRID_IMP_R8000:
454 c->cputype = CPU_R8000;
455 c->isa_level = MIPS_CPU_ISA_IV;
456 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
457 MIPS_CPU_FPU | MIPS_CPU_32FPR |
458 MIPS_CPU_LLSC;
459 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
460 break;
461 case PRID_IMP_R10000:
462 c->cputype = CPU_R10000;
463 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 464 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 465 MIPS_CPU_FPU | MIPS_CPU_32FPR |
466 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
467 MIPS_CPU_LLSC;
468 c->tlbsize = 64;
469 break;
470 case PRID_IMP_R12000:
471 c->cputype = CPU_R12000;
472 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 473 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 474 MIPS_CPU_FPU | MIPS_CPU_32FPR |
475 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
476 MIPS_CPU_LLSC;
477 c->tlbsize = 64;
478 break;
44d921b2
K		 479 case PRID_IMP_R14000:
480 c->cputype = CPU_R14000;
481 c->isa_level = MIPS_CPU_ISA_IV;
482 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
483 MIPS_CPU_FPU | MIPS_CPU_32FPR |
484 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
485 MIPS_CPU_LLSC;
486 c->tlbsize = 64;
487 break;
1da177e4
LT		 488 }
489}
490
b4672d37
RB		 491static char unknown_isa[] __initdata = KERN_ERR \
492 "Unsupported ISA type, c0.config0: %d.";
493
4194318c 494static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4 495{
4194318c
RB		 496 unsigned int config0;
497 int isa;
1da177e4 498
4194318c
RB		 499 config0 = read_c0_config();
500
501 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
02cf2119 502 c->options |= MIPS_CPU_TLB;
4194318c
RB		 503 isa = (config0 & MIPS_CONF_AT) >> 13;
504 switch (isa) {
505 case 0:
3a01c49a 506 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 507 case 0:
508 c->isa_level = MIPS_CPU_ISA_M32R1;
509 break;
510 case 1:
511 c->isa_level = MIPS_CPU_ISA_M32R2;
512 break;
513 default:
514 goto unknown;
515 }
4194318c
RB		 516 break;
517 case 2:
3a01c49a 518 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 519 case 0:
520 c->isa_level = MIPS_CPU_ISA_M64R1;
521 break;
522 case 1:
523 c->isa_level = MIPS_CPU_ISA_M64R2;
524 break;
525 default:
526 goto unknown;
527 }
4194318c
RB		 528 break;
529 default:
b4672d37 530 goto unknown;
4194318c
RB		 531 }
532
533 return config0 & MIPS_CONF_M;
b4672d37
RB		 534
535unknown:
536 panic(unknown_isa, config0);
4194318c
RB		 537}
538
539static inline unsigned int decode_config1(struct cpuinfo_mips *c)
540{
541 unsigned int config1;
1da177e4 542
1da177e4 543 config1 = read_c0_config1();
4194318c
RB		 544
545 if (config1 & MIPS_CONF1_MD)
546 c->ases |= MIPS_ASE_MDMX;
547 if (config1 & MIPS_CONF1_WR)
1da177e4 548 c->options |= MIPS_CPU_WATCH;
4194318c
RB		 549 if (config1 & MIPS_CONF1_CA)
550 c->ases |= MIPS_ASE_MIPS16;
551 if (config1 & MIPS_CONF1_EP)
1da177e4 552 c->options |= MIPS_CPU_EJTAG;
4194318c 553 if (config1 & MIPS_CONF1_FP) {
1da177e4
LT		 554 c->options |= MIPS_CPU_FPU;
555 c->options |= MIPS_CPU_32FPR;
556 }
4194318c
RB		 557 if (cpu_has_tlb)
558 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
559
560 return config1 & MIPS_CONF_M;
561}
562
563static inline unsigned int decode_config2(struct cpuinfo_mips *c)
564{
565 unsigned int config2;
566
567 config2 = read_c0_config2();
568
569 if (config2 & MIPS_CONF2_SL)
570 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
571
572 return config2 & MIPS_CONF_M;
573}
574
575static inline unsigned int decode_config3(struct cpuinfo_mips *c)
576{
577 unsigned int config3;
578
579 config3 = read_c0_config3();
580
581 if (config3 & MIPS_CONF3_SM)
582 c->ases |= MIPS_ASE_SMARTMIPS;
e50c0a8f
RB		 583 if (config3 & MIPS_CONF3_DSP)
584 c->ases |= MIPS_ASE_DSP;
8f40611d
RB		 585 if (config3 & MIPS_CONF3_VINT)
586 c->options |= MIPS_CPU_VINT;
587 if (config3 & MIPS_CONF3_VEIC)
588 c->options |= MIPS_CPU_VEIC;
589 if (config3 & MIPS_CONF3_MT)
e0daad44 590 c->ases |= MIPS_ASE_MIPSMT;
a3692020
RB		 591 if (config3 & MIPS_CONF3_ULRI)
592 c->options |= MIPS_CPU_ULRI;
4194318c
RB		 593
594 return config3 & MIPS_CONF_M;
595}
596
c36cd4ba 597static void __init decode_configs(struct cpuinfo_mips *c)
4194318c
RB		 598{
599 /* MIPS32 or MIPS64 compliant CPU. */
02cf2119
RB		 600 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
601 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
4194318c 602
1da177e4
LT		 603 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
604
4194318c
RB		 605 /* Read Config registers. */
606 if (!decode_config0(c))
607 return; /* actually worth a panic() */
608 if (!decode_config1(c))
609 return;
610 if (!decode_config2(c))
611 return;
612 if (!decode_config3(c))
613 return;
1da177e4
LT		 614}
615
616static inline void cpu_probe_mips(struct cpuinfo_mips *c)
617{
4194318c 618 decode_configs(c);
1da177e4
LT		 619 switch (c->processor_id & 0xff00) {
620 case PRID_IMP_4KC:
621 c->cputype = CPU_4KC;
1da177e4
LT		 622 break;
623 case PRID_IMP_4KEC:
624 c->cputype = CPU_4KEC;
1da177e4 625 break;
2b07bd02
RB		 626 case PRID_IMP_4KECR2:
627 c->cputype = CPU_4KEC;
2b07bd02 628 break;
1da177e4 629 case PRID_IMP_4KSC:
8afcb5d8 630 case PRID_IMP_4KSD:
1da177e4 631 c->cputype = CPU_4KSC;
1da177e4
LT		 632 break;
633 case PRID_IMP_5KC:
634 c->cputype = CPU_5KC;
1da177e4
LT		 635 break;
636 case PRID_IMP_20KC:
637 c->cputype = CPU_20KC;
1da177e4
LT		 638 break;
639 case PRID_IMP_24K:
e50c0a8f 640 case PRID_IMP_24KE:
1da177e4 641 c->cputype = CPU_24K;
1da177e4
LT		 642 break;
643 case PRID_IMP_25KF:
644 c->cputype = CPU_25KF;
1da177e4 645 break;
bbc7f22f
RB		 646 case PRID_IMP_34K:
647 c->cputype = CPU_34K;
bbc7f22f 648 break;
c620953c
CD		 649 case PRID_IMP_74K:
650 c->cputype = CPU_74K;
651 break;
1da177e4
LT		 652 }
653}
654
655static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
656{
4194318c 657 decode_configs(c);
1da177e4
LT		 658 switch (c->processor_id & 0xff00) {
659 case PRID_IMP_AU1_REV1:
660 case PRID_IMP_AU1_REV2:
661 switch ((c->processor_id >> 24) & 0xff) {
662 case 0:
a3dddd56 663 c->cputype = CPU_AU1000;
1da177e4
LT		 664 break;
665 case 1:
666 c->cputype = CPU_AU1500;
667 break;
668 case 2:
669 c->cputype = CPU_AU1100;
670 break;
671 case 3:
672 c->cputype = CPU_AU1550;
673 break;
e3ad1c23
PP		 674 case 4:
675 c->cputype = CPU_AU1200;
676 break;
1da177e4
LT		 677 default:
678 panic("Unknown Au Core!");
679 break;
680 }
1da177e4
LT		 681 break;
682 }
683}
684
685static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
686{
4194318c 687 decode_configs(c);
02cf2119
RB		 688
689 /*
690 * For historical reasons the SB1 comes with it's own variant of
691 * cache code which eventually will be folded into c-r4k.c. Until
692 * then we pretend it's got it's own cache architecture.
693 */
d121ced2 694 c->options &= ~MIPS_CPU_4K_CACHE;
02cf2119
RB		 695 c->options |= MIPS_CPU_SB1_CACHE;
696
1da177e4
LT		 697 switch (c->processor_id & 0xff00) {
698 case PRID_IMP_SB1:
699 c->cputype = CPU_SB1;
1da177e4 700 /* FPU in pass1 is known to have issues. */
aa32374a 701 if ((c->processor_id & 0xff) < 0x02)
010b853b 702 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 703 break;
93ce2f52
AI		 704 case PRID_IMP_SB1A:
705 c->cputype = CPU_SB1A;
706 break;
1da177e4
LT		 707 }
708}
709
710static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
711{
4194318c 712 decode_configs(c);
1da177e4
LT		 713 switch (c->processor_id & 0xff00) {
714 case PRID_IMP_SR71000:
715 c->cputype = CPU_SR71000;
1da177e4
LT		 716 c->scache.ways = 8;
717 c->tlbsize = 64;
718 break;
719 }
720}
721
bdf21b18
PP		 722static inline void cpu_probe_philips(struct cpuinfo_mips *c)
723{
724 decode_configs(c);
725 switch (c->processor_id & 0xff00) {
726 case PRID_IMP_PR4450:
727 c->cputype = CPU_PR4450;
e7958bb9 728 c->isa_level = MIPS_CPU_ISA_M32R1;
bdf21b18
PP		 729 break;
730 default:
731 panic("Unknown Philips Core!"); /* REVISIT: die? */
732 break;
733 }
734}
735
736
1da177e4
LT		 737__init void cpu_probe(void)
738{
739 struct cpuinfo_mips *c = &current_cpu_data;
740
741 c->processor_id = PRID_IMP_UNKNOWN;
742 c->fpu_id = FPIR_IMP_NONE;
743 c->cputype = CPU_UNKNOWN;
744
745 c->processor_id = read_c0_prid();
746 switch (c->processor_id & 0xff0000) {
747 case PRID_COMP_LEGACY:
748 cpu_probe_legacy(c);
749 break;
750 case PRID_COMP_MIPS:
751 cpu_probe_mips(c);
752 break;
753 case PRID_COMP_ALCHEMY:
754 cpu_probe_alchemy(c);
755 break;
756 case PRID_COMP_SIBYTE:
757 cpu_probe_sibyte(c);
758 break;
1da177e4
LT		 759 case PRID_COMP_SANDCRAFT:
760 cpu_probe_sandcraft(c);
761 break;
bdf21b18
PP		 762 case PRID_COMP_PHILIPS:
763 cpu_probe_philips(c);
a3dddd56 764 break;
1da177e4
LT		 765 default:
766 c->cputype = CPU_UNKNOWN;
767 }
4194318c 768 if (c->options & MIPS_CPU_FPU) {
1da177e4 769 c->fpu_id = cpu_get_fpu_id();
4194318c 770
e7958bb9 771 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
b4672d37
RB		 772 c->isa_level == MIPS_CPU_ISA_M32R2 ||
773 c->isa_level == MIPS_CPU_ISA_M64R1 ||
774 c->isa_level == MIPS_CPU_ISA_M64R2) {
4194318c
RB		 775 if (c->fpu_id & MIPS_FPIR_3D)
776 c->ases |= MIPS_ASE_MIPS3D;
777 }
778 }
1da177e4
LT		 779}
780
781__init void cpu_report(void)
782{
783 struct cpuinfo_mips *c = &current_cpu_data;
784
785 printk("CPU revision is: %08x\n", c->processor_id);
786 if (c->options & MIPS_CPU_FPU)
787 printk("FPU revision is: %08x\n", c->fpu_id);
788}
Linux kernel - Deliverables
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