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Merge tag 'samsung-fixes-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
69f24d17 23#include <asm/cpu-type.h>
1da177e4
LT		 24#include <asm/fpu.h>
25#include <asm/mipsregs.h>
30ee615b 26#include <asm/mipsmtregs.h>
a5e9a69e 27#include <asm/msa.h>
654f57bf 28#include <asm/watch.h>
06372a63 29#include <asm/elf.h>
4f12b91d 30#include <asm/pgtable-bits.h>
a074f0e8 31#include <asm/spram.h>
949e51be
DD		 32#include <asm/uaccess.h>
33
078a55fc 34static int mips_fpu_disabled;
0103d23f
KC		 35
36static int __init fpu_disable(char *s)
37{
38 cpu_data[0].options &= ~MIPS_CPU_FPU;
39 mips_fpu_disabled = 1;
40
41 return 1;
42}
43
44__setup("nofpu", fpu_disable);
45
078a55fc 46int mips_dsp_disabled;
0103d23f
KC		 47
48static int __init dsp_disable(char *s)
49{
ee80f7c7 50 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 51 mips_dsp_disabled = 1;
52
53 return 1;
54}
55
56__setup("nodsp", dsp_disable);
57
3d528b32
MC		 58static int mips_htw_disabled;
59
60static int __init htw_disable(char *s)
61{
62 mips_htw_disabled = 1;
63 cpu_data[0].options &= ~MIPS_CPU_HTW;
64 write_c0_pwctl(read_c0_pwctl() &
65 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
66
67 return 1;
68}
69
70__setup("nohtw", htw_disable);
71
9267a30d
MSJ		 72static inline void check_errata(void)
73{
74 struct cpuinfo_mips *c = &current_cpu_data;
75
69f24d17 76 switch (current_cpu_type()) {
9267a30d
MSJ		 77 case CPU_34K:
78 /*
79 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 80 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 81 * making use of VPE1 will be responsable for that VPE.
82 */
83 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
84 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
85 break;
86 default:
87 break;
88 }
89}
90
1da177e4
LT		 91void __init check_bugs32(void)
92{
9267a30d 93 check_errata();
1da177e4
LT		 94}
95
96/*
97 * Probe whether cpu has config register by trying to play with
98 * alternate cache bit and see whether it matters.
99 * It's used by cpu_probe to distinguish between R3000A and R3081.
100 */
101static inline int cpu_has_confreg(void)
102{
103#ifdef CONFIG_CPU_R3000
104 extern unsigned long r3k_cache_size(unsigned long);
105 unsigned long size1, size2;
106 unsigned long cfg = read_c0_conf();
107
108 size1 = r3k_cache_size(ST0_ISC);
109 write_c0_conf(cfg ^ R30XX_CONF_AC);
110 size2 = r3k_cache_size(ST0_ISC);
111 write_c0_conf(cfg);
112 return size1 != size2;
113#else
114 return 0;
115#endif
116}
117
c094c99e
RM		 118static inline void set_elf_platform(int cpu, const char *plat)
119{
120 if (cpu == 0)
121 __elf_platform = plat;
122}
123
1da177e4
LT		 124/*
125 * Get the FPU Implementation/Revision.
126 */
127static inline unsigned long cpu_get_fpu_id(void)
128{
129 unsigned long tmp, fpu_id;
130
131 tmp = read_c0_status();
597ce172 132 __enable_fpu(FPU_AS_IS);
1da177e4
LT		 133 fpu_id = read_32bit_cp1_register(CP1_REVISION);
134 write_c0_status(tmp);
135 return fpu_id;
136}
137
138/*
139 * Check the CPU has an FPU the official way.
140 */
141static inline int __cpu_has_fpu(void)
142{
8ff374b9 143 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
1da177e4
LT		 144}
145
a5e9a69e
PB		 146static inline unsigned long cpu_get_msa_id(void)
147{
3587ea88 148 unsigned long status, msa_id;
a5e9a69e
PB		 149
150 status = read_c0_status();
151 __enable_fpu(FPU_64BIT);
a5e9a69e
PB		 152 enable_msa();
153 msa_id = read_msa_ir();
3587ea88 154 disable_msa();
a5e9a69e
PB		 155 write_c0_status(status);
156 return msa_id;
157}
158
91dfc423
GR		 159static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
160{
161#ifdef __NEED_VMBITS_PROBE
5b7efa89 162 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 163 back_to_back_c0_hazard();
5b7efa89 164 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 165#endif
166}
167
078a55fc 168static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 169{
170 switch (isa) {
171 case MIPS_CPU_ISA_M64R2:
172 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
173 case MIPS_CPU_ISA_M64R1:
174 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
175 case MIPS_CPU_ISA_V:
176 c->isa_level |= MIPS_CPU_ISA_V;
177 case MIPS_CPU_ISA_IV:
178 c->isa_level |= MIPS_CPU_ISA_IV;
179 case MIPS_CPU_ISA_III:
1990e542 180 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 181 break;
182
183 case MIPS_CPU_ISA_M32R2:
184 c->isa_level |= MIPS_CPU_ISA_M32R2;
185 case MIPS_CPU_ISA_M32R1:
186 c->isa_level |= MIPS_CPU_ISA_M32R1;
187 case MIPS_CPU_ISA_II:
188 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 189 break;
190 }
191}
192
078a55fc 193static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 194 "Unsupported ISA type, c0.config0: %d.";
195
75b5b5e0
LY		 196static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
197{
198 unsigned int config6;
d83b0e82
JH		 199
200 /* It's implementation dependent how the FTLB can be enabled */
201 switch (c->cputype) {
202 case CPU_PROAPTIV:
203 case CPU_P5600:
204 /* proAptiv & related cores use Config6 to enable the FTLB */
75b5b5e0
LY		 205 config6 = read_c0_config6();
206 if (enable)
207 /* Enable FTLB */
208 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
209 else
210 /* Disable FTLB */
211 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
212 back_to_back_c0_hazard();
d83b0e82 213 break;
75b5b5e0
LY		 214 }
215}
216
2fa36399
KC		 217static inline unsigned int decode_config0(struct cpuinfo_mips *c)
218{
219 unsigned int config0;
220 int isa;
221
222 config0 = read_c0_config();
223
75b5b5e0
LY		 224 /*
225 * Look for Standard TLB or Dual VTLB and FTLB
226 */
227 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
228 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 229 c->options |= MIPS_CPU_TLB;
75b5b5e0 230
2fa36399
KC		 231 isa = (config0 & MIPS_CONF_AT) >> 13;
232 switch (isa) {
233 case 0:
234 switch ((config0 & MIPS_CONF_AR) >> 10) {
235 case 0:
a96102be 236 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 237 break;
238 case 1:
a96102be 239 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 240 break;
241 default:
242 goto unknown;
243 }
244 break;
245 case 2:
246 switch ((config0 & MIPS_CONF_AR) >> 10) {
247 case 0:
a96102be 248 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 249 break;
250 case 1:
a96102be 251 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 252 break;
253 default:
254 goto unknown;
255 }
256 break;
257 default:
258 goto unknown;
259 }
260
261 return config0 & MIPS_CONF_M;
262
263unknown:
264 panic(unknown_isa, config0);
265}
266
267static inline unsigned int decode_config1(struct cpuinfo_mips *c)
268{
269 unsigned int config1;
270
271 config1 = read_c0_config1();
272
273 if (config1 & MIPS_CONF1_MD)
274 c->ases |= MIPS_ASE_MDMX;
275 if (config1 & MIPS_CONF1_WR)
276 c->options |= MIPS_CPU_WATCH;
277 if (config1 & MIPS_CONF1_CA)
278 c->ases |= MIPS_ASE_MIPS16;
279 if (config1 & MIPS_CONF1_EP)
280 c->options |= MIPS_CPU_EJTAG;
281 if (config1 & MIPS_CONF1_FP) {
282 c->options |= MIPS_CPU_FPU;
283 c->options |= MIPS_CPU_32FPR;
284 }
75b5b5e0 285 if (cpu_has_tlb) {
2fa36399 286 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 287 c->tlbsizevtlb = c->tlbsize;
288 c->tlbsizeftlbsets = 0;
289 }
2fa36399
KC		 290
291 return config1 & MIPS_CONF_M;
292}
293
294static inline unsigned int decode_config2(struct cpuinfo_mips *c)
295{
296 unsigned int config2;
297
298 config2 = read_c0_config2();
299
300 if (config2 & MIPS_CONF2_SL)
301 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
302
303 return config2 & MIPS_CONF_M;
304}
305
306static inline unsigned int decode_config3(struct cpuinfo_mips *c)
307{
308 unsigned int config3;
309
310 config3 = read_c0_config3();
311
b2ab4f08 312 if (config3 & MIPS_CONF3_SM) {
2fa36399 313 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 314 c->options |= MIPS_CPU_RIXI;
315 }
316 if (config3 & MIPS_CONF3_RXI)
317 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 318 if (config3 & MIPS_CONF3_DSP)
319 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 320 if (config3 & MIPS_CONF3_DSP2P)
321 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 322 if (config3 & MIPS_CONF3_VINT)
323 c->options |= MIPS_CPU_VINT;
324 if (config3 & MIPS_CONF3_VEIC)
325 c->options |= MIPS_CPU_VEIC;
326 if (config3 & MIPS_CONF3_MT)
327 c->ases |= MIPS_ASE_MIPSMT;
328 if (config3 & MIPS_CONF3_ULRI)
329 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 330 if (config3 & MIPS_CONF3_ISA)
331 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 332 if (config3 & MIPS_CONF3_VZ)
333 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 334 if (config3 & MIPS_CONF3_SC)
335 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 336 if (config3 & MIPS_CONF3_MSA)
337 c->ases |= MIPS_ASE_MSA;
3d528b32
MC		 338 /* Only tested on 32-bit cores */
339 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT))
340 c->options |= MIPS_CPU_HTW;
2fa36399
KC		 341
342 return config3 & MIPS_CONF_M;
343}
344
345static inline unsigned int decode_config4(struct cpuinfo_mips *c)
346{
347 unsigned int config4;
75b5b5e0
LY		 348 unsigned int newcf4;
349 unsigned int mmuextdef;
350 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 351
352 config4 = read_c0_config4();
353
1745c1ef
LY		 354 if (cpu_has_tlb) {
355 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
356 c->options |= MIPS_CPU_TLBINV;
75b5b5e0
LY		 357 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
358 switch (mmuextdef) {
359 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
360 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
361 c->tlbsizevtlb = c->tlbsize;
362 break;
363 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
364 c->tlbsizevtlb +=
365 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
366 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
367 c->tlbsize = c->tlbsizevtlb;
368 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
369 /* fall through */
370 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
371 newcf4 = (config4 & ~ftlb_page) |
372 (page_size_ftlb(mmuextdef) <<
373 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
374 write_c0_config4(newcf4);
375 back_to_back_c0_hazard();
376 config4 = read_c0_config4();
377 if (config4 != newcf4) {
378 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
379 PAGE_SIZE, config4);
380 /* Switch FTLB off */
381 set_ftlb_enable(c, 0);
382 break;
383 }
384 c->tlbsizeftlbsets = 1 <<
385 ((config4 & MIPS_CONF4_FTLBSETS) >>
386 MIPS_CONF4_FTLBSETS_SHIFT);
387 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
388 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
389 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
390 break;
391 }
1745c1ef
LY		 392 }
393
2fa36399
KC		 394 c->kscratch_mask = (config4 >> 16) & 0xff;
395
396 return config4 & MIPS_CONF_M;
397}
398
8b8a7634
RB		 399static inline unsigned int decode_config5(struct cpuinfo_mips *c)
400{
401 unsigned int config5;
402
403 config5 = read_c0_config5();
404 config5 &= ~MIPS_CONF5_UFR;
405 write_c0_config5(config5);
406
49016748
MC		 407 if (config5 & MIPS_CONF5_EVA)
408 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 409 if (config5 & MIPS_CONF5_MRP)
410 c->options |= MIPS_CPU_MAAR;
49016748 411
8b8a7634
RB		 412 return config5 & MIPS_CONF_M;
413}
414
078a55fc 415static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 416{
417 int ok;
418
419 /* MIPS32 or MIPS64 compliant CPU. */
420 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
421 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
422
423 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
424
75b5b5e0
LY		 425 /* Enable FTLB if present */
426 set_ftlb_enable(c, 1);
427
2fa36399 428 ok = decode_config0(c); /* Read Config registers. */
70342287 429 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 430 if (ok)
431 ok = decode_config1(c);
432 if (ok)
433 ok = decode_config2(c);
434 if (ok)
435 ok = decode_config3(c);
436 if (ok)
437 ok = decode_config4(c);
8b8a7634
RB		 438 if (ok)
439 ok = decode_config5(c);
2fa36399
KC		 440
441 mips_probe_watch_registers(c);
442
6575b1d4
LY		 443 if (cpu_has_rixi) {
444 /* Enable the RIXI exceptions */
445 write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
446 back_to_back_c0_hazard();
447 /* Verify the IEC bit is set */
448 if (read_c0_pagegrain() & PG_IEC)
449 c->options |= MIPS_CPU_RIXIEX;
450 }
451
0ee958e1 452#ifndef CONFIG_MIPS_CPS
30ee615b 453 if (cpu_has_mips_r2) {
45b585c8 454 c->core = get_ebase_cpunum();
30ee615b
PB		 455 if (cpu_has_mipsmt)
456 c->core >>= fls(core_nvpes()) - 1;
457 }
0ee958e1 458#endif
2fa36399
KC		 459}
460
02cf2119 461#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 462 | MIPS_CPU_COUNTER)
463
cea7e2df 464static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 465{
8ff374b9 466 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 467 case PRID_IMP_R2000:
468 c->cputype = CPU_R2000;
cea7e2df 469 __cpu_name[cpu] = "R2000";
02cf2119 470 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 471 MIPS_CPU_NOFPUEX;
1da177e4
LT		 472 if (__cpu_has_fpu())
473 c->options |= MIPS_CPU_FPU;
474 c->tlbsize = 64;
475 break;
476 case PRID_IMP_R3000:
8ff374b9 477 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 478 if (cpu_has_confreg()) {
1da177e4 479 c->cputype = CPU_R3081E;
cea7e2df
RB		 480 __cpu_name[cpu] = "R3081";
481 } else {
1da177e4 482 c->cputype = CPU_R3000A;
cea7e2df
RB		 483 __cpu_name[cpu] = "R3000A";
484 }
cea7e2df 485 } else {
1da177e4 486 c->cputype = CPU_R3000;
cea7e2df
RB		 487 __cpu_name[cpu] = "R3000";
488 }
02cf2119 489 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 490 MIPS_CPU_NOFPUEX;
1da177e4
LT		 491 if (__cpu_has_fpu())
492 c->options |= MIPS_CPU_FPU;
493 c->tlbsize = 64;
494 break;
495 case PRID_IMP_R4000:
496 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 497 if ((c->processor_id & PRID_REV_MASK) >=
498 PRID_REV_R4400) {
1da177e4 499 c->cputype = CPU_R4400PC;
cea7e2df
RB		 500 __cpu_name[cpu] = "R4400PC";
501 } else {
1da177e4 502 c->cputype = CPU_R4000PC;
cea7e2df
RB		 503 __cpu_name[cpu] = "R4000PC";
504 }
1da177e4 505 } else {
7f177a52
MR		 506 int cca = read_c0_config() & CONF_CM_CMASK;
507 int mc;
508
509 /*
510 * SC and MC versions can't be reliably told apart,
511 * but only the latter support coherent caching
512 * modes so assume the firmware has set the KSEG0
513 * coherency attribute reasonably (if uncached, we
514 * assume SC).
515 */
516 switch (cca) {
517 case CONF_CM_CACHABLE_CE:
518 case CONF_CM_CACHABLE_COW:
519 case CONF_CM_CACHABLE_CUW:
520 mc = 1;
521 break;
522 default:
523 mc = 0;
524 break;
525 }
8ff374b9
MR		 526 if ((c->processor_id & PRID_REV_MASK) >=
527 PRID_REV_R4400) {
7f177a52
MR		 528 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
529 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 530 } else {
7f177a52
MR		 531 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
532 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 533 }
1da177e4
LT		 534 }
535
a96102be 536 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 537 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 538 MIPS_CPU_WATCH | MIPS_CPU_VCE |
539 MIPS_CPU_LLSC;
1da177e4
LT		 540 c->tlbsize = 48;
541 break;
542 case PRID_IMP_VR41XX:
9f91e506
YY		 543 set_isa(c, MIPS_CPU_ISA_III);
544 c->options = R4K_OPTS;
545 c->tlbsize = 32;
1da177e4 546 switch (c->processor_id & 0xf0) {
1da177e4
LT		 547 case PRID_REV_VR4111:
548 c->cputype = CPU_VR4111;
cea7e2df 549 __cpu_name[cpu] = "NEC VR4111";
1da177e4 550 break;
1da177e4
LT		 551 case PRID_REV_VR4121:
552 c->cputype = CPU_VR4121;
cea7e2df 553 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 554 break;
555 case PRID_REV_VR4122:
cea7e2df 556 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 557 c->cputype = CPU_VR4122;
cea7e2df
RB		 558 __cpu_name[cpu] = "NEC VR4122";
559 } else {
1da177e4 560 c->cputype = CPU_VR4181A;
cea7e2df
RB		 561 __cpu_name[cpu] = "NEC VR4181A";
562 }
1da177e4
LT		 563 break;
564 case PRID_REV_VR4130:
cea7e2df 565 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 566 c->cputype = CPU_VR4131;
cea7e2df
RB		 567 __cpu_name[cpu] = "NEC VR4131";
568 } else {
1da177e4 569 c->cputype = CPU_VR4133;
9f91e506 570 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 571 __cpu_name[cpu] = "NEC VR4133";
572 }
1da177e4
LT		 573 break;
574 default:
575 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
576 c->cputype = CPU_VR41XX;
cea7e2df 577 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 578 break;
579 }
1da177e4
LT		 580 break;
581 case PRID_IMP_R4300:
582 c->cputype = CPU_R4300;
cea7e2df 583 __cpu_name[cpu] = "R4300";
a96102be 584 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 585 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 586 MIPS_CPU_LLSC;
1da177e4
LT		 587 c->tlbsize = 32;
588 break;
589 case PRID_IMP_R4600:
590 c->cputype = CPU_R4600;
cea7e2df 591 __cpu_name[cpu] = "R4600";
a96102be 592 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 593 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
594 MIPS_CPU_LLSC;
1da177e4
LT		 595 c->tlbsize = 48;
596 break;
597 #if 0
03751e79 598 case PRID_IMP_R4650:
1da177e4
LT		 599 /*
600 * This processor doesn't have an MMU, so it's not
601 * "real easy" to run Linux on it. It is left purely
602 * for documentation. Commented out because it shares
603 * it's c0_prid id number with the TX3900.
604 */
a3dddd56 605 c->cputype = CPU_R4650;
cea7e2df 606 __cpu_name[cpu] = "R4650";
a96102be 607 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 608 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 609 c->tlbsize = 48;
1da177e4
LT		 610 break;
611 #endif
612 case PRID_IMP_TX39:
02cf2119 613 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 614
615 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
616 c->cputype = CPU_TX3927;
cea7e2df 617 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 618 c->tlbsize = 64;
619 } else {
8ff374b9 620 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 621 case PRID_REV_TX3912:
622 c->cputype = CPU_TX3912;
cea7e2df 623 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 624 c->tlbsize = 32;
625 break;
626 case PRID_REV_TX3922:
627 c->cputype = CPU_TX3922;
cea7e2df 628 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 629 c->tlbsize = 64;
630 break;
1da177e4
LT		 631 }
632 }
633 break;
634 case PRID_IMP_R4700:
635 c->cputype = CPU_R4700;
cea7e2df 636 __cpu_name[cpu] = "R4700";
a96102be 637 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 638 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 639 MIPS_CPU_LLSC;
1da177e4
LT		 640 c->tlbsize = 48;
641 break;
642 case PRID_IMP_TX49:
643 c->cputype = CPU_TX49XX;
cea7e2df 644 __cpu_name[cpu] = "R49XX";
a96102be 645 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 646 c->options = R4K_OPTS | MIPS_CPU_LLSC;
647 if (!(c->processor_id & 0x08))
648 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
649 c->tlbsize = 48;
650 break;
651 case PRID_IMP_R5000:
652 c->cputype = CPU_R5000;
cea7e2df 653 __cpu_name[cpu] = "R5000";
a96102be 654 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 655 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 656 MIPS_CPU_LLSC;
1da177e4
LT		 657 c->tlbsize = 48;
658 break;
659 case PRID_IMP_R5432:
660 c->cputype = CPU_R5432;
cea7e2df 661 __cpu_name[cpu] = "R5432";
a96102be 662 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 663 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 664 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 665 c->tlbsize = 48;
666 break;
667 case PRID_IMP_R5500:
668 c->cputype = CPU_R5500;
cea7e2df 669 __cpu_name[cpu] = "R5500";
a96102be 670 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 671 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 672 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 673 c->tlbsize = 48;
674 break;
675 case PRID_IMP_NEVADA:
676 c->cputype = CPU_NEVADA;
cea7e2df 677 __cpu_name[cpu] = "Nevada";
a96102be 678 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 679 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 680 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 681 c->tlbsize = 48;
682 break;
683 case PRID_IMP_R6000:
684 c->cputype = CPU_R6000;
cea7e2df 685 __cpu_name[cpu] = "R6000";
a96102be 686 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 687 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 688 MIPS_CPU_LLSC;
1da177e4
LT		 689 c->tlbsize = 32;
690 break;
691 case PRID_IMP_R6000A:
692 c->cputype = CPU_R6000A;
cea7e2df 693 __cpu_name[cpu] = "R6000A";
a96102be 694 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 695 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 696 MIPS_CPU_LLSC;
1da177e4
LT		 697 c->tlbsize = 32;
698 break;
699 case PRID_IMP_RM7000:
700 c->cputype = CPU_RM7000;
cea7e2df 701 __cpu_name[cpu] = "RM7000";
a96102be 702 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 703 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 704 MIPS_CPU_LLSC;
1da177e4 705 /*
70342287 706 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 707 * the RM7000 v2.0 indicates if the TLB has 48 or 64
708 * entries.
709 *
70342287
RB		 710 * 29 1 => 64 entry JTLB
711 * 0 => 48 entry JTLB
1da177e4
LT		 712 */
713 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 714 break;
715 case PRID_IMP_R8000:
716 c->cputype = CPU_R8000;
cea7e2df 717 __cpu_name[cpu] = "RM8000";
a96102be 718 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 719 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 720 MIPS_CPU_FPU | MIPS_CPU_32FPR |
721 MIPS_CPU_LLSC;
1da177e4
LT		 722 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
723 break;
724 case PRID_IMP_R10000:
725 c->cputype = CPU_R10000;
cea7e2df 726 __cpu_name[cpu] = "R10000";
a96102be 727 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 728 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 729 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 730 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 731 MIPS_CPU_LLSC;
1da177e4
LT		 732 c->tlbsize = 64;
733 break;
734 case PRID_IMP_R12000:
735 c->cputype = CPU_R12000;
cea7e2df 736 __cpu_name[cpu] = "R12000";
a96102be 737 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 738 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 739 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 740 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 741 MIPS_CPU_LLSC;
1da177e4
LT		 742 c->tlbsize = 64;
743 break;
44d921b2
K		 744 case PRID_IMP_R14000:
745 c->cputype = CPU_R14000;
cea7e2df 746 __cpu_name[cpu] = "R14000";
a96102be 747 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 748 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 749 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 750 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 751 MIPS_CPU_LLSC;
44d921b2
K		 752 c->tlbsize = 64;
753 break;
26859198 754 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 755 switch (c->processor_id & PRID_REV_MASK) {
756 case PRID_REV_LOONGSON2E:
c579d310
HC		 757 c->cputype = CPU_LOONGSON2;
758 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 759 set_elf_platform(cpu, "loongson2e");
7352c8b1 760 set_isa(c, MIPS_CPU_ISA_III);
5aac1e8a
RM		 761 break;
762 case PRID_REV_LOONGSON2F:
c579d310
HC		 763 c->cputype = CPU_LOONGSON2;
764 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 765 set_elf_platform(cpu, "loongson2f");
7352c8b1 766 set_isa(c, MIPS_CPU_ISA_III);
5aac1e8a 767 break;
c579d310
HC		 768 case PRID_REV_LOONGSON3A:
769 c->cputype = CPU_LOONGSON3;
770 __cpu_name[cpu] = "ICT Loongson-3";
771 set_elf_platform(cpu, "loongson3a");
7352c8b1 772 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 773 break;
e7841be5
HC		 774 case PRID_REV_LOONGSON3B_R1:
775 case PRID_REV_LOONGSON3B_R2:
776 c->cputype = CPU_LOONGSON3;
777 __cpu_name[cpu] = "ICT Loongson-3";
778 set_elf_platform(cpu, "loongson3b");
7352c8b1 779 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 780 break;
5aac1e8a
RM		 781 }
782
2a21c730
FZ		 783 c->options = R4K_OPTS |
784 MIPS_CPU_FPU | MIPS_CPU_LLSC |
785 MIPS_CPU_32FPR;
786 c->tlbsize = 64;
cc94ea31 787 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 788 break;
26859198 789 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 790 decode_configs(c);
b4672d37 791
2fa36399 792 c->cputype = CPU_LOONGSON1;
1da177e4 793
2fa36399
KC		 794 switch (c->processor_id & PRID_REV_MASK) {
795 case PRID_REV_LOONGSON1B:
796 __cpu_name[cpu] = "Loongson 1B";
b4672d37 797 break;
b4672d37 798 }
4194318c 799
2fa36399 800 break;
1da177e4 801 }
1da177e4
LT		 802}
803
cea7e2df 804static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 805{
4f12b91d 806 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 807 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 808 case PRID_IMP_4KC:
809 c->cputype = CPU_4KC;
4f12b91d 810 c->writecombine = _CACHE_UNCACHED;
cea7e2df 811 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 812 break;
813 case PRID_IMP_4KEC:
2b07bd02
RB		 814 case PRID_IMP_4KECR2:
815 c->cputype = CPU_4KEC;
4f12b91d 816 c->writecombine = _CACHE_UNCACHED;
cea7e2df 817 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 818 break;
1da177e4 819 case PRID_IMP_4KSC:
8afcb5d8 820 case PRID_IMP_4KSD:
1da177e4 821 c->cputype = CPU_4KSC;
4f12b91d 822 c->writecombine = _CACHE_UNCACHED;
cea7e2df 823 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 824 break;
825 case PRID_IMP_5KC:
826 c->cputype = CPU_5KC;
4f12b91d 827 c->writecombine = _CACHE_UNCACHED;
cea7e2df 828 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 829 break;
78d4803f
LY		 830 case PRID_IMP_5KE:
831 c->cputype = CPU_5KE;
4f12b91d 832 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 833 __cpu_name[cpu] = "MIPS 5KE";
834 break;
1da177e4
LT		 835 case PRID_IMP_20KC:
836 c->cputype = CPU_20KC;
4f12b91d 837 c->writecombine = _CACHE_UNCACHED;
cea7e2df 838 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 839 break;
840 case PRID_IMP_24K:
841 c->cputype = CPU_24K;
4f12b91d 842 c->writecombine = _CACHE_UNCACHED;
cea7e2df 843 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 844 break;
42f3caef
JC		 845 case PRID_IMP_24KE:
846 c->cputype = CPU_24K;
4f12b91d 847 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 848 __cpu_name[cpu] = "MIPS 24KEc";
849 break;
1da177e4
LT		 850 case PRID_IMP_25KF:
851 c->cputype = CPU_25KF;
4f12b91d 852 c->writecombine = _CACHE_UNCACHED;
cea7e2df 853 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 854 break;
bbc7f22f
RB		 855 case PRID_IMP_34K:
856 c->cputype = CPU_34K;
4f12b91d 857 c->writecombine = _CACHE_UNCACHED;
cea7e2df 858 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 859 break;
c620953c
CD		 860 case PRID_IMP_74K:
861 c->cputype = CPU_74K;
4f12b91d 862 c->writecombine = _CACHE_UNCACHED;
cea7e2df 863 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 864 break;
113c62d9
SH		 865 case PRID_IMP_M14KC:
866 c->cputype = CPU_M14KC;
4f12b91d 867 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 868 __cpu_name[cpu] = "MIPS M14Kc";
869 break;
f8fa4811
SH		 870 case PRID_IMP_M14KEC:
871 c->cputype = CPU_M14KEC;
4f12b91d 872 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 873 __cpu_name[cpu] = "MIPS M14KEc";
874 break;
39b8d525
RB		 875 case PRID_IMP_1004K:
876 c->cputype = CPU_1004K;
4f12b91d 877 c->writecombine = _CACHE_UNCACHED;
cea7e2df 878 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 879 break;
006a851b 880 case PRID_IMP_1074K:
442e14a2 881 c->cputype = CPU_1074K;
4f12b91d 882 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 883 __cpu_name[cpu] = "MIPS 1074Kc";
884 break;
b5f065e7
LY		 885 case PRID_IMP_INTERAPTIV_UP:
886 c->cputype = CPU_INTERAPTIV;
887 __cpu_name[cpu] = "MIPS interAptiv";
888 break;
889 case PRID_IMP_INTERAPTIV_MP:
890 c->cputype = CPU_INTERAPTIV;
891 __cpu_name[cpu] = "MIPS interAptiv (multi)";
892 break;
b0d4d300
LY		 893 case PRID_IMP_PROAPTIV_UP:
894 c->cputype = CPU_PROAPTIV;
895 __cpu_name[cpu] = "MIPS proAptiv";
896 break;
897 case PRID_IMP_PROAPTIV_MP:
898 c->cputype = CPU_PROAPTIV;
899 __cpu_name[cpu] = "MIPS proAptiv (multi)";
900 break;
829dcc0a
JH		 901 case PRID_IMP_P5600:
902 c->cputype = CPU_P5600;
903 __cpu_name[cpu] = "MIPS P5600";
904 break;
9943ed92
LY		 905 case PRID_IMP_M5150:
906 c->cputype = CPU_M5150;
907 __cpu_name[cpu] = "MIPS M5150";
908 break;
1da177e4 909 }
0b6d497f 910
75b5b5e0
LY		 911 decode_configs(c);
912
0b6d497f 913 spram_config();
1da177e4
LT		 914}
915
cea7e2df 916static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 917{
4194318c 918 decode_configs(c);
8ff374b9 919 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 920 case PRID_IMP_AU1_REV1:
921 case PRID_IMP_AU1_REV2:
270717a8 922 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 923 switch ((c->processor_id >> 24) & 0xff) {
924 case 0:
cea7e2df 925 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 926 break;
927 case 1:
cea7e2df 928 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 929 break;
930 case 2:
cea7e2df 931 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 932 break;
933 case 3:
cea7e2df 934 __cpu_name[cpu] = "Au1550";
1da177e4 935 break;
e3ad1c23 936 case 4:
cea7e2df 937 __cpu_name[cpu] = "Au1200";
8ff374b9 938 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 939 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 940 break;
941 case 5:
cea7e2df 942 __cpu_name[cpu] = "Au1210";
e3ad1c23 943 break;
1da177e4 944 default:
270717a8 945 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 946 break;
947 }
1da177e4
LT		 948 break;
949 }
950}
951
cea7e2df 952static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 953{
4194318c 954 decode_configs(c);
02cf2119 955
4f12b91d 956 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 957 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 958 case PRID_IMP_SB1:
959 c->cputype = CPU_SB1;
cea7e2df 960 __cpu_name[cpu] = "SiByte SB1";
1da177e4 961 /* FPU in pass1 is known to have issues. */
8ff374b9 962 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 963 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 964 break;
93ce2f52
AI		 965 case PRID_IMP_SB1A:
966 c->cputype = CPU_SB1A;
cea7e2df 967 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 968 break;
1da177e4
LT		 969 }
970}
971
cea7e2df 972static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 973{
4194318c 974 decode_configs(c);
8ff374b9 975 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 976 case PRID_IMP_SR71000:
977 c->cputype = CPU_SR71000;
cea7e2df 978 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 979 c->scache.ways = 8;
980 c->tlbsize = 64;
981 break;
982 }
983}
984
cea7e2df 985static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 986{
987 decode_configs(c);
8ff374b9 988 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 989 case PRID_IMP_PR4450:
990 c->cputype = CPU_PR4450;
cea7e2df 991 __cpu_name[cpu] = "Philips PR4450";
a96102be 992 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 993 break;
bdf21b18
PP		 994 }
995}
996
cea7e2df 997static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 998{
999 decode_configs(c);
8ff374b9 1000 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1001 case PRID_IMP_BMIPS32_REV4:
1002 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1003 c->cputype = CPU_BMIPS32;
1004 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1005 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1006 break;
1007 case PRID_IMP_BMIPS3300:
1008 case PRID_IMP_BMIPS3300_ALT:
1009 case PRID_IMP_BMIPS3300_BUG:
1010 c->cputype = CPU_BMIPS3300;
1011 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1012 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1013 break;
1014 case PRID_IMP_BMIPS43XX: {
8ff374b9 1015 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1016
1017 if (rev >= PRID_REV_BMIPS4380_LO &&
1018 rev <= PRID_REV_BMIPS4380_HI) {
1019 c->cputype = CPU_BMIPS4380;
1020 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1021 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 1022 } else {
1023 c->cputype = CPU_BMIPS4350;
1024 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1025 set_elf_platform(cpu, "bmips4350");
602977b0 1026 }
0de663ef 1027 break;
602977b0
KC		 1028 }
1029 case PRID_IMP_BMIPS5000:
1030 c->cputype = CPU_BMIPS5000;
1031 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1032 set_elf_platform(cpu, "bmips5000");
602977b0 1033 c->options |= MIPS_CPU_ULRI;
0de663ef 1034 break;
1c0c13eb
AJ		 1035 }
1036}
1037
0dd4781b
DD		 1038static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1039{
1040 decode_configs(c);
8ff374b9 1041 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1042 case PRID_IMP_CAVIUM_CN38XX:
1043 case PRID_IMP_CAVIUM_CN31XX:
1044 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1045 c->cputype = CPU_CAVIUM_OCTEON;
1046 __cpu_name[cpu] = "Cavium Octeon";
1047 goto platform;
0dd4781b
DD		 1048 case PRID_IMP_CAVIUM_CN58XX:
1049 case PRID_IMP_CAVIUM_CN56XX:
1050 case PRID_IMP_CAVIUM_CN50XX:
1051 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1052 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1053 __cpu_name[cpu] = "Cavium Octeon+";
1054platform:
c094c99e 1055 set_elf_platform(cpu, "octeon");
0dd4781b 1056 break;
a1431b61 1057 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1058 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1059 case PRID_IMP_CAVIUM_CN66XX:
1060 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1061 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1062 c->cputype = CPU_CAVIUM_OCTEON2;
1063 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1064 set_elf_platform(cpu, "octeon2");
0e56b385 1065 break;
af04bb85
DD		 1066 case PRID_IMP_CAVIUM_CN70XX:
1067 case PRID_IMP_CAVIUM_CN78XX:
1068 c->cputype = CPU_CAVIUM_OCTEON3;
1069 __cpu_name[cpu] = "Cavium Octeon III";
1070 set_elf_platform(cpu, "octeon3");
1071 break;
0dd4781b
DD		 1072 default:
1073 printk(KERN_INFO "Unknown Octeon chip!\n");
1074 c->cputype = CPU_UNKNOWN;
1075 break;
1076 }
1077}
1078
83ccf69d
LPC		 1079static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1080{
1081 decode_configs(c);
1082 /* JZRISC does not implement the CP0 counter. */
1083 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1084 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1085 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1086 case PRID_IMP_JZRISC:
1087 c->cputype = CPU_JZRISC;
4f12b91d 1088 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1089 __cpu_name[cpu] = "Ingenic JZRISC";
1090 break;
1091 default:
1092 panic("Unknown Ingenic Processor ID!");
1093 break;
1094 }
1095}
1096
a7117c6b
J		 1097static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1098{
1099 decode_configs(c);
1100
8ff374b9 1101 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1102 c->cputype = CPU_ALCHEMY;
1103 __cpu_name[cpu] = "Au1300";
1104 /* following stuff is not for Alchemy */
1105 return;
1106 }
1107
70342287
RB		 1108 c->options = (MIPS_CPU_TLB |
1109 MIPS_CPU_4KEX |
a7117c6b 1110 MIPS_CPU_COUNTER |
70342287
RB		 1111 MIPS_CPU_DIVEC |
1112 MIPS_CPU_WATCH |
1113 MIPS_CPU_EJTAG |
a7117c6b
J		 1114 MIPS_CPU_LLSC);
1115
8ff374b9 1116 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1117 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1118 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1119 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1120 c->cputype = CPU_XLP;
1121 __cpu_name[cpu] = "Broadcom XLPII";
1122 break;
1123
2aa54b20
J		 1124 case PRID_IMP_NETLOGIC_XLP8XX:
1125 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1126 c->cputype = CPU_XLP;
1127 __cpu_name[cpu] = "Netlogic XLP";
1128 break;
1129
a7117c6b
J		 1130 case PRID_IMP_NETLOGIC_XLR732:
1131 case PRID_IMP_NETLOGIC_XLR716:
1132 case PRID_IMP_NETLOGIC_XLR532:
1133 case PRID_IMP_NETLOGIC_XLR308:
1134 case PRID_IMP_NETLOGIC_XLR532C:
1135 case PRID_IMP_NETLOGIC_XLR516C:
1136 case PRID_IMP_NETLOGIC_XLR508C:
1137 case PRID_IMP_NETLOGIC_XLR308C:
1138 c->cputype = CPU_XLR;
1139 __cpu_name[cpu] = "Netlogic XLR";
1140 break;
1141
1142 case PRID_IMP_NETLOGIC_XLS608:
1143 case PRID_IMP_NETLOGIC_XLS408:
1144 case PRID_IMP_NETLOGIC_XLS404:
1145 case PRID_IMP_NETLOGIC_XLS208:
1146 case PRID_IMP_NETLOGIC_XLS204:
1147 case PRID_IMP_NETLOGIC_XLS108:
1148 case PRID_IMP_NETLOGIC_XLS104:
1149 case PRID_IMP_NETLOGIC_XLS616B:
1150 case PRID_IMP_NETLOGIC_XLS608B:
1151 case PRID_IMP_NETLOGIC_XLS416B:
1152 case PRID_IMP_NETLOGIC_XLS412B:
1153 case PRID_IMP_NETLOGIC_XLS408B:
1154 case PRID_IMP_NETLOGIC_XLS404B:
1155 c->cputype = CPU_XLR;
1156 __cpu_name[cpu] = "Netlogic XLS";
1157 break;
1158
1159 default:
a3d4fb2d 1160 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1161 c->processor_id);
1162 c->cputype = CPU_XLR;
1163 break;
1164 }
1165
a3d4fb2d 1166 if (c->cputype == CPU_XLP) {
a96102be 1167 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1168 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1169 /* This will be updated again after all threads are woken up */
1170 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1171 } else {
a96102be 1172 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1173 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1174 }
7777b939 1175 c->kscratch_mask = 0xf;
a7117c6b
J		 1176}
1177
949e51be
DD		 1178#ifdef CONFIG_64BIT
1179/* For use by uaccess.h */
1180u64 __ua_limit;
1181EXPORT_SYMBOL(__ua_limit);
1182#endif
1183
9966db25 1184const char *__cpu_name[NR_CPUS];
874fd3b5 1185const char *__elf_platform;
9966db25 1186
078a55fc 1187void cpu_probe(void)
1da177e4
LT		 1188{
1189 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1190 unsigned int cpu = smp_processor_id();
1da177e4 1191
70342287 1192 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1193 c->fpu_id = FPIR_IMP_NONE;
1194 c->cputype = CPU_UNKNOWN;
4f12b91d 1195 c->writecombine = _CACHE_UNCACHED;
1da177e4
LT		 1196
1197 c->processor_id = read_c0_prid();
8ff374b9 1198 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1199 case PRID_COMP_LEGACY:
cea7e2df 1200 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1201 break;
1202 case PRID_COMP_MIPS:
cea7e2df 1203 cpu_probe_mips(c, cpu);
1da177e4
LT		 1204 break;
1205 case PRID_COMP_ALCHEMY:
cea7e2df 1206 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1207 break;
1208 case PRID_COMP_SIBYTE:
cea7e2df 1209 cpu_probe_sibyte(c, cpu);
1da177e4 1210 break;
1c0c13eb 1211 case PRID_COMP_BROADCOM:
cea7e2df 1212 cpu_probe_broadcom(c, cpu);
1c0c13eb 1213 break;
1da177e4 1214 case PRID_COMP_SANDCRAFT:
cea7e2df 1215 cpu_probe_sandcraft(c, cpu);
1da177e4 1216 break;
a92b0588 1217 case PRID_COMP_NXP:
cea7e2df 1218 cpu_probe_nxp(c, cpu);
a3dddd56 1219 break;
0dd4781b
DD		 1220 case PRID_COMP_CAVIUM:
1221 cpu_probe_cavium(c, cpu);
1222 break;
83ccf69d
LPC		 1223 case PRID_COMP_INGENIC:
1224 cpu_probe_ingenic(c, cpu);
1225 break;
a7117c6b
J		 1226 case PRID_COMP_NETLOGIC:
1227 cpu_probe_netlogic(c, cpu);
1228 break;
1da177e4 1229 }
dec8b1ca 1230
cea7e2df
RB		 1231 BUG_ON(!__cpu_name[cpu]);
1232 BUG_ON(c->cputype == CPU_UNKNOWN);
1233
dec8b1ca
FBH		 1234 /*
1235 * Platform code can force the cpu type to optimize code
1236 * generation. In that case be sure the cpu type is correctly
1237 * manually setup otherwise it could trigger some nasty bugs.
1238 */
1239 BUG_ON(current_cpu_type() != c->cputype);
1240
0103d23f
KC		 1241 if (mips_fpu_disabled)
1242 c->options &= ~MIPS_CPU_FPU;
1243
1244 if (mips_dsp_disabled)
ee80f7c7 1245 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1246
3d528b32
MC		 1247 if (mips_htw_disabled) {
1248 c->options &= ~MIPS_CPU_HTW;
1249 write_c0_pwctl(read_c0_pwctl() &
1250 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1251 }
1252
4194318c 1253 if (c->options & MIPS_CPU_FPU) {
1da177e4 1254 c->fpu_id = cpu_get_fpu_id();
4194318c 1255
adb37892
DCZ		 1256 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1257 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
4194318c
RB		 1258 if (c->fpu_id & MIPS_FPIR_3D)
1259 c->ases |= MIPS_ASE_MIPS3D;
1260 }
1261 }
9966db25 1262
da4b62cd 1263 if (cpu_has_mips_r2) {
f6771dbb 1264 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1265 /* R2 has Performance Counter Interrupt indicator */
1266 c->options |= MIPS_CPU_PCI;
1267 }
f6771dbb
RB		 1268 else
1269 c->srsets = 1;
91dfc423 1270
a8ad1367 1271 if (cpu_has_msa) {
a5e9a69e 1272 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1273 WARN(c->msa_id & MSA_IR_WRPF,
1274 "Vector register partitioning unimplemented!");
1275 }
a5e9a69e 1276
91dfc423 1277 cpu_probe_vmbits(c);
949e51be
DD		 1278
1279#ifdef CONFIG_64BIT
1280 if (cpu == 0)
1281 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1282#endif
1da177e4
LT		 1283}
1284
078a55fc 1285void cpu_report(void)
1da177e4
LT		 1286{
1287 struct cpuinfo_mips *c = &current_cpu_data;
1288
d9f897c9
LY		 1289 pr_info("CPU%d revision is: %08x (%s)\n",
1290 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1291 if (c->options & MIPS_CPU_FPU)
9966db25 1292 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1293 if (cpu_has_msa)
1294 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1295}
Linux kernel - Deliverables
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