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MIPS: Add defs & probing of [X]ContextConfig
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
f6843626 23#include <asm/cpu-features.h>
69f24d17 24#include <asm/cpu-type.h>
1da177e4
LT		 25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
30ee615b 27#include <asm/mipsmtregs.h>
a5e9a69e 28#include <asm/msa.h>
654f57bf 29#include <asm/watch.h>
06372a63 30#include <asm/elf.h>
4f12b91d 31#include <asm/pgtable-bits.h>
a074f0e8 32#include <asm/spram.h>
949e51be
DD		 33#include <asm/uaccess.h>
34
e14f1db7
PB		 35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
37
7aecd5ca
MR		 38/*
39 * Get the FPU Implementation/Revision.
40 */
41static inline unsigned long cpu_get_fpu_id(void)
42{
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50}
51
52/*
53 * Check if the CPU has an external FPU.
54 */
55static inline int __cpu_has_fpu(void)
56{
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58}
59
60static inline unsigned long cpu_get_msa_id(void)
61{
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71}
72
9b26616c
MR		 73/*
74 * Determine the FCSR mask for FPU hardware.
75 */
76static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77{
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
90b712dd 80 fcsr = c->fpu_csr31;
9b26616c
MR		 81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
9b26616c
MR		 86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99}
100
93adeaf6
MR		 101/*
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
104 */
105static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
106{
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
111
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
114
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
118
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
122
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
126
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
128
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
133
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
138
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
145 }
146
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
150 }
151}
152
153/*
503943e0
MR		 154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
156 */
157static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
158
159/*
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
93adeaf6
MR		 164 */
165static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
166{
503943e0 167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
93adeaf6 168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
503943e0
MR		 169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
180 }
181 break;
182 case LEGACY:
93adeaf6
MR		 183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
503943e0
MR		 185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
93adeaf6
MR		 194 }
195}
196
503943e0
MR		 197/*
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
200 */
201static void cpu_set_nan_2008(struct cpuinfo_mips *c)
202{
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
220 }
221}
222
223/*
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
226 *
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
231 */
232static int __init ieee754_setup(char *s)
233{
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
246
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
250
251 return 0;
252}
253
254early_param("ieee754", ieee754_setup);
255
f6843626
MR		 256/*
257 * Set the FIR feature flags for the FPU emulator.
258 */
259static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
260{
261 u32 value;
262
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
90d53a91
MR		 271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
f6843626
MR		 273 c->fpu_id = value;
274}
275
9b26616c
MR		 276/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277static unsigned int mips_nofpu_msk31;
278
7aecd5ca
MR		 279/*
280 * Set options for FPU hardware.
281 */
282static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
283{
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
286
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_FREP)
293 c->options |= MIPS_CPU_FRE;
294 }
295
296 cpu_set_fpu_fcsr_mask(c);
93adeaf6 297 cpu_set_fpu_2008(c);
503943e0 298 cpu_set_nan_2008(c);
7aecd5ca
MR		 299}
300
301/*
302 * Set options for the FPU emulator.
303 */
304static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
305{
306 c->options &= ~MIPS_CPU_FPU;
307 c->fpu_msk31 = mips_nofpu_msk31;
308
93adeaf6 309 cpu_set_nofpu_2008(c);
503943e0 310 cpu_set_nan_2008(c);
7aecd5ca
MR		 311 cpu_set_nofpu_id(c);
312}
313
078a55fc 314static int mips_fpu_disabled;
0103d23f
KC		 315
316static int __init fpu_disable(char *s)
317{
7aecd5ca 318 cpu_set_nofpu_opts(&boot_cpu_data);
0103d23f
KC		 319 mips_fpu_disabled = 1;
320
321 return 1;
322}
323
324__setup("nofpu", fpu_disable);
325
078a55fc 326int mips_dsp_disabled;
0103d23f
KC		 327
328static int __init dsp_disable(char *s)
329{
ee80f7c7 330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 331 mips_dsp_disabled = 1;
332
333 return 1;
334}
335
336__setup("nodsp", dsp_disable);
337
3d528b32
MC		 338static int mips_htw_disabled;
339
340static int __init htw_disable(char *s)
341{
342 mips_htw_disabled = 1;
343 cpu_data[0].options &= ~MIPS_CPU_HTW;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
346
347 return 1;
348}
349
350__setup("nohtw", htw_disable);
351
97f4ad29
MC		 352static int mips_ftlb_disabled;
353static int mips_has_ftlb_configured;
354
912708c2 355static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
97f4ad29
MC		 356
357static int __init ftlb_disable(char *s)
358{
359 unsigned int config4, mmuextdef;
360
361 /*
362 * If the core hasn't done any FTLB configuration, there is nothing
363 * for us to do here.
364 */
365 if (!mips_has_ftlb_configured)
366 return 1;
367
368 /* Disable it in the boot cpu */
912708c2
MC		 369 if (set_ftlb_enable(&cpu_data[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
371 return 1;
372 }
97f4ad29
MC		 373
374 back_to_back_c0_hazard();
375
376 config4 = read_c0_config4();
377
378 /* Check that FTLB has been disabled */
379 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
384 return 1;
385 }
386
387 mips_ftlb_disabled = 1;
388 mips_has_ftlb_configured = 0;
389
390 /*
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
393 */
394 pr_info("FTLB has been disabled\n");
395
396 /*
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
400 */
401 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
402 cpu_data[0].tlbsizeftlbsets;
403 cpu_data[0].tlbsizeftlbsets = 0;
404 cpu_data[0].tlbsizeftlbways = 0;
405
406 return 1;
407}
408
409__setup("noftlb", ftlb_disable);
410
411
9267a30d
MSJ		 412static inline void check_errata(void)
413{
414 struct cpuinfo_mips *c = &current_cpu_data;
415
69f24d17 416 switch (current_cpu_type()) {
9267a30d
MSJ		 417 case CPU_34K:
418 /*
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 420 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 421 * making use of VPE1 will be responsable for that VPE.
422 */
423 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
425 break;
426 default:
427 break;
428 }
429}
430
1da177e4
LT		 431void __init check_bugs32(void)
432{
9267a30d 433 check_errata();
1da177e4
LT		 434}
435
436/*
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
440 */
441static inline int cpu_has_confreg(void)
442{
443#ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1, size2;
446 unsigned long cfg = read_c0_conf();
447
448 size1 = r3k_cache_size(ST0_ISC);
449 write_c0_conf(cfg ^ R30XX_CONF_AC);
450 size2 = r3k_cache_size(ST0_ISC);
451 write_c0_conf(cfg);
452 return size1 != size2;
453#else
454 return 0;
455#endif
456}
457
c094c99e
RM		 458static inline void set_elf_platform(int cpu, const char *plat)
459{
460 if (cpu == 0)
461 __elf_platform = plat;
462}
463
91dfc423
GR		 464static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
465{
466#ifdef __NEED_VMBITS_PROBE
5b7efa89 467 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 468 back_to_back_c0_hazard();
5b7efa89 469 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 470#endif
471}
472
078a55fc 473static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 474{
475 switch (isa) {
476 case MIPS_CPU_ISA_M64R2:
477 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
478 case MIPS_CPU_ISA_M64R1:
479 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
480 case MIPS_CPU_ISA_V:
481 c->isa_level |= MIPS_CPU_ISA_V;
482 case MIPS_CPU_ISA_IV:
483 c->isa_level |= MIPS_CPU_ISA_IV;
484 case MIPS_CPU_ISA_III:
1990e542 485 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 486 break;
487
8b8aa636
LY		 488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6:
490 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
491 case MIPS_CPU_ISA_M32R6:
492 c->isa_level |= MIPS_CPU_ISA_M32R6;
493 /* Break here so we don't add incompatible ISAs */
494 break;
a96102be
SH		 495 case MIPS_CPU_ISA_M32R2:
496 c->isa_level |= MIPS_CPU_ISA_M32R2;
497 case MIPS_CPU_ISA_M32R1:
498 c->isa_level |= MIPS_CPU_ISA_M32R1;
499 case MIPS_CPU_ISA_II:
500 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 501 break;
502 }
503}
504
078a55fc 505static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 506 "Unsupported ISA type, c0.config0: %d.";
507
cf0a8aa0
MC		 508static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
509{
510
511 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
512
513 /*
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
519 *
520 * Use the linear midpoint as the probability threshold.
521 */
522 if (probability >= 12)
523 return 1;
524 else if (probability >= 6)
525 return 2;
526 else
527 /*
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
530 */
531 return 3;
532}
533
912708c2 534static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
75b5b5e0 535{
20a7f7e5 536 unsigned int config;
d83b0e82
JH		 537
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c->cputype) {
540 case CPU_PROAPTIV:
541 case CPU_P5600:
1091bfa2 542 case CPU_P6600:
d83b0e82 543 /* proAptiv & related cores use Config6 to enable the FTLB */
20a7f7e5 544 config = read_c0_config6();
cf0a8aa0 545 /* Clear the old probability value */
20a7f7e5 546 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
75b5b5e0
LY		 547 if (enable)
548 /* Enable FTLB */
20a7f7e5 549 write_c0_config6(config |
cf0a8aa0
MC		 550 (calculate_ftlb_probability(c)
551 << MIPS_CONF6_FTLBP_SHIFT)
552 | MIPS_CONF6_FTLBEN);
75b5b5e0
LY		 553 else
554 /* Disable FTLB */
20a7f7e5
MC		 555 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
556 break;
557 case CPU_I6400:
558 /* I6400 & related cores use Config7 to configure FTLB */
559 config = read_c0_config7();
560 /* Clear the old probability value */
561 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
562 write_c0_config7(config | (calculate_ftlb_probability(c)
563 << MIPS_CONF7_FTLBP_SHIFT));
d83b0e82 564 break;
b2edcfc8 565 case CPU_LOONGSON3:
06e4814e
HC		 566 /* Flush ITLB, DTLB, VTLB and FTLB */
567 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
568 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
b2edcfc8
HC		 569 /* Loongson-3 cores use Config6 to enable the FTLB */
570 config = read_c0_config6();
571 if (enable)
572 /* Enable FTLB */
573 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
574 else
575 /* Disable FTLB */
576 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
577 break;
912708c2
MC		 578 default:
579 return 1;
75b5b5e0 580 }
912708c2
MC		 581
582 return 0;
75b5b5e0
LY		 583}
584
2fa36399
KC		 585static inline unsigned int decode_config0(struct cpuinfo_mips *c)
586{
587 unsigned int config0;
2f6f3136 588 int isa, mt;
2fa36399
KC		 589
590 config0 = read_c0_config();
591
75b5b5e0
LY		 592 /*
593 * Look for Standard TLB or Dual VTLB and FTLB
594 */
2f6f3136
JH		 595 mt = config0 & MIPS_CONF_MT;
596 if (mt == MIPS_CONF_MT_TLB)
2fa36399 597 c->options |= MIPS_CPU_TLB;
2f6f3136
JH		 598 else if (mt == MIPS_CONF_MT_FTLB)
599 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
75b5b5e0 600
2fa36399
KC		 601 isa = (config0 & MIPS_CONF_AT) >> 13;
602 switch (isa) {
603 case 0:
604 switch ((config0 & MIPS_CONF_AR) >> 10) {
605 case 0:
a96102be 606 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 607 break;
608 case 1:
a96102be 609 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 610 break;
8b8aa636
LY		 611 case 2:
612 set_isa(c, MIPS_CPU_ISA_M32R6);
613 break;
2fa36399
KC		 614 default:
615 goto unknown;
616 }
617 break;
618 case 2:
619 switch ((config0 & MIPS_CONF_AR) >> 10) {
620 case 0:
a96102be 621 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 622 break;
623 case 1:
a96102be 624 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 625 break;
8b8aa636
LY		 626 case 2:
627 set_isa(c, MIPS_CPU_ISA_M64R6);
628 break;
2fa36399
KC		 629 default:
630 goto unknown;
631 }
632 break;
633 default:
634 goto unknown;
635 }
636
637 return config0 & MIPS_CONF_M;
638
639unknown:
640 panic(unknown_isa, config0);
641}
642
643static inline unsigned int decode_config1(struct cpuinfo_mips *c)
644{
645 unsigned int config1;
646
647 config1 = read_c0_config1();
648
649 if (config1 & MIPS_CONF1_MD)
650 c->ases |= MIPS_ASE_MDMX;
651 if (config1 & MIPS_CONF1_WR)
652 c->options |= MIPS_CPU_WATCH;
653 if (config1 & MIPS_CONF1_CA)
654 c->ases |= MIPS_ASE_MIPS16;
655 if (config1 & MIPS_CONF1_EP)
656 c->options |= MIPS_CPU_EJTAG;
657 if (config1 & MIPS_CONF1_FP) {
658 c->options |= MIPS_CPU_FPU;
659 c->options |= MIPS_CPU_32FPR;
660 }
75b5b5e0 661 if (cpu_has_tlb) {
2fa36399 662 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 663 c->tlbsizevtlb = c->tlbsize;
664 c->tlbsizeftlbsets = 0;
665 }
2fa36399
KC		 666
667 return config1 & MIPS_CONF_M;
668}
669
670static inline unsigned int decode_config2(struct cpuinfo_mips *c)
671{
672 unsigned int config2;
673
674 config2 = read_c0_config2();
675
676 if (config2 & MIPS_CONF2_SL)
677 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
678
679 return config2 & MIPS_CONF_M;
680}
681
682static inline unsigned int decode_config3(struct cpuinfo_mips *c)
683{
684 unsigned int config3;
685
686 config3 = read_c0_config3();
687
b2ab4f08 688 if (config3 & MIPS_CONF3_SM) {
2fa36399 689 c->ases |= MIPS_ASE_SMARTMIPS;
f18bdfa1 690 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
b2ab4f08
SH		 691 }
692 if (config3 & MIPS_CONF3_RXI)
693 c->options |= MIPS_CPU_RIXI;
f18bdfa1
JH		 694 if (config3 & MIPS_CONF3_CTXTC)
695 c->options |= MIPS_CPU_CTXTC;
2fa36399
KC		 696 if (config3 & MIPS_CONF3_DSP)
697 c->ases |= MIPS_ASE_DSP;
b5a6455c 698 if (config3 & MIPS_CONF3_DSP2P) {
ee80f7c7 699 c->ases |= MIPS_ASE_DSP2P;
b5a6455c
ZLK		 700 if (cpu_has_mips_r6)
701 c->ases |= MIPS_ASE_DSP3;
702 }
2fa36399
KC		 703 if (config3 & MIPS_CONF3_VINT)
704 c->options |= MIPS_CPU_VINT;
705 if (config3 & MIPS_CONF3_VEIC)
706 c->options |= MIPS_CPU_VEIC;
12822570
JH		 707 if (config3 & MIPS_CONF3_LPA)
708 c->options |= MIPS_CPU_LPA;
2fa36399
KC		 709 if (config3 & MIPS_CONF3_MT)
710 c->ases |= MIPS_ASE_MIPSMT;
711 if (config3 & MIPS_CONF3_ULRI)
712 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 713 if (config3 & MIPS_CONF3_ISA)
714 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 715 if (config3 & MIPS_CONF3_VZ)
716 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 717 if (config3 & MIPS_CONF3_SC)
718 c->options |= MIPS_CPU_SEGMENTS;
e06a1548
JH		 719 if (config3 & MIPS_CONF3_BI)
720 c->options |= MIPS_CPU_BADINSTR;
721 if (config3 & MIPS_CONF3_BP)
722 c->options |= MIPS_CPU_BADINSTRP;
a5e9a69e
PB		 723 if (config3 & MIPS_CONF3_MSA)
724 c->ases |= MIPS_ASE_MSA;
cab25bc7 725 if (config3 & MIPS_CONF3_PW) {
ed4cbc81 726 c->htw_seq = 0;
3d528b32 727 c->options |= MIPS_CPU_HTW;
ed4cbc81 728 }
9b3274bd
JH		 729 if (config3 & MIPS_CONF3_CDMM)
730 c->options |= MIPS_CPU_CDMM;
aaa7be48
JH		 731 if (config3 & MIPS_CONF3_SP)
732 c->options |= MIPS_CPU_SP;
2fa36399
KC		 733
734 return config3 & MIPS_CONF_M;
735}
736
737static inline unsigned int decode_config4(struct cpuinfo_mips *c)
738{
739 unsigned int config4;
75b5b5e0
LY		 740 unsigned int newcf4;
741 unsigned int mmuextdef;
742 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2db003a5 743 unsigned long asid_mask;
2fa36399
KC		 744
745 config4 = read_c0_config4();
746
1745c1ef
LY		 747 if (cpu_has_tlb) {
748 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
749 c->options |= MIPS_CPU_TLBINV;
43d104db 750
e87569cd 751 /*
43d104db
JH		 752 * R6 has dropped the MMUExtDef field from config4.
753 * On R6 the fields always describe the FTLB, and only if it is
754 * present according to Config.MT.
e87569cd 755 */
43d104db
JH		 756 if (!cpu_has_mips_r6)
757 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
758 else if (cpu_has_ftlb)
e87569cd
MC		 759 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
760 else
43d104db 761 mmuextdef = 0;
e87569cd 762
75b5b5e0
LY		 763 switch (mmuextdef) {
764 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
765 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
766 c->tlbsizevtlb = c->tlbsize;
767 break;
768 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
769 c->tlbsizevtlb +=
770 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
771 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
772 c->tlbsize = c->tlbsizevtlb;
773 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
774 /* fall through */
775 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 776 if (mips_ftlb_disabled)
777 break;
75b5b5e0
LY		 778 newcf4 = (config4 & ~ftlb_page) |
779 (page_size_ftlb(mmuextdef) <<
780 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
781 write_c0_config4(newcf4);
782 back_to_back_c0_hazard();
783 config4 = read_c0_config4();
784 if (config4 != newcf4) {
785 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
786 PAGE_SIZE, config4);
787 /* Switch FTLB off */
788 set_ftlb_enable(c, 0);
789 break;
790 }
791 c->tlbsizeftlbsets = 1 <<
792 ((config4 & MIPS_CONF4_FTLBSETS) >>
793 MIPS_CONF4_FTLBSETS_SHIFT);
794 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
795 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
796 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 797 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 798 break;
799 }
1745c1ef
LY		 800 }
801
2fa36399
KC		 802 c->kscratch_mask = (config4 >> 16) & 0xff;
803
2db003a5
PB		 804 asid_mask = MIPS_ENTRYHI_ASID;
805 if (config4 & MIPS_CONF4_AE)
806 asid_mask |= MIPS_ENTRYHI_ASIDX;
807 set_cpu_asid_mask(c, asid_mask);
808
809 /*
810 * Warn if the computed ASID mask doesn't match the mask the kernel
811 * is built for. This may indicate either a serious problem or an
812 * easy optimisation opportunity, but either way should be addressed.
813 */
814 WARN_ON(asid_mask != cpu_asid_mask(c));
815
2fa36399
KC		 816 return config4 & MIPS_CONF_M;
817}
818
8b8a7634
RB		 819static inline unsigned int decode_config5(struct cpuinfo_mips *c)
820{
821 unsigned int config5;
822
823 config5 = read_c0_config5();
d175ed2b 824 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 825 write_c0_config5(config5);
826
49016748
MC		 827 if (config5 & MIPS_CONF5_EVA)
828 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 829 if (config5 & MIPS_CONF5_MRP)
830 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 831 if (config5 & MIPS_CONF5_LLB)
832 c->options |= MIPS_CPU_RW_LLB;
c5b36783
SH		 833#ifdef CONFIG_XPA
834 if (config5 & MIPS_CONF5_MVH)
835 c->options |= MIPS_CPU_XPA;
836#endif
f270d881
PB		 837 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
838 c->options |= MIPS_CPU_VP;
49016748 839
8b8a7634
RB		 840 return config5 & MIPS_CONF_M;
841}
842
078a55fc 843static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 844{
845 int ok;
846
847 /* MIPS32 or MIPS64 compliant CPU. */
848 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
849 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
850
851 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
852
97f4ad29
MC		 853 /* Enable FTLB if present and not disabled */
854 set_ftlb_enable(c, !mips_ftlb_disabled);
75b5b5e0 855
2fa36399 856 ok = decode_config0(c); /* Read Config registers. */
70342287 857 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 858 if (ok)
859 ok = decode_config1(c);
860 if (ok)
861 ok = decode_config2(c);
862 if (ok)
863 ok = decode_config3(c);
864 if (ok)
865 ok = decode_config4(c);
8b8a7634
RB		 866 if (ok)
867 ok = decode_config5(c);
2fa36399 868
37fb60f8
JH		 869 /* Probe the EBase.WG bit */
870 if (cpu_has_mips_r2_r6) {
871 u64 ebase;
872 unsigned int status;
873
874 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
875 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
876 : (s32)read_c0_ebase();
877 if (ebase & MIPS_EBASE_WG) {
878 /* WG bit already set, we can avoid the clumsy probe */
879 c->options |= MIPS_CPU_EBASE_WG;
880 } else {
881 /* Its UNDEFINED to change EBase while BEV=0 */
882 status = read_c0_status();
883 write_c0_status(status | ST0_BEV);
884 irq_enable_hazard();
885 /*
886 * On pre-r6 cores, this may well clobber the upper bits
887 * of EBase. This is hard to avoid without potentially
888 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
889 */
890 if (cpu_has_mips64r6)
891 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
892 else
893 write_c0_ebase(ebase | MIPS_EBASE_WG);
894 back_to_back_c0_hazard();
895 /* Restore BEV */
896 write_c0_status(status);
897 if (read_c0_ebase() & MIPS_EBASE_WG) {
898 c->options |= MIPS_CPU_EBASE_WG;
899 write_c0_ebase(ebase);
900 }
901 }
902 }
903
2fa36399
KC		 904 mips_probe_watch_registers(c);
905
0ee958e1 906#ifndef CONFIG_MIPS_CPS
8b8aa636 907 if (cpu_has_mips_r2_r6) {
45b585c8 908 c->core = get_ebase_cpunum();
30ee615b
PB		 909 if (cpu_has_mipsmt)
910 c->core >>= fls(core_nvpes()) - 1;
911 }
0ee958e1 912#endif
2fa36399
KC		 913}
914
02cf2119 915#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 916 | MIPS_CPU_COUNTER)
917
cea7e2df 918static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 919{
8ff374b9 920 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 921 case PRID_IMP_R2000:
922 c->cputype = CPU_R2000;
cea7e2df 923 __cpu_name[cpu] = "R2000";
9b26616c 924 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 925 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 926 MIPS_CPU_NOFPUEX;
1da177e4
LT		 927 if (__cpu_has_fpu())
928 c->options |= MIPS_CPU_FPU;
929 c->tlbsize = 64;
930 break;
931 case PRID_IMP_R3000:
8ff374b9 932 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 933 if (cpu_has_confreg()) {
1da177e4 934 c->cputype = CPU_R3081E;
cea7e2df
RB		 935 __cpu_name[cpu] = "R3081";
936 } else {
1da177e4 937 c->cputype = CPU_R3000A;
cea7e2df
RB		 938 __cpu_name[cpu] = "R3000A";
939 }
cea7e2df 940 } else {
1da177e4 941 c->cputype = CPU_R3000;
cea7e2df
RB		 942 __cpu_name[cpu] = "R3000";
943 }
9b26616c 944 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 945 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 946 MIPS_CPU_NOFPUEX;
1da177e4
LT		 947 if (__cpu_has_fpu())
948 c->options |= MIPS_CPU_FPU;
949 c->tlbsize = 64;
950 break;
951 case PRID_IMP_R4000:
952 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 953 if ((c->processor_id & PRID_REV_MASK) >=
954 PRID_REV_R4400) {
1da177e4 955 c->cputype = CPU_R4400PC;
cea7e2df
RB		 956 __cpu_name[cpu] = "R4400PC";
957 } else {
1da177e4 958 c->cputype = CPU_R4000PC;
cea7e2df
RB		 959 __cpu_name[cpu] = "R4000PC";
960 }
1da177e4 961 } else {
7f177a52
MR		 962 int cca = read_c0_config() & CONF_CM_CMASK;
963 int mc;
964
965 /*
966 * SC and MC versions can't be reliably told apart,
967 * but only the latter support coherent caching
968 * modes so assume the firmware has set the KSEG0
969 * coherency attribute reasonably (if uncached, we
970 * assume SC).
971 */
972 switch (cca) {
973 case CONF_CM_CACHABLE_CE:
974 case CONF_CM_CACHABLE_COW:
975 case CONF_CM_CACHABLE_CUW:
976 mc = 1;
977 break;
978 default:
979 mc = 0;
980 break;
981 }
8ff374b9
MR		 982 if ((c->processor_id & PRID_REV_MASK) >=
983 PRID_REV_R4400) {
7f177a52
MR		 984 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
985 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 986 } else {
7f177a52
MR		 987 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
988 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 989 }
1da177e4
LT		 990 }
991
a96102be 992 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 993 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 994 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 995 MIPS_CPU_WATCH | MIPS_CPU_VCE |
996 MIPS_CPU_LLSC;
1da177e4
LT		 997 c->tlbsize = 48;
998 break;
999 case PRID_IMP_VR41XX:
9f91e506 1000 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1001 c->fpu_msk31 |= FPU_CSR_CONDX;
9f91e506
YY		 1002 c->options = R4K_OPTS;
1003 c->tlbsize = 32;
1da177e4 1004 switch (c->processor_id & 0xf0) {
1da177e4
LT		 1005 case PRID_REV_VR4111:
1006 c->cputype = CPU_VR4111;
cea7e2df 1007 __cpu_name[cpu] = "NEC VR4111";
1da177e4 1008 break;
1da177e4
LT		 1009 case PRID_REV_VR4121:
1010 c->cputype = CPU_VR4121;
cea7e2df 1011 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 1012 break;
1013 case PRID_REV_VR4122:
cea7e2df 1014 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 1015 c->cputype = CPU_VR4122;
cea7e2df
RB		 1016 __cpu_name[cpu] = "NEC VR4122";
1017 } else {
1da177e4 1018 c->cputype = CPU_VR4181A;
cea7e2df
RB		 1019 __cpu_name[cpu] = "NEC VR4181A";
1020 }
1da177e4
LT		 1021 break;
1022 case PRID_REV_VR4130:
cea7e2df 1023 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 1024 c->cputype = CPU_VR4131;
cea7e2df
RB		 1025 __cpu_name[cpu] = "NEC VR4131";
1026 } else {
1da177e4 1027 c->cputype = CPU_VR4133;
9f91e506 1028 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 1029 __cpu_name[cpu] = "NEC VR4133";
1030 }
1da177e4
LT		 1031 break;
1032 default:
1033 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1034 c->cputype = CPU_VR41XX;
cea7e2df 1035 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 1036 break;
1037 }
1da177e4
LT		 1038 break;
1039 case PRID_IMP_R4300:
1040 c->cputype = CPU_R4300;
cea7e2df 1041 __cpu_name[cpu] = "R4300";
a96102be 1042 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1043 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1044 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1045 MIPS_CPU_LLSC;
1da177e4
LT		 1046 c->tlbsize = 32;
1047 break;
1048 case PRID_IMP_R4600:
1049 c->cputype = CPU_R4600;
cea7e2df 1050 __cpu_name[cpu] = "R4600";
a96102be 1051 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1052 c->fpu_msk31 |= FPU_CSR_CONDX;
075e7502
TS		 1053 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1054 MIPS_CPU_LLSC;
1da177e4
LT		 1055 c->tlbsize = 48;
1056 break;
1057 #if 0
03751e79 1058 case PRID_IMP_R4650:
1da177e4
LT		 1059 /*
1060 * This processor doesn't have an MMU, so it's not
1061 * "real easy" to run Linux on it. It is left purely
1062 * for documentation. Commented out because it shares
1063 * it's c0_prid id number with the TX3900.
1064 */
a3dddd56 1065 c->cputype = CPU_R4650;
cea7e2df 1066 __cpu_name[cpu] = "R4650";
a96102be 1067 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1068 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1069 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 1070 c->tlbsize = 48;
1da177e4
LT		 1071 break;
1072 #endif
1073 case PRID_IMP_TX39:
9b26616c 1074 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1075 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 1076
1077 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1078 c->cputype = CPU_TX3927;
cea7e2df 1079 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 1080 c->tlbsize = 64;
1081 } else {
8ff374b9 1082 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 1083 case PRID_REV_TX3912:
1084 c->cputype = CPU_TX3912;
cea7e2df 1085 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 1086 c->tlbsize = 32;
1087 break;
1088 case PRID_REV_TX3922:
1089 c->cputype = CPU_TX3922;
cea7e2df 1090 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 1091 c->tlbsize = 64;
1092 break;
1da177e4
LT		 1093 }
1094 }
1095 break;
1096 case PRID_IMP_R4700:
1097 c->cputype = CPU_R4700;
cea7e2df 1098 __cpu_name[cpu] = "R4700";
a96102be 1099 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1100 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1101 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1102 MIPS_CPU_LLSC;
1da177e4
LT		 1103 c->tlbsize = 48;
1104 break;
1105 case PRID_IMP_TX49:
1106 c->cputype = CPU_TX49XX;
cea7e2df 1107 __cpu_name[cpu] = "R49XX";
a96102be 1108 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1109 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4
LT		 1110 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1111 if (!(c->processor_id & 0x08))
1112 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1113 c->tlbsize = 48;
1114 break;
1115 case PRID_IMP_R5000:
1116 c->cputype = CPU_R5000;
cea7e2df 1117 __cpu_name[cpu] = "R5000";
a96102be 1118 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1119 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1120 MIPS_CPU_LLSC;
1da177e4
LT		 1121 c->tlbsize = 48;
1122 break;
1123 case PRID_IMP_R5432:
1124 c->cputype = CPU_R5432;
cea7e2df 1125 __cpu_name[cpu] = "R5432";
a96102be 1126 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1127 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1128 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1129 c->tlbsize = 48;
1130 break;
1131 case PRID_IMP_R5500:
1132 c->cputype = CPU_R5500;
cea7e2df 1133 __cpu_name[cpu] = "R5500";
a96102be 1134 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1135 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1136 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1137 c->tlbsize = 48;
1138 break;
1139 case PRID_IMP_NEVADA:
1140 c->cputype = CPU_NEVADA;
cea7e2df 1141 __cpu_name[cpu] = "Nevada";
a96102be 1142 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1143 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1144 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 1145 c->tlbsize = 48;
1146 break;
1147 case PRID_IMP_R6000:
1148 c->cputype = CPU_R6000;
cea7e2df 1149 __cpu_name[cpu] = "R6000";
a96102be 1150 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1151 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1152 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1153 MIPS_CPU_LLSC;
1da177e4
LT		 1154 c->tlbsize = 32;
1155 break;
1156 case PRID_IMP_R6000A:
1157 c->cputype = CPU_R6000A;
cea7e2df 1158 __cpu_name[cpu] = "R6000A";
a96102be 1159 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1160 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1161 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1162 MIPS_CPU_LLSC;
1da177e4
LT		 1163 c->tlbsize = 32;
1164 break;
1165 case PRID_IMP_RM7000:
1166 c->cputype = CPU_RM7000;
cea7e2df 1167 __cpu_name[cpu] = "RM7000";
a96102be 1168 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1169 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1170 MIPS_CPU_LLSC;
1da177e4 1171 /*
70342287 1172 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 1173 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1174 * entries.
1175 *
70342287
RB		 1176 * 29 1 => 64 entry JTLB
1177 * 0 => 48 entry JTLB
1da177e4
LT		 1178 */
1179 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 1180 break;
1181 case PRID_IMP_R8000:
1182 c->cputype = CPU_R8000;
cea7e2df 1183 __cpu_name[cpu] = "RM8000";
a96102be 1184 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1185 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 1186 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1187 MIPS_CPU_LLSC;
1da177e4
LT		 1188 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1189 break;
1190 case PRID_IMP_R10000:
1191 c->cputype = CPU_R10000;
cea7e2df 1192 __cpu_name[cpu] = "R10000";
a96102be 1193 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1194 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1195 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1196 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 1197 MIPS_CPU_LLSC;
1da177e4
LT		 1198 c->tlbsize = 64;
1199 break;
1200 case PRID_IMP_R12000:
1201 c->cputype = CPU_R12000;
cea7e2df 1202 __cpu_name[cpu] = "R12000";
a96102be 1203 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1204 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1205 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1206 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1207 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1da177e4
LT		 1208 c->tlbsize = 64;
1209 break;
44d921b2 1210 case PRID_IMP_R14000:
30577391
JK		 1211 if (((c->processor_id >> 4) & 0x0f) > 2) {
1212 c->cputype = CPU_R16000;
1213 __cpu_name[cpu] = "R16000";
1214 } else {
1215 c->cputype = CPU_R14000;
1216 __cpu_name[cpu] = "R14000";
1217 }
a96102be 1218 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 1219 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1220 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 1221 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1222 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
44d921b2
K		 1223 c->tlbsize = 64;
1224 break;
26859198 1225 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 1226 switch (c->processor_id & PRID_REV_MASK) {
1227 case PRID_REV_LOONGSON2E:
c579d310
HC		 1228 c->cputype = CPU_LOONGSON2;
1229 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1230 set_elf_platform(cpu, "loongson2e");
7352c8b1 1231 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1232 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a
RM		 1233 break;
1234 case PRID_REV_LOONGSON2F:
c579d310
HC		 1235 c->cputype = CPU_LOONGSON2;
1236 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1237 set_elf_platform(cpu, "loongson2f");
7352c8b1 1238 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1239 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a 1240 break;
b2edcfc8 1241 case PRID_REV_LOONGSON3A_R1:
c579d310
HC		 1242 c->cputype = CPU_LOONGSON3;
1243 __cpu_name[cpu] = "ICT Loongson-3";
1244 set_elf_platform(cpu, "loongson3a");
7352c8b1 1245 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 1246 break;
e7841be5
HC		 1247 case PRID_REV_LOONGSON3B_R1:
1248 case PRID_REV_LOONGSON3B_R2:
1249 c->cputype = CPU_LOONGSON3;
1250 __cpu_name[cpu] = "ICT Loongson-3";
1251 set_elf_platform(cpu, "loongson3b");
7352c8b1 1252 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 1253 break;
5aac1e8a
RM		 1254 }
1255
2a21c730
FZ		 1256 c->options = R4K_OPTS |
1257 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1258 MIPS_CPU_32FPR;
1259 c->tlbsize = 64;
cc94ea31 1260 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 1261 break;
26859198 1262 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 1263 decode_configs(c);
b4672d37 1264
2fa36399 1265 c->cputype = CPU_LOONGSON1;
1da177e4 1266
2fa36399
KC		 1267 switch (c->processor_id & PRID_REV_MASK) {
1268 case PRID_REV_LOONGSON1B:
1269 __cpu_name[cpu] = "Loongson 1B";
b4672d37 1270 break;
b4672d37 1271 }
4194318c 1272
2fa36399 1273 break;
1da177e4 1274 }
1da177e4
LT		 1275}
1276
cea7e2df 1277static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1278{
4f12b91d 1279 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1280 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 1281 case PRID_IMP_QEMU_GENERIC:
1282 c->writecombine = _CACHE_UNCACHED;
1283 c->cputype = CPU_QEMU_GENERIC;
1284 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1285 break;
1da177e4
LT		 1286 case PRID_IMP_4KC:
1287 c->cputype = CPU_4KC;
4f12b91d 1288 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1289 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 1290 break;
1291 case PRID_IMP_4KEC:
2b07bd02
RB		 1292 case PRID_IMP_4KECR2:
1293 c->cputype = CPU_4KEC;
4f12b91d 1294 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1295 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 1296 break;
1da177e4 1297 case PRID_IMP_4KSC:
8afcb5d8 1298 case PRID_IMP_4KSD:
1da177e4 1299 c->cputype = CPU_4KSC;
4f12b91d 1300 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1301 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 1302 break;
1303 case PRID_IMP_5KC:
1304 c->cputype = CPU_5KC;
4f12b91d 1305 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1306 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 1307 break;
78d4803f
LY		 1308 case PRID_IMP_5KE:
1309 c->cputype = CPU_5KE;
4f12b91d 1310 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 1311 __cpu_name[cpu] = "MIPS 5KE";
1312 break;
1da177e4
LT		 1313 case PRID_IMP_20KC:
1314 c->cputype = CPU_20KC;
4f12b91d 1315 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1316 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 1317 break;
1318 case PRID_IMP_24K:
1319 c->cputype = CPU_24K;
4f12b91d 1320 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1321 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 1322 break;
42f3caef
JC		 1323 case PRID_IMP_24KE:
1324 c->cputype = CPU_24K;
4f12b91d 1325 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 1326 __cpu_name[cpu] = "MIPS 24KEc";
1327 break;
1da177e4
LT		 1328 case PRID_IMP_25KF:
1329 c->cputype = CPU_25KF;
4f12b91d 1330 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1331 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 1332 break;
bbc7f22f
RB		 1333 case PRID_IMP_34K:
1334 c->cputype = CPU_34K;
4f12b91d 1335 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1336 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 1337 break;
c620953c
CD		 1338 case PRID_IMP_74K:
1339 c->cputype = CPU_74K;
4f12b91d 1340 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1341 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 1342 break;
113c62d9
SH		 1343 case PRID_IMP_M14KC:
1344 c->cputype = CPU_M14KC;
4f12b91d 1345 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 1346 __cpu_name[cpu] = "MIPS M14Kc";
1347 break;
f8fa4811
SH		 1348 case PRID_IMP_M14KEC:
1349 c->cputype = CPU_M14KEC;
4f12b91d 1350 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 1351 __cpu_name[cpu] = "MIPS M14KEc";
1352 break;
39b8d525
RB		 1353 case PRID_IMP_1004K:
1354 c->cputype = CPU_1004K;
4f12b91d 1355 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1356 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 1357 break;
006a851b 1358 case PRID_IMP_1074K:
442e14a2 1359 c->cputype = CPU_1074K;
4f12b91d 1360 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 1361 __cpu_name[cpu] = "MIPS 1074Kc";
1362 break;
b5f065e7
LY		 1363 case PRID_IMP_INTERAPTIV_UP:
1364 c->cputype = CPU_INTERAPTIV;
1365 __cpu_name[cpu] = "MIPS interAptiv";
1366 break;
1367 case PRID_IMP_INTERAPTIV_MP:
1368 c->cputype = CPU_INTERAPTIV;
1369 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1370 break;
b0d4d300
LY		 1371 case PRID_IMP_PROAPTIV_UP:
1372 c->cputype = CPU_PROAPTIV;
1373 __cpu_name[cpu] = "MIPS proAptiv";
1374 break;
1375 case PRID_IMP_PROAPTIV_MP:
1376 c->cputype = CPU_PROAPTIV;
1377 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1378 break;
829dcc0a
JH		 1379 case PRID_IMP_P5600:
1380 c->cputype = CPU_P5600;
1381 __cpu_name[cpu] = "MIPS P5600";
1382 break;
eba20a3a
PB		 1383 case PRID_IMP_P6600:
1384 c->cputype = CPU_P6600;
1385 __cpu_name[cpu] = "MIPS P6600";
1386 break;
e57f9a2d
MC		 1387 case PRID_IMP_I6400:
1388 c->cputype = CPU_I6400;
1389 __cpu_name[cpu] = "MIPS I6400";
1390 break;
9943ed92
LY		 1391 case PRID_IMP_M5150:
1392 c->cputype = CPU_M5150;
1393 __cpu_name[cpu] = "MIPS M5150";
1394 break;
43aff742
PB		 1395 case PRID_IMP_M6250:
1396 c->cputype = CPU_M6250;
1397 __cpu_name[cpu] = "MIPS M6250";
1398 break;
1da177e4 1399 }
0b6d497f 1400
75b5b5e0
LY		 1401 decode_configs(c);
1402
0b6d497f 1403 spram_config();
1da177e4
LT		 1404}
1405
cea7e2df 1406static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1407{
4194318c 1408 decode_configs(c);
8ff374b9 1409 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1410 case PRID_IMP_AU1_REV1:
1411 case PRID_IMP_AU1_REV2:
270717a8 1412 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1413 switch ((c->processor_id >> 24) & 0xff) {
1414 case 0:
cea7e2df 1415 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1416 break;
1417 case 1:
cea7e2df 1418 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1419 break;
1420 case 2:
cea7e2df 1421 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1422 break;
1423 case 3:
cea7e2df 1424 __cpu_name[cpu] = "Au1550";
1da177e4 1425 break;
e3ad1c23 1426 case 4:
cea7e2df 1427 __cpu_name[cpu] = "Au1200";
8ff374b9 1428 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1429 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1430 break;
1431 case 5:
cea7e2df 1432 __cpu_name[cpu] = "Au1210";
e3ad1c23 1433 break;
1da177e4 1434 default:
270717a8 1435 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1436 break;
1437 }
1da177e4
LT		 1438 break;
1439 }
1440}
1441
cea7e2df 1442static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1443{
4194318c 1444 decode_configs(c);
02cf2119 1445
4f12b91d 1446 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1447 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1448 case PRID_IMP_SB1:
1449 c->cputype = CPU_SB1;
cea7e2df 1450 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1451 /* FPU in pass1 is known to have issues. */
8ff374b9 1452 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1453 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1454 break;
93ce2f52
AI		 1455 case PRID_IMP_SB1A:
1456 c->cputype = CPU_SB1A;
cea7e2df 1457 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1458 break;
1da177e4
LT		 1459 }
1460}
1461
cea7e2df 1462static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1463{
4194318c 1464 decode_configs(c);
8ff374b9 1465 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1466 case PRID_IMP_SR71000:
1467 c->cputype = CPU_SR71000;
cea7e2df 1468 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1469 c->scache.ways = 8;
1470 c->tlbsize = 64;
1471 break;
1472 }
1473}
1474
cea7e2df 1475static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1476{
1477 decode_configs(c);
8ff374b9 1478 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1479 case PRID_IMP_PR4450:
1480 c->cputype = CPU_PR4450;
cea7e2df 1481 __cpu_name[cpu] = "Philips PR4450";
a96102be 1482 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1483 break;
bdf21b18
PP		 1484 }
1485}
1486
cea7e2df 1487static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1488{
1489 decode_configs(c);
8ff374b9 1490 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1491 case PRID_IMP_BMIPS32_REV4:
1492 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1493 c->cputype = CPU_BMIPS32;
1494 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1495 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1496 break;
1497 case PRID_IMP_BMIPS3300:
1498 case PRID_IMP_BMIPS3300_ALT:
1499 case PRID_IMP_BMIPS3300_BUG:
1500 c->cputype = CPU_BMIPS3300;
1501 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1502 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1503 break;
1504 case PRID_IMP_BMIPS43XX: {
8ff374b9 1505 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1506
1507 if (rev >= PRID_REV_BMIPS4380_LO &&
1508 rev <= PRID_REV_BMIPS4380_HI) {
1509 c->cputype = CPU_BMIPS4380;
1510 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1511 set_elf_platform(cpu, "bmips4380");
b4720809 1512 c->options |= MIPS_CPU_RIXI;
602977b0
KC		 1513 } else {
1514 c->cputype = CPU_BMIPS4350;
1515 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1516 set_elf_platform(cpu, "bmips4350");
602977b0 1517 }
0de663ef 1518 break;
602977b0
KC		 1519 }
1520 case PRID_IMP_BMIPS5000:
68e6a783 1521 case PRID_IMP_BMIPS5200:
602977b0 1522 c->cputype = CPU_BMIPS5000;
37808d62
FF		 1523 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1524 __cpu_name[cpu] = "Broadcom BMIPS5200";
1525 else
1526 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1527 set_elf_platform(cpu, "bmips5000");
b4720809 1528 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
0de663ef 1529 break;
1c0c13eb
AJ		 1530 }
1531}
1532
0dd4781b
DD		 1533static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1534{
1535 decode_configs(c);
8ff374b9 1536 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1537 case PRID_IMP_CAVIUM_CN38XX:
1538 case PRID_IMP_CAVIUM_CN31XX:
1539 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1540 c->cputype = CPU_CAVIUM_OCTEON;
1541 __cpu_name[cpu] = "Cavium Octeon";
1542 goto platform;
0dd4781b
DD		 1543 case PRID_IMP_CAVIUM_CN58XX:
1544 case PRID_IMP_CAVIUM_CN56XX:
1545 case PRID_IMP_CAVIUM_CN50XX:
1546 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1547 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1548 __cpu_name[cpu] = "Cavium Octeon+";
1549platform:
c094c99e 1550 set_elf_platform(cpu, "octeon");
0dd4781b 1551 break;
a1431b61 1552 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1553 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1554 case PRID_IMP_CAVIUM_CN66XX:
1555 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1556 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1557 c->cputype = CPU_CAVIUM_OCTEON2;
1558 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1559 set_elf_platform(cpu, "octeon2");
0e56b385 1560 break;
af04bb85 1561 case PRID_IMP_CAVIUM_CN70XX:
b8c8f665
DD		 1562 case PRID_IMP_CAVIUM_CN73XX:
1563 case PRID_IMP_CAVIUM_CNF75XX:
af04bb85
DD		 1564 case PRID_IMP_CAVIUM_CN78XX:
1565 c->cputype = CPU_CAVIUM_OCTEON3;
1566 __cpu_name[cpu] = "Cavium Octeon III";
1567 set_elf_platform(cpu, "octeon3");
1568 break;
0dd4781b
DD		 1569 default:
1570 printk(KERN_INFO "Unknown Octeon chip!\n");
1571 c->cputype = CPU_UNKNOWN;
1572 break;
1573 }
1574}
1575
b2edcfc8
HC		 1576static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1577{
1578 switch (c->processor_id & PRID_IMP_MASK) {
1579 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1580 switch (c->processor_id & PRID_REV_MASK) {
1581 case PRID_REV_LOONGSON3A_R2:
1582 c->cputype = CPU_LOONGSON3;
1583 __cpu_name[cpu] = "ICT Loongson-3";
1584 set_elf_platform(cpu, "loongson3a");
1585 set_isa(c, MIPS_CPU_ISA_M64R2);
1586 break;
1587 }
1588
1589 decode_configs(c);
380cd582 1590 c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
b2edcfc8
HC		 1591 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1592 break;
1593 default:
1594 panic("Unknown Loongson Processor ID!");
1595 break;
1596 }
1597}
1598
83ccf69d
LPC		 1599static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1600{
1601 decode_configs(c);
1602 /* JZRISC does not implement the CP0 counter. */
1603 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1604 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1605 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1606 case PRID_IMP_JZRISC:
1607 c->cputype = CPU_JZRISC;
4f12b91d 1608 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1609 __cpu_name[cpu] = "Ingenic JZRISC";
1610 break;
1611 default:
1612 panic("Unknown Ingenic Processor ID!");
1613 break;
1614 }
1615}
1616
a7117c6b
J		 1617static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1618{
1619 decode_configs(c);
1620
8ff374b9 1621 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1622 c->cputype = CPU_ALCHEMY;
1623 __cpu_name[cpu] = "Au1300";
1624 /* following stuff is not for Alchemy */
1625 return;
1626 }
1627
70342287
RB		 1628 c->options = (MIPS_CPU_TLB |
1629 MIPS_CPU_4KEX |
a7117c6b 1630 MIPS_CPU_COUNTER |
70342287
RB		 1631 MIPS_CPU_DIVEC |
1632 MIPS_CPU_WATCH |
1633 MIPS_CPU_EJTAG |
a7117c6b
J		 1634 MIPS_CPU_LLSC);
1635
8ff374b9 1636 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1637 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1638 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1639 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1640 c->cputype = CPU_XLP;
1641 __cpu_name[cpu] = "Broadcom XLPII";
1642 break;
1643
2aa54b20
J		 1644 case PRID_IMP_NETLOGIC_XLP8XX:
1645 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1646 c->cputype = CPU_XLP;
1647 __cpu_name[cpu] = "Netlogic XLP";
1648 break;
1649
a7117c6b
J		 1650 case PRID_IMP_NETLOGIC_XLR732:
1651 case PRID_IMP_NETLOGIC_XLR716:
1652 case PRID_IMP_NETLOGIC_XLR532:
1653 case PRID_IMP_NETLOGIC_XLR308:
1654 case PRID_IMP_NETLOGIC_XLR532C:
1655 case PRID_IMP_NETLOGIC_XLR516C:
1656 case PRID_IMP_NETLOGIC_XLR508C:
1657 case PRID_IMP_NETLOGIC_XLR308C:
1658 c->cputype = CPU_XLR;
1659 __cpu_name[cpu] = "Netlogic XLR";
1660 break;
1661
1662 case PRID_IMP_NETLOGIC_XLS608:
1663 case PRID_IMP_NETLOGIC_XLS408:
1664 case PRID_IMP_NETLOGIC_XLS404:
1665 case PRID_IMP_NETLOGIC_XLS208:
1666 case PRID_IMP_NETLOGIC_XLS204:
1667 case PRID_IMP_NETLOGIC_XLS108:
1668 case PRID_IMP_NETLOGIC_XLS104:
1669 case PRID_IMP_NETLOGIC_XLS616B:
1670 case PRID_IMP_NETLOGIC_XLS608B:
1671 case PRID_IMP_NETLOGIC_XLS416B:
1672 case PRID_IMP_NETLOGIC_XLS412B:
1673 case PRID_IMP_NETLOGIC_XLS408B:
1674 case PRID_IMP_NETLOGIC_XLS404B:
1675 c->cputype = CPU_XLR;
1676 __cpu_name[cpu] = "Netlogic XLS";
1677 break;
1678
1679 default:
a3d4fb2d 1680 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1681 c->processor_id);
1682 c->cputype = CPU_XLR;
1683 break;
1684 }
1685
a3d4fb2d 1686 if (c->cputype == CPU_XLP) {
a96102be 1687 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1688 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1689 /* This will be updated again after all threads are woken up */
1690 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1691 } else {
a96102be 1692 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1693 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1694 }
7777b939 1695 c->kscratch_mask = 0xf;
a7117c6b
J		 1696}
1697
949e51be
DD		 1698#ifdef CONFIG_64BIT
1699/* For use by uaccess.h */
1700u64 __ua_limit;
1701EXPORT_SYMBOL(__ua_limit);
1702#endif
1703
9966db25 1704const char *__cpu_name[NR_CPUS];
874fd3b5 1705const char *__elf_platform;
9966db25 1706
078a55fc 1707void cpu_probe(void)
1da177e4
LT		 1708{
1709 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1710 unsigned int cpu = smp_processor_id();
1da177e4 1711
70342287 1712 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1713 c->fpu_id = FPIR_IMP_NONE;
1714 c->cputype = CPU_UNKNOWN;
4f12b91d 1715 c->writecombine = _CACHE_UNCACHED;
1da177e4 1716
9b26616c
MR		 1717 c->fpu_csr31 = FPU_CSR_RN;
1718 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1719
1da177e4 1720 c->processor_id = read_c0_prid();
8ff374b9 1721 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1722 case PRID_COMP_LEGACY:
cea7e2df 1723 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1724 break;
1725 case PRID_COMP_MIPS:
cea7e2df 1726 cpu_probe_mips(c, cpu);
1da177e4
LT		 1727 break;
1728 case PRID_COMP_ALCHEMY:
cea7e2df 1729 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1730 break;
1731 case PRID_COMP_SIBYTE:
cea7e2df 1732 cpu_probe_sibyte(c, cpu);
1da177e4 1733 break;
1c0c13eb 1734 case PRID_COMP_BROADCOM:
cea7e2df 1735 cpu_probe_broadcom(c, cpu);
1c0c13eb 1736 break;
1da177e4 1737 case PRID_COMP_SANDCRAFT:
cea7e2df 1738 cpu_probe_sandcraft(c, cpu);
1da177e4 1739 break;
a92b0588 1740 case PRID_COMP_NXP:
cea7e2df 1741 cpu_probe_nxp(c, cpu);
a3dddd56 1742 break;
0dd4781b
DD		 1743 case PRID_COMP_CAVIUM:
1744 cpu_probe_cavium(c, cpu);
1745 break;
b2edcfc8
HC		 1746 case PRID_COMP_LOONGSON:
1747 cpu_probe_loongson(c, cpu);
1748 break;
252617a4
PB		 1749 case PRID_COMP_INGENIC_D0:
1750 case PRID_COMP_INGENIC_D1:
1751 case PRID_COMP_INGENIC_E1:
83ccf69d
LPC		 1752 cpu_probe_ingenic(c, cpu);
1753 break;
a7117c6b
J		 1754 case PRID_COMP_NETLOGIC:
1755 cpu_probe_netlogic(c, cpu);
1756 break;
1da177e4 1757 }
dec8b1ca 1758
cea7e2df
RB		 1759 BUG_ON(!__cpu_name[cpu]);
1760 BUG_ON(c->cputype == CPU_UNKNOWN);
1761
dec8b1ca
FBH		 1762 /*
1763 * Platform code can force the cpu type to optimize code
1764 * generation. In that case be sure the cpu type is correctly
1765 * manually setup otherwise it could trigger some nasty bugs.
1766 */
1767 BUG_ON(current_cpu_type() != c->cputype);
1768
2e274768
FF		 1769 if (cpu_has_rixi) {
1770 /* Enable the RIXI exceptions */
1771 set_c0_pagegrain(PG_IEC);
1772 back_to_back_c0_hazard();
1773 /* Verify the IEC bit is set */
1774 if (read_c0_pagegrain() & PG_IEC)
1775 c->options |= MIPS_CPU_RIXIEX;
1776 }
1777
0103d23f
KC		 1778 if (mips_fpu_disabled)
1779 c->options &= ~MIPS_CPU_FPU;
1780
1781 if (mips_dsp_disabled)
ee80f7c7 1782 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1783
3d528b32
MC		 1784 if (mips_htw_disabled) {
1785 c->options &= ~MIPS_CPU_HTW;
1786 write_c0_pwctl(read_c0_pwctl() &
1787 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1788 }
1789
7aecd5ca
MR		 1790 if (c->options & MIPS_CPU_FPU)
1791 cpu_set_fpu_opts(c);
1792 else
1793 cpu_set_nofpu_opts(c);
9966db25 1794
8d5ded16
JK		 1795 if (cpu_has_bp_ghist)
1796 write_c0_r10k_diag(read_c0_r10k_diag() |
1797 R10K_DIAG_E_GHIST);
1798
8b8aa636 1799 if (cpu_has_mips_r2_r6) {
f6771dbb 1800 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1801 /* R2 has Performance Counter Interrupt indicator */
1802 c->options |= MIPS_CPU_PCI;
1803 }
f6771dbb
RB		 1804 else
1805 c->srsets = 1;
91dfc423 1806
4c063034
PB		 1807 if (cpu_has_mips_r6)
1808 elf_hwcap |= HWCAP_MIPS_R6;
1809
a8ad1367 1810 if (cpu_has_msa) {
a5e9a69e 1811 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1812 WARN(c->msa_id & MSA_IR_WRPF,
1813 "Vector register partitioning unimplemented!");
3cc9fa7f 1814 elf_hwcap |= HWCAP_MIPS_MSA;
a8ad1367 1815 }
a5e9a69e 1816
91dfc423 1817 cpu_probe_vmbits(c);
949e51be
DD		 1818
1819#ifdef CONFIG_64BIT
1820 if (cpu == 0)
1821 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1822#endif
1da177e4
LT		 1823}
1824
078a55fc 1825void cpu_report(void)
1da177e4
LT		 1826{
1827 struct cpuinfo_mips *c = &current_cpu_data;
1828
d9f897c9
LY		 1829 pr_info("CPU%d revision is: %08x (%s)\n",
1830 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1831 if (c->options & MIPS_CPU_FPU)
9966db25 1832 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1833 if (cpu_has_msa)
1834 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1835}
Linux kernel - Deliverables
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