projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
MIPS: SMTC: Use %p to format pointers
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
4194318c 7 * Copyright (C) 2001, 2004 MIPS Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
f8ede0f7 19#include <linux/module.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4
LT		 22#include <asm/cpu.h>
23#include <asm/fpu.h>
24#include <asm/mipsregs.h>
25#include <asm/system.h>
654f57bf 26#include <asm/watch.h>
a074f0e8 27#include <asm/spram.h>
1da177e4
LT		 28/*
29 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
30 * the implementation of the "wait" feature differs between CPU families. This
31 * points to the function that implements CPU specific wait.
32 * The wait instruction stops the pipeline and reduces the power consumption of
33 * the CPU very much.
34 */
982f6ffe 35void (*cpu_wait)(void);
f8ede0f7 36EXPORT_SYMBOL(cpu_wait);
1da177e4
LT		 37
38static void r3081_wait(void)
39{
40 unsigned long cfg = read_c0_conf();
41 write_c0_conf(cfg | R30XX_CONF_HALT);
42}
43
44static void r39xx_wait(void)
45{
60a6c377
AN		 46 local_irq_disable();
47 if (!need_resched())
48 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
49 local_irq_enable();
1da177e4
LT		 50}
51
c65a5480 52extern void r4k_wait(void);
60a6c377
AN		 53
54/*
55 * This variant is preferable as it allows testing need_resched and going to
56 * sleep depending on the outcome atomically. Unfortunately the "It is
57 * implementation-dependent whether the pipeline restarts when a non-enabled
58 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
59 * using this version a gamble.
60 */
8531a35e 61void r4k_wait_irqoff(void)
60a6c377
AN		 62{
63 local_irq_disable();
64 if (!need_resched())
8531a35e
KK		 65 __asm__(" .set push \n"
66 " .set mips3 \n"
60a6c377 67 " wait \n"
8531a35e 68 " .set pop \n");
60a6c377 69 local_irq_enable();
8531a35e
KK		 70 __asm__(" .globl __pastwait \n"
71 "__pastwait: \n");
72 return;
1da177e4
LT		 73}
74
5a812999
RB		 75/*
76 * The RM7000 variant has to handle erratum 38. The workaround is to not
77 * have any pending stores when the WAIT instruction is executed.
78 */
79static void rm7k_wait_irqoff(void)
80{
81 local_irq_disable();
82 if (!need_resched())
83 __asm__(
84 " .set push \n"
85 " .set mips3 \n"
86 " .set noat \n"
87 " mfc0 $1, $12 \n"
88 " sync \n"
89 " mtc0 $1, $12 # stalls until W stage \n"
90 " wait \n"
91 " mtc0 $1, $12 # stalls until W stage \n"
92 " .set pop \n");
93 local_irq_enable();
94}
95
2882b0c6
ML		 96/*
97 * The Au1xxx wait is available only if using 32khz counter or
98 * external timer source, but specifically not CP0 Counter.
99 * alchemy/common/time.c may override cpu_wait!
100 */
494900af 101static void au1k_wait(void)
1da177e4 102{
60a6c377
AN		 103 __asm__(" .set mips3 \n"
104 " cache 0x14, 0(%0) \n"
105 " cache 0x14, 32(%0) \n"
106 " sync \n"
107 " nop \n"
108 " wait \n"
109 " nop \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " .set mips0 \n"
10f650db 114 : : "r" (au1k_wait));
1da177e4
LT		 115}
116
982f6ffe 117static int __initdata nowait;
55d04dff 118
f49a747c 119static int __init wait_disable(char *s)
55d04dff
RB		 120{
121 nowait = 1;
122
123 return 1;
124}
125
126__setup("nowait", wait_disable);
127
0103d23f
KC		 128static int __cpuinitdata mips_fpu_disabled;
129
130static int __init fpu_disable(char *s)
131{
132 cpu_data[0].options &= ~MIPS_CPU_FPU;
133 mips_fpu_disabled = 1;
134
135 return 1;
136}
137
138__setup("nofpu", fpu_disable);
139
140int __cpuinitdata mips_dsp_disabled;
141
142static int __init dsp_disable(char *s)
143{
144 cpu_data[0].ases &= ~MIPS_ASE_DSP;
145 mips_dsp_disabled = 1;
146
147 return 1;
148}
149
150__setup("nodsp", dsp_disable);
151
c65a5480 152void __init check_wait(void)
1da177e4
LT		 153{
154 struct cpuinfo_mips *c = &current_cpu_data;
155
55d04dff 156 if (nowait) {
c2379230 157 printk("Wait instruction disabled.\n");
55d04dff
RB		 158 return;
159 }
160
1da177e4
LT		 161 switch (c->cputype) {
162 case CPU_R3081:
163 case CPU_R3081E:
164 cpu_wait = r3081_wait;
1da177e4
LT		 165 break;
166 case CPU_TX3927:
167 cpu_wait = r39xx_wait;
1da177e4
LT		 168 break;
169 case CPU_R4200:
170/* case CPU_R4300: */
171 case CPU_R4600:
172 case CPU_R4640:
173 case CPU_R4650:
174 case CPU_R4700:
175 case CPU_R5000:
a644b277 176 case CPU_R5500:
1da177e4 177 case CPU_NEVADA:
1da177e4
LT		 178 case CPU_4KC:
179 case CPU_4KEC:
180 case CPU_4KSC:
181 case CPU_5KC:
1da177e4 182 case CPU_25KF:
4b3e975e 183 case CPU_PR4450:
1c0c13eb 184 case CPU_BCM3302:
0de663ef
MB		 185 case CPU_BCM6338:
186 case CPU_BCM6348:
187 case CPU_BCM6358:
0dd4781b 188 case CPU_CAVIUM_OCTEON:
6f329468 189 case CPU_CAVIUM_OCTEON_PLUS:
83ccf69d 190 case CPU_JZRISC:
4b3e975e
RB		 191 cpu_wait = r4k_wait;
192 break;
193
5a812999
RB		 194 case CPU_RM7000:
195 cpu_wait = rm7k_wait_irqoff;
196 break;
197
4b3e975e 198 case CPU_24K:
bbc7f22f 199 case CPU_34K:
39b8d525 200 case CPU_1004K:
4b3e975e
RB		 201 cpu_wait = r4k_wait;
202 if (read_c0_config7() & MIPS_CONF7_WII)
203 cpu_wait = r4k_wait_irqoff;
204 break;
205
c620953c 206 case CPU_74K:
1da177e4 207 cpu_wait = r4k_wait;
4b3e975e
RB		 208 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
209 cpu_wait = r4k_wait_irqoff;
1da177e4 210 break;
4b3e975e 211
60a6c377
AN		 212 case CPU_TX49XX:
213 cpu_wait = r4k_wait_irqoff;
60a6c377 214 break;
270717a8 215 case CPU_ALCHEMY:
0c694de1 216 cpu_wait = au1k_wait;
1da177e4 217 break;
c8eae71d
RB		 218 case CPU_20KC:
219 /*
220 * WAIT on Rev1.0 has E1, E2, E3 and E16.
221 * WAIT on Rev2.0 and Rev3.0 has E16.
222 * Rev3.1 WAIT is nop, why bother
223 */
224 if ((c->processor_id & 0xff) <= 0x64)
225 break;
226
50da469a
RB		 227 /*
228 * Another rev is incremeting c0_count at a reduced clock
229 * rate while in WAIT mode. So we basically have the choice
230 * between using the cp0 timer as clocksource or avoiding
231 * the WAIT instruction. Until more details are known,
232 * disable the use of WAIT for 20Kc entirely.
233 cpu_wait = r4k_wait;
234 */
c8eae71d 235 break;
441ee341 236 case CPU_RM9000:
c2379230 237 if ((c->processor_id & 0x00ff) >= 0x40)
441ee341 238 cpu_wait = r4k_wait;
441ee341 239 break;
1da177e4 240 default:
1da177e4
LT		 241 break;
242 }
243}
244
9267a30d
MSJ		 245static inline void check_errata(void)
246{
247 struct cpuinfo_mips *c = &current_cpu_data;
248
249 switch (c->cputype) {
250 case CPU_34K:
251 /*
252 * Erratum "RPS May Cause Incorrect Instruction Execution"
253 * This code only handles VPE0, any SMP/SMTC/RTOS code
254 * making use of VPE1 will be responsable for that VPE.
255 */
256 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
257 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
258 break;
259 default:
260 break;
261 }
262}
263
1da177e4
LT		 264void __init check_bugs32(void)
265{
9267a30d 266 check_errata();
1da177e4
LT		 267}
268
269/*
270 * Probe whether cpu has config register by trying to play with
271 * alternate cache bit and see whether it matters.
272 * It's used by cpu_probe to distinguish between R3000A and R3081.
273 */
274static inline int cpu_has_confreg(void)
275{
276#ifdef CONFIG_CPU_R3000
277 extern unsigned long r3k_cache_size(unsigned long);
278 unsigned long size1, size2;
279 unsigned long cfg = read_c0_conf();
280
281 size1 = r3k_cache_size(ST0_ISC);
282 write_c0_conf(cfg ^ R30XX_CONF_AC);
283 size2 = r3k_cache_size(ST0_ISC);
284 write_c0_conf(cfg);
285 return size1 != size2;
286#else
287 return 0;
288#endif
289}
290
291/*
292 * Get the FPU Implementation/Revision.
293 */
294static inline unsigned long cpu_get_fpu_id(void)
295{
296 unsigned long tmp, fpu_id;
297
298 tmp = read_c0_status();
299 __enable_fpu();
300 fpu_id = read_32bit_cp1_register(CP1_REVISION);
301 write_c0_status(tmp);
302 return fpu_id;
303}
304
305/*
306 * Check the CPU has an FPU the official way.
307 */
308static inline int __cpu_has_fpu(void)
309{
310 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
311}
312
91dfc423
GR		 313static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
314{
315#ifdef __NEED_VMBITS_PROBE
5b7efa89 316 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 317 back_to_back_c0_hazard();
5b7efa89 318 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 319#endif
320}
321
02cf2119 322#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 323 | MIPS_CPU_COUNTER)
324
cea7e2df 325static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4
LT		 326{
327 switch (c->processor_id & 0xff00) {
328 case PRID_IMP_R2000:
329 c->cputype = CPU_R2000;
cea7e2df 330 __cpu_name[cpu] = "R2000";
1da177e4 331 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 332 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
333 MIPS_CPU_NOFPUEX;
1da177e4
LT		 334 if (__cpu_has_fpu())
335 c->options |= MIPS_CPU_FPU;
336 c->tlbsize = 64;
337 break;
338 case PRID_IMP_R3000:
cea7e2df
RB		 339 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
340 if (cpu_has_confreg()) {
1da177e4 341 c->cputype = CPU_R3081E;
cea7e2df
RB		 342 __cpu_name[cpu] = "R3081";
343 } else {
1da177e4 344 c->cputype = CPU_R3000A;
cea7e2df
RB		 345 __cpu_name[cpu] = "R3000A";
346 }
347 break;
348 } else {
1da177e4 349 c->cputype = CPU_R3000;
cea7e2df
RB		 350 __cpu_name[cpu] = "R3000";
351 }
1da177e4 352 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 353 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
354 MIPS_CPU_NOFPUEX;
1da177e4
LT		 355 if (__cpu_has_fpu())
356 c->options |= MIPS_CPU_FPU;
357 c->tlbsize = 64;
358 break;
359 case PRID_IMP_R4000:
360 if (read_c0_config() & CONF_SC) {
cea7e2df 361 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 362 c->cputype = CPU_R4400PC;
cea7e2df
RB		 363 __cpu_name[cpu] = "R4400PC";
364 } else {
1da177e4 365 c->cputype = CPU_R4000PC;
cea7e2df
RB		 366 __cpu_name[cpu] = "R4000PC";
367 }
1da177e4 368 } else {
cea7e2df 369 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 370 c->cputype = CPU_R4400SC;
cea7e2df
RB		 371 __cpu_name[cpu] = "R4400SC";
372 } else {
1da177e4 373 c->cputype = CPU_R4000SC;
cea7e2df
RB		 374 __cpu_name[cpu] = "R4000SC";
375 }
1da177e4
LT		 376 }
377
378 c->isa_level = MIPS_CPU_ISA_III;
379 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
380 MIPS_CPU_WATCH | MIPS_CPU_VCE |
381 MIPS_CPU_LLSC;
382 c->tlbsize = 48;
383 break;
384 case PRID_IMP_VR41XX:
385 switch (c->processor_id & 0xf0) {
1da177e4
LT		 386 case PRID_REV_VR4111:
387 c->cputype = CPU_VR4111;
cea7e2df 388 __cpu_name[cpu] = "NEC VR4111";
1da177e4 389 break;
1da177e4
LT		 390 case PRID_REV_VR4121:
391 c->cputype = CPU_VR4121;
cea7e2df 392 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 393 break;
394 case PRID_REV_VR4122:
cea7e2df 395 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 396 c->cputype = CPU_VR4122;
cea7e2df
RB		 397 __cpu_name[cpu] = "NEC VR4122";
398 } else {
1da177e4 399 c->cputype = CPU_VR4181A;
cea7e2df
RB		 400 __cpu_name[cpu] = "NEC VR4181A";
401 }
1da177e4
LT		 402 break;
403 case PRID_REV_VR4130:
cea7e2df 404 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 405 c->cputype = CPU_VR4131;
cea7e2df
RB		 406 __cpu_name[cpu] = "NEC VR4131";
407 } else {
1da177e4 408 c->cputype = CPU_VR4133;
cea7e2df
RB		 409 __cpu_name[cpu] = "NEC VR4133";
410 }
1da177e4
LT		 411 break;
412 default:
413 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
414 c->cputype = CPU_VR41XX;
cea7e2df 415 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 416 break;
417 }
418 c->isa_level = MIPS_CPU_ISA_III;
419 c->options = R4K_OPTS;
420 c->tlbsize = 32;
421 break;
422 case PRID_IMP_R4300:
423 c->cputype = CPU_R4300;
cea7e2df 424 __cpu_name[cpu] = "R4300";
1da177e4
LT		 425 c->isa_level = MIPS_CPU_ISA_III;
426 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
427 MIPS_CPU_LLSC;
428 c->tlbsize = 32;
429 break;
430 case PRID_IMP_R4600:
431 c->cputype = CPU_R4600;
cea7e2df 432 __cpu_name[cpu] = "R4600";
1da177e4 433 c->isa_level = MIPS_CPU_ISA_III;
075e7502
TS		 434 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
435 MIPS_CPU_LLSC;
1da177e4
LT		 436 c->tlbsize = 48;
437 break;
438 #if 0
439 case PRID_IMP_R4650:
440 /*
441 * This processor doesn't have an MMU, so it's not
442 * "real easy" to run Linux on it. It is left purely
443 * for documentation. Commented out because it shares
444 * it's c0_prid id number with the TX3900.
445 */
a3dddd56 446 c->cputype = CPU_R4650;
cea7e2df 447 __cpu_name[cpu] = "R4650";
1da177e4
LT		 448 c->isa_level = MIPS_CPU_ISA_III;
449 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
450 c->tlbsize = 48;
451 break;
452 #endif
453 case PRID_IMP_TX39:
454 c->isa_level = MIPS_CPU_ISA_I;
02cf2119 455 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 456
457 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
458 c->cputype = CPU_TX3927;
cea7e2df 459 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 460 c->tlbsize = 64;
461 } else {
462 switch (c->processor_id & 0xff) {
463 case PRID_REV_TX3912:
464 c->cputype = CPU_TX3912;
cea7e2df 465 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 466 c->tlbsize = 32;
467 break;
468 case PRID_REV_TX3922:
469 c->cputype = CPU_TX3922;
cea7e2df 470 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 471 c->tlbsize = 64;
472 break;
1da177e4
LT		 473 }
474 }
475 break;
476 case PRID_IMP_R4700:
477 c->cputype = CPU_R4700;
cea7e2df 478 __cpu_name[cpu] = "R4700";
1da177e4
LT		 479 c->isa_level = MIPS_CPU_ISA_III;
480 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
481 MIPS_CPU_LLSC;
482 c->tlbsize = 48;
483 break;
484 case PRID_IMP_TX49:
485 c->cputype = CPU_TX49XX;
cea7e2df 486 __cpu_name[cpu] = "R49XX";
1da177e4
LT		 487 c->isa_level = MIPS_CPU_ISA_III;
488 c->options = R4K_OPTS | MIPS_CPU_LLSC;
489 if (!(c->processor_id & 0x08))
490 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
491 c->tlbsize = 48;
492 break;
493 case PRID_IMP_R5000:
494 c->cputype = CPU_R5000;
cea7e2df 495 __cpu_name[cpu] = "R5000";
1da177e4
LT		 496 c->isa_level = MIPS_CPU_ISA_IV;
497 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
498 MIPS_CPU_LLSC;
499 c->tlbsize = 48;
500 break;
501 case PRID_IMP_R5432:
502 c->cputype = CPU_R5432;
cea7e2df 503 __cpu_name[cpu] = "R5432";
1da177e4
LT		 504 c->isa_level = MIPS_CPU_ISA_IV;
505 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
506 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
507 c->tlbsize = 48;
508 break;
509 case PRID_IMP_R5500:
510 c->cputype = CPU_R5500;
cea7e2df 511 __cpu_name[cpu] = "R5500";
1da177e4
LT		 512 c->isa_level = MIPS_CPU_ISA_IV;
513 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
514 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
515 c->tlbsize = 48;
516 break;
517 case PRID_IMP_NEVADA:
518 c->cputype = CPU_NEVADA;
cea7e2df 519 __cpu_name[cpu] = "Nevada";
1da177e4
LT		 520 c->isa_level = MIPS_CPU_ISA_IV;
521 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
522 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
523 c->tlbsize = 48;
524 break;
525 case PRID_IMP_R6000:
526 c->cputype = CPU_R6000;
cea7e2df 527 __cpu_name[cpu] = "R6000";
1da177e4
LT		 528 c->isa_level = MIPS_CPU_ISA_II;
529 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
530 MIPS_CPU_LLSC;
531 c->tlbsize = 32;
532 break;
533 case PRID_IMP_R6000A:
534 c->cputype = CPU_R6000A;
cea7e2df 535 __cpu_name[cpu] = "R6000A";
1da177e4
LT		 536 c->isa_level = MIPS_CPU_ISA_II;
537 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
538 MIPS_CPU_LLSC;
539 c->tlbsize = 32;
540 break;
541 case PRID_IMP_RM7000:
542 c->cputype = CPU_RM7000;
cea7e2df 543 __cpu_name[cpu] = "RM7000";
1da177e4
LT		 544 c->isa_level = MIPS_CPU_ISA_IV;
545 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
546 MIPS_CPU_LLSC;
547 /*
548 * Undocumented RM7000: Bit 29 in the info register of
549 * the RM7000 v2.0 indicates if the TLB has 48 or 64
550 * entries.
551 *
552 * 29 1 => 64 entry JTLB
553 * 0 => 48 entry JTLB
554 */
555 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
556 break;
557 case PRID_IMP_RM9000:
558 c->cputype = CPU_RM9000;
cea7e2df 559 __cpu_name[cpu] = "RM9000";
1da177e4
LT		 560 c->isa_level = MIPS_CPU_ISA_IV;
561 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
562 MIPS_CPU_LLSC;
563 /*
564 * Bit 29 in the info register of the RM9000
565 * indicates if the TLB has 48 or 64 entries.
566 *
567 * 29 1 => 64 entry JTLB
568 * 0 => 48 entry JTLB
569 */
570 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
571 break;
572 case PRID_IMP_R8000:
573 c->cputype = CPU_R8000;
cea7e2df 574 __cpu_name[cpu] = "RM8000";
1da177e4
LT		 575 c->isa_level = MIPS_CPU_ISA_IV;
576 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
577 MIPS_CPU_FPU | MIPS_CPU_32FPR |
578 MIPS_CPU_LLSC;
579 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
580 break;
581 case PRID_IMP_R10000:
582 c->cputype = CPU_R10000;
cea7e2df 583 __cpu_name[cpu] = "R10000";
1da177e4 584 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 585 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 586 MIPS_CPU_FPU | MIPS_CPU_32FPR |
587 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
588 MIPS_CPU_LLSC;
589 c->tlbsize = 64;
590 break;
591 case PRID_IMP_R12000:
592 c->cputype = CPU_R12000;
cea7e2df 593 __cpu_name[cpu] = "R12000";
1da177e4 594 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 595 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 596 MIPS_CPU_FPU | MIPS_CPU_32FPR |
597 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
598 MIPS_CPU_LLSC;
599 c->tlbsize = 64;
600 break;
44d921b2
K		 601 case PRID_IMP_R14000:
602 c->cputype = CPU_R14000;
cea7e2df 603 __cpu_name[cpu] = "R14000";
44d921b2
K		 604 c->isa_level = MIPS_CPU_ISA_IV;
605 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
606 MIPS_CPU_FPU | MIPS_CPU_32FPR |
607 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
608 MIPS_CPU_LLSC;
609 c->tlbsize = 64;
610 break;
2a21c730
FZ		 611 case PRID_IMP_LOONGSON2:
612 c->cputype = CPU_LOONGSON2;
cea7e2df 613 __cpu_name[cpu] = "ICT Loongson-2";
2a21c730
FZ		 614 c->isa_level = MIPS_CPU_ISA_III;
615 c->options = R4K_OPTS |
616 MIPS_CPU_FPU | MIPS_CPU_LLSC |
617 MIPS_CPU_32FPR;
618 c->tlbsize = 64;
619 break;
1da177e4
LT		 620 }
621}
622
234fcd14 623static char unknown_isa[] __cpuinitdata = KERN_ERR \
b4672d37
RB		 624 "Unsupported ISA type, c0.config0: %d.";
625
4194318c 626static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4 627{
4194318c
RB		 628 unsigned int config0;
629 int isa;
1da177e4 630
4194318c
RB		 631 config0 = read_c0_config();
632
633 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
02cf2119 634 c->options |= MIPS_CPU_TLB;
4194318c
RB		 635 isa = (config0 & MIPS_CONF_AT) >> 13;
636 switch (isa) {
637 case 0:
3a01c49a 638 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 639 case 0:
640 c->isa_level = MIPS_CPU_ISA_M32R1;
641 break;
642 case 1:
643 c->isa_level = MIPS_CPU_ISA_M32R2;
644 break;
645 default:
646 goto unknown;
647 }
4194318c
RB		 648 break;
649 case 2:
3a01c49a 650 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 651 case 0:
652 c->isa_level = MIPS_CPU_ISA_M64R1;
653 break;
654 case 1:
655 c->isa_level = MIPS_CPU_ISA_M64R2;
656 break;
657 default:
658 goto unknown;
659 }
4194318c
RB		 660 break;
661 default:
b4672d37 662 goto unknown;
4194318c
RB		 663 }
664
665 return config0 & MIPS_CONF_M;
b4672d37
RB		 666
667unknown:
668 panic(unknown_isa, config0);
4194318c
RB		 669}
670
671static inline unsigned int decode_config1(struct cpuinfo_mips *c)
672{
673 unsigned int config1;
1da177e4 674
1da177e4 675 config1 = read_c0_config1();
4194318c
RB		 676
677 if (config1 & MIPS_CONF1_MD)
678 c->ases |= MIPS_ASE_MDMX;
679 if (config1 & MIPS_CONF1_WR)
1da177e4 680 c->options |= MIPS_CPU_WATCH;
4194318c
RB		 681 if (config1 & MIPS_CONF1_CA)
682 c->ases |= MIPS_ASE_MIPS16;
683 if (config1 & MIPS_CONF1_EP)
1da177e4 684 c->options |= MIPS_CPU_EJTAG;
4194318c 685 if (config1 & MIPS_CONF1_FP) {
1da177e4
LT		 686 c->options |= MIPS_CPU_FPU;
687 c->options |= MIPS_CPU_32FPR;
688 }
4194318c
RB		 689 if (cpu_has_tlb)
690 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
691
692 return config1 & MIPS_CONF_M;
693}
694
695static inline unsigned int decode_config2(struct cpuinfo_mips *c)
696{
697 unsigned int config2;
698
699 config2 = read_c0_config2();
700
701 if (config2 & MIPS_CONF2_SL)
702 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
703
704 return config2 & MIPS_CONF_M;
705}
706
707static inline unsigned int decode_config3(struct cpuinfo_mips *c)
708{
709 unsigned int config3;
710
711 config3 = read_c0_config3();
712
713 if (config3 & MIPS_CONF3_SM)
714 c->ases |= MIPS_ASE_SMARTMIPS;
e50c0a8f
RB		 715 if (config3 & MIPS_CONF3_DSP)
716 c->ases |= MIPS_ASE_DSP;
8f40611d
RB		 717 if (config3 & MIPS_CONF3_VINT)
718 c->options |= MIPS_CPU_VINT;
719 if (config3 & MIPS_CONF3_VEIC)
720 c->options |= MIPS_CPU_VEIC;
721 if (config3 & MIPS_CONF3_MT)
e0daad44 722 c->ases |= MIPS_ASE_MIPSMT;
a3692020
RB		 723 if (config3 & MIPS_CONF3_ULRI)
724 c->options |= MIPS_CPU_ULRI;
4194318c
RB		 725
726 return config3 & MIPS_CONF_M;
727}
728
1b362e3e
DD		 729static inline unsigned int decode_config4(struct cpuinfo_mips *c)
730{
731 unsigned int config4;
732
733 config4 = read_c0_config4();
734
735 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
736 && cpu_has_tlb)
737 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
738
739 return config4 & MIPS_CONF_M;
740}
741
234fcd14 742static void __cpuinit decode_configs(struct cpuinfo_mips *c)
4194318c 743{
558ce124
RB		 744 int ok;
745
4194318c 746 /* MIPS32 or MIPS64 compliant CPU. */
02cf2119
RB		 747 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
748 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
4194318c 749
1da177e4
LT		 750 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
751
558ce124
RB		 752 ok = decode_config0(c); /* Read Config registers. */
753 BUG_ON(!ok); /* Arch spec violation! */
754 if (ok)
755 ok = decode_config1(c);
756 if (ok)
757 ok = decode_config2(c);
758 if (ok)
759 ok = decode_config3(c);
1b362e3e
DD		 760 if (ok)
761 ok = decode_config4(c);
558ce124
RB		 762
763 mips_probe_watch_registers(c);
1da177e4
LT		 764}
765
cea7e2df 766static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 767{
4194318c 768 decode_configs(c);
1da177e4
LT		 769 switch (c->processor_id & 0xff00) {
770 case PRID_IMP_4KC:
771 c->cputype = CPU_4KC;
cea7e2df 772 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 773 break;
774 case PRID_IMP_4KEC:
2b07bd02
RB		 775 case PRID_IMP_4KECR2:
776 c->cputype = CPU_4KEC;
cea7e2df 777 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 778 break;
1da177e4 779 case PRID_IMP_4KSC:
8afcb5d8 780 case PRID_IMP_4KSD:
1da177e4 781 c->cputype = CPU_4KSC;
cea7e2df 782 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 783 break;
784 case PRID_IMP_5KC:
785 c->cputype = CPU_5KC;
cea7e2df 786 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4
LT		 787 break;
788 case PRID_IMP_20KC:
789 c->cputype = CPU_20KC;
cea7e2df 790 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 791 break;
792 case PRID_IMP_24K:
e50c0a8f 793 case PRID_IMP_24KE:
1da177e4 794 c->cputype = CPU_24K;
cea7e2df 795 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4
LT		 796 break;
797 case PRID_IMP_25KF:
798 c->cputype = CPU_25KF;
cea7e2df 799 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 800 break;
bbc7f22f
RB		 801 case PRID_IMP_34K:
802 c->cputype = CPU_34K;
cea7e2df 803 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 804 break;
c620953c
CD		 805 case PRID_IMP_74K:
806 c->cputype = CPU_74K;
cea7e2df 807 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 808 break;
39b8d525
RB		 809 case PRID_IMP_1004K:
810 c->cputype = CPU_1004K;
cea7e2df 811 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 812 break;
1da177e4 813 }
0b6d497f
CD		 814
815 spram_config();
1da177e4
LT		 816}
817
cea7e2df 818static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 819{
4194318c 820 decode_configs(c);
1da177e4
LT		 821 switch (c->processor_id & 0xff00) {
822 case PRID_IMP_AU1_REV1:
823 case PRID_IMP_AU1_REV2:
270717a8 824 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 825 switch ((c->processor_id >> 24) & 0xff) {
826 case 0:
cea7e2df 827 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 828 break;
829 case 1:
cea7e2df 830 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 831 break;
832 case 2:
cea7e2df 833 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 834 break;
835 case 3:
cea7e2df 836 __cpu_name[cpu] = "Au1550";
1da177e4 837 break;
e3ad1c23 838 case 4:
cea7e2df 839 __cpu_name[cpu] = "Au1200";
270717a8 840 if ((c->processor_id & 0xff) == 2)
cea7e2df 841 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 842 break;
843 case 5:
cea7e2df 844 __cpu_name[cpu] = "Au1210";
e3ad1c23 845 break;
1da177e4 846 default:
270717a8 847 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 848 break;
849 }
1da177e4
LT		 850 break;
851 }
852}
853
cea7e2df 854static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 855{
4194318c 856 decode_configs(c);
02cf2119 857
1da177e4
LT		 858 switch (c->processor_id & 0xff00) {
859 case PRID_IMP_SB1:
860 c->cputype = CPU_SB1;
cea7e2df 861 __cpu_name[cpu] = "SiByte SB1";
1da177e4 862 /* FPU in pass1 is known to have issues. */
aa32374a 863 if ((c->processor_id & 0xff) < 0x02)
010b853b 864 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 865 break;
93ce2f52
AI		 866 case PRID_IMP_SB1A:
867 c->cputype = CPU_SB1A;
cea7e2df 868 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 869 break;
1da177e4
LT		 870 }
871}
872
cea7e2df 873static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 874{
4194318c 875 decode_configs(c);
1da177e4
LT		 876 switch (c->processor_id & 0xff00) {
877 case PRID_IMP_SR71000:
878 c->cputype = CPU_SR71000;
cea7e2df 879 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 880 c->scache.ways = 8;
881 c->tlbsize = 64;
882 break;
883 }
884}
885
cea7e2df 886static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 887{
888 decode_configs(c);
889 switch (c->processor_id & 0xff00) {
890 case PRID_IMP_PR4450:
891 c->cputype = CPU_PR4450;
cea7e2df 892 __cpu_name[cpu] = "Philips PR4450";
e7958bb9 893 c->isa_level = MIPS_CPU_ISA_M32R1;
bdf21b18 894 break;
bdf21b18
PP		 895 }
896}
897
cea7e2df 898static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 899{
900 decode_configs(c);
901 switch (c->processor_id & 0xff00) {
902 case PRID_IMP_BCM3302:
0de663ef 903 /* same as PRID_IMP_BCM6338 */
1c0c13eb 904 c->cputype = CPU_BCM3302;
cea7e2df 905 __cpu_name[cpu] = "Broadcom BCM3302";
1c0c13eb
AJ		 906 break;
907 case PRID_IMP_BCM4710:
908 c->cputype = CPU_BCM4710;
cea7e2df 909 __cpu_name[cpu] = "Broadcom BCM4710";
1c0c13eb 910 break;
0de663ef
MB		 911 case PRID_IMP_BCM6345:
912 c->cputype = CPU_BCM6345;
913 __cpu_name[cpu] = "Broadcom BCM6345";
914 break;
915 case PRID_IMP_BCM6348:
916 c->cputype = CPU_BCM6348;
917 __cpu_name[cpu] = "Broadcom BCM6348";
918 break;
919 case PRID_IMP_BCM4350:
920 switch (c->processor_id & 0xf0) {
921 case PRID_REV_BCM6358:
922 c->cputype = CPU_BCM6358;
923 __cpu_name[cpu] = "Broadcom BCM6358";
924 break;
925 default:
926 c->cputype = CPU_UNKNOWN;
927 break;
928 }
929 break;
1c0c13eb
AJ		 930 }
931}
932
0dd4781b
DD		 933static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
934{
935 decode_configs(c);
936 switch (c->processor_id & 0xff00) {
937 case PRID_IMP_CAVIUM_CN38XX:
938 case PRID_IMP_CAVIUM_CN31XX:
939 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 940 c->cputype = CPU_CAVIUM_OCTEON;
941 __cpu_name[cpu] = "Cavium Octeon";
942 goto platform;
0dd4781b
DD		 943 case PRID_IMP_CAVIUM_CN58XX:
944 case PRID_IMP_CAVIUM_CN56XX:
945 case PRID_IMP_CAVIUM_CN50XX:
946 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 947 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
948 __cpu_name[cpu] = "Cavium Octeon+";
949platform:
368bf8ef
DD		 950 if (cpu == 0)
951 __elf_platform = "octeon";
0dd4781b
DD		 952 break;
953 default:
954 printk(KERN_INFO "Unknown Octeon chip!\n");
955 c->cputype = CPU_UNKNOWN;
956 break;
957 }
958}
959
83ccf69d
LPC		 960static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
961{
962 decode_configs(c);
963 /* JZRISC does not implement the CP0 counter. */
964 c->options &= ~MIPS_CPU_COUNTER;
965 switch (c->processor_id & 0xff00) {
966 case PRID_IMP_JZRISC:
967 c->cputype = CPU_JZRISC;
968 __cpu_name[cpu] = "Ingenic JZRISC";
969 break;
970 default:
971 panic("Unknown Ingenic Processor ID!");
972 break;
973 }
974}
975
9966db25 976const char *__cpu_name[NR_CPUS];
874fd3b5 977const char *__elf_platform;
9966db25 978
234fcd14 979__cpuinit void cpu_probe(void)
1da177e4
LT		 980{
981 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 982 unsigned int cpu = smp_processor_id();
1da177e4
LT		 983
984 c->processor_id = PRID_IMP_UNKNOWN;
985 c->fpu_id = FPIR_IMP_NONE;
986 c->cputype = CPU_UNKNOWN;
987
988 c->processor_id = read_c0_prid();
989 switch (c->processor_id & 0xff0000) {
990 case PRID_COMP_LEGACY:
cea7e2df 991 cpu_probe_legacy(c, cpu);
1da177e4
LT		 992 break;
993 case PRID_COMP_MIPS:
cea7e2df 994 cpu_probe_mips(c, cpu);
1da177e4
LT		 995 break;
996 case PRID_COMP_ALCHEMY:
cea7e2df 997 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 998 break;
999 case PRID_COMP_SIBYTE:
cea7e2df 1000 cpu_probe_sibyte(c, cpu);
1da177e4 1001 break;
1c0c13eb 1002 case PRID_COMP_BROADCOM:
cea7e2df 1003 cpu_probe_broadcom(c, cpu);
1c0c13eb 1004 break;
1da177e4 1005 case PRID_COMP_SANDCRAFT:
cea7e2df 1006 cpu_probe_sandcraft(c, cpu);
1da177e4 1007 break;
a92b0588 1008 case PRID_COMP_NXP:
cea7e2df 1009 cpu_probe_nxp(c, cpu);
a3dddd56 1010 break;
0dd4781b
DD		 1011 case PRID_COMP_CAVIUM:
1012 cpu_probe_cavium(c, cpu);
1013 break;
83ccf69d
LPC		 1014 case PRID_COMP_INGENIC:
1015 cpu_probe_ingenic(c, cpu);
1016 break;
1da177e4 1017 }
dec8b1ca 1018
cea7e2df
RB		 1019 BUG_ON(!__cpu_name[cpu]);
1020 BUG_ON(c->cputype == CPU_UNKNOWN);
1021
dec8b1ca
FBH		 1022 /*
1023 * Platform code can force the cpu type to optimize code
1024 * generation. In that case be sure the cpu type is correctly
1025 * manually setup otherwise it could trigger some nasty bugs.
1026 */
1027 BUG_ON(current_cpu_type() != c->cputype);
1028
0103d23f
KC		 1029 if (mips_fpu_disabled)
1030 c->options &= ~MIPS_CPU_FPU;
1031
1032 if (mips_dsp_disabled)
1033 c->ases &= ~MIPS_ASE_DSP;
1034
4194318c 1035 if (c->options & MIPS_CPU_FPU) {
1da177e4 1036 c->fpu_id = cpu_get_fpu_id();
4194318c 1037
e7958bb9 1038 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
b4672d37
RB		 1039 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1040 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1041 c->isa_level == MIPS_CPU_ISA_M64R2) {
4194318c
RB		 1042 if (c->fpu_id & MIPS_FPIR_3D)
1043 c->ases |= MIPS_ASE_MIPS3D;
1044 }
1045 }
9966db25 1046
f6771dbb
RB		 1047 if (cpu_has_mips_r2)
1048 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1049 else
1050 c->srsets = 1;
91dfc423
GR		 1051
1052 cpu_probe_vmbits(c);
1da177e4
LT		 1053}
1054
234fcd14 1055__cpuinit void cpu_report(void)
1da177e4
LT		 1056{
1057 struct cpuinfo_mips *c = &current_cpu_data;
1058
9966db25
RB		 1059 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1060 c->processor_id, cpu_name_string());
1da177e4 1061 if (c->options & MIPS_CPU_FPU)
9966db25 1062 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 1063}
Linux kernel - Deliverables
This page took 1.324587 seconds and 5 git commands to generate.