[deliverable/linux.git] / arch / mips / kernel / entry.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2001 MIPS Technologies, Inc.
 */

#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/isadep.h>
#include <asm/thread_info.h>
#include <asm/war.h>
#ifdef CONFIG_MIPS_MT_SMTC
#include <asm/mipsmtregs.h>
#endif

#ifndef CONFIG_PREEMPT
	.macro	preempt_stop
	local_irq_disable
	.endm
#define resume_kernel	restore_all
#endif

	.text
	.align	5
FEXPORT(ret_from_irq)
	LONG_S	s0, TI_REGS($28)
#ifdef CONFIG_PREEMPT
FEXPORT(ret_from_exception)
#else
	b	_ret_from_irq
FEXPORT(ret_from_exception)
	preempt_stop
#endif
FEXPORT(_ret_from_irq)
	LONG_L	t0, PT_STATUS(sp)		# returning to kernel mode?
	andi	t0, t0, KU_USER
	beqz	t0, resume_kernel

resume_userspace:
	local_irq_disable		# make sure we dont miss an
					# interrupt setting need_resched
					# between sampling and return
	LONG_L	a2, TI_FLAGS($28)	# current->work
	andi	t0, a2, _TIF_WORK_MASK	# (ignoring syscall_trace)
	bnez	t0, work_pending
	j	restore_all

#ifdef CONFIG_PREEMPT
resume_kernel:
	local_irq_disable
	lw	t0, TI_PRE_COUNT($28)
	bnez	t0, restore_all
need_resched:
	LONG_L	t0, TI_FLAGS($28)
	andi	t1, t0, _TIF_NEED_RESCHED
	beqz	t1, restore_all
	LONG_L	t0, PT_STATUS(sp)		# Interrupts off?
	andi	t0, 1
	beqz	t0, restore_all
	jal	preempt_schedule_irq
	b	need_resched
#endif

FEXPORT(ret_from_fork)
	jal	schedule_tail		# a0 = struct task_struct *prev

FEXPORT(syscall_exit)
	local_irq_disable		# make sure need_resched and
					# signals dont change between
					# sampling and return
	LONG_L	a2, TI_FLAGS($28)	# current->work
	li	t0, _TIF_ALLWORK_MASK
	and	t0, a2, t0
	bnez	t0, syscall_exit_work

FEXPORT(restore_all)			# restore full frame
#ifdef CONFIG_MIPS_MT_SMTC
/* Detect and execute deferred IPI "interrupts" */
	LONG_L	s0, TI_REGS($28)
	LONG_S	sp, TI_REGS($28)
	jal	deferred_smtc_ipi
	LONG_S	s0, TI_REGS($28)
/* Re-arm any temporarily masked interrupts not explicitly "acked" */
	mfc0	v0, CP0_TCSTATUS
	ori	v1, v0, TCSTATUS_IXMT
	mtc0	v1, CP0_TCSTATUS
	andi	v0, TCSTATUS_IXMT
	_ehb
	mfc0	t0, CP0_TCCONTEXT
	DMT	9				# dmt t1
	jal	mips_ihb
	mfc0	t2, CP0_STATUS
	andi	t3, t0, 0xff00
	or	t2, t2, t3
	mtc0	t2, CP0_STATUS
	_ehb
	andi	t1, t1, VPECONTROL_TE
	beqz	t1, 1f
	EMT
1:
	mfc0	v1, CP0_TCSTATUS
	/* We set IXMT above, XOR should clear it here */
	xori	v1, v1, TCSTATUS_IXMT
	or	v1, v0, v1
	mtc0	v1, CP0_TCSTATUS
	_ehb
	xor	t0, t0, t3
	mtc0	t0, CP0_TCCONTEXT
#endif /* CONFIG_MIPS_MT_SMTC */
	.set	noat
	RESTORE_TEMP
	RESTORE_AT
	RESTORE_STATIC
FEXPORT(restore_partial)		# restore partial frame
#ifdef CONFIG_TRACE_IRQFLAGS
	SAVE_STATIC
	SAVE_AT
	SAVE_TEMP
	LONG_L	v0, PT_STATUS(sp)
	and	v0, 1
	beqz	v0, 1f
	jal	trace_hardirqs_on
	b	2f
1:	jal	trace_hardirqs_off
2:
	RESTORE_TEMP
	RESTORE_AT
	RESTORE_STATIC
#endif
	RESTORE_SOME
	RESTORE_SP_AND_RET
	.set	at

work_pending:
	andi	t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS
	beqz	t0, work_notifysig
work_resched:
	jal	schedule

	local_irq_disable		# make sure need_resched and
					# signals dont change between
					# sampling and return
	LONG_L	a2, TI_FLAGS($28)
	andi	t0, a2, _TIF_WORK_MASK	# is there any work to be done
					# other than syscall tracing?
	beqz	t0, restore_all
	andi	t0, a2, _TIF_NEED_RESCHED
	bnez	t0, work_resched

work_notifysig:				# deal with pending signals and
					# notify-resume requests
	move	a0, sp
	li	a1, 0
	jal	do_notify_resume	# a2 already loaded
	j	resume_userspace

FEXPORT(syscall_exit_work_partial)
	SAVE_STATIC
syscall_exit_work:
	li	t0, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
	and	t0, a2			# a2 is preloaded with TI_FLAGS
	beqz	t0, work_pending	# trace bit set?
	local_irq_enable		# could let do_syscall_trace()
					# call schedule() instead
	move	a0, sp
	li	a1, 1
	jal	do_syscall_trace
	b	resume_userspace

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT)

/*
 * MIPS32R2 Instruction Hazard Barrier - must be called
 *
 * For C code use the inline version named instruction_hazard().
 */
LEAF(mips_ihb)
	.set	mips32r2
	jr.hb	ra
	nop
	END(mips_ihb)

#endif /* CONFIG_CPU_MIPSR2 or CONFIG_MIPS_MT */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
	7	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
	8	* Copyright (C) 2001 MIPS Technologies, Inc.
	9	*/
1da177e4 LT	10
	11	#include <asm/asm.h>
	12	#include <asm/asmmacro.h>
	13	#include <asm/regdef.h>
	14	#include <asm/mipsregs.h>
	15	#include <asm/stackframe.h>
	16	#include <asm/isadep.h>
	17	#include <asm/thread_info.h>
	18	#include <asm/war.h>
41c594ab RB	19	#ifdef CONFIG_MIPS_MT_SMTC
	20	#include <asm/mipsmtregs.h>
	21	#endif
1da177e4	22
f431baa5	23	#ifndef CONFIG_PREEMPT
c2648527 TS	24	.macro preempt_stop
c2648527 TS	25	local_irq_disable
1da177e4 LT	26	.endm
	27	#define resume_kernel restore_all
	28	#endif
	29
	30	.text
	31	.align 5
f431baa5 AN	32	FEXPORT(ret_from_irq)
	33	LONG_S s0, TI_REGS($28)
	34	#ifdef CONFIG_PREEMPT
	35	FEXPORT(ret_from_exception)
	36	#else
	37	b _ret_from_irq
1da177e4 LT	38	FEXPORT(ret_from_exception)
1da177e4 LT	39	preempt_stop
f431baa5 AN	40	#endif
f431baa5 AN	41	FEXPORT(_ret_from_irq)
1da177e4 LT	42	LONG_L t0, PT_STATUS(sp) # returning to kernel mode?
	43	andi t0, t0, KU_USER
	44	beqz t0, resume_kernel
	45
c2648527 TS	46	resume_userspace:
c2648527 TS	47	local_irq_disable # make sure we dont miss an
1da177e4 LT	48	# interrupt setting need_resched
	49	# between sampling and return
	50	LONG_L a2, TI_FLAGS($28) # current->work
c2648527 TS	51	andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace)
c2648527 TS	52	bnez t0, work_pending
1da177e4 LT	53	j restore_all
	54
	55	#ifdef CONFIG_PREEMPT
c2648527	56	resume_kernel:
a18815ab	57	local_irq_disable
1da177e4 LT	58	lw t0, TI_PRE_COUNT($28)
	59	bnez t0, restore_all
	60	need_resched:
	61	LONG_L t0, TI_FLAGS($28)
	62	andi t1, t0, _TIF_NEED_RESCHED
	63	beqz t1, restore_all
	64	LONG_L t0, PT_STATUS(sp) # Interrupts off?
	65	andi t0, 1
	66	beqz t0, restore_all
a18815ab	67	jal preempt_schedule_irq
cdaed73a	68	b need_resched
1da177e4 LT	69	#endif
	70
	71	FEXPORT(ret_from_fork)
36c8b586	72	jal schedule_tail # a0 = struct task_struct *prev
1da177e4 LT	73
	74	FEXPORT(syscall_exit)
	75	local_irq_disable # make sure need_resched and
	76	# signals dont change between
	77	# sampling and return
	78	LONG_L a2, TI_FLAGS($28) # current->work
	79	li t0, _TIF_ALLWORK_MASK
	80	and t0, a2, t0
	81	bnez t0, syscall_exit_work
	82
	83	FEXPORT(restore_all) # restore full frame
41c594ab RB	84	#ifdef CONFIG_MIPS_MT_SMTC
41c594ab RB	85	/* Detect and execute deferred IPI "interrupts" */
cb56837e RB	86	LONG_L s0, TI_REGS($28)
cb56837e RB	87	LONG_S sp, TI_REGS($28)
41c594ab	88	jal deferred_smtc_ipi
cb56837e	89	LONG_S s0, TI_REGS($28)
41c594ab RB	90	/* Re-arm any temporarily masked interrupts not explicitly "acked" */
	91	mfc0 v0, CP0_TCSTATUS
	92	ori v1, v0, TCSTATUS_IXMT
	93	mtc0 v1, CP0_TCSTATUS
	94	andi v0, TCSTATUS_IXMT
4277ff5e	95	_ehb
41c594ab RB	96	mfc0 t0, CP0_TCCONTEXT
	97	DMT 9 # dmt t1
	98	jal mips_ihb
	99	mfc0 t2, CP0_STATUS
	100	andi t3, t0, 0xff00
	101	or t2, t2, t3
	102	mtc0 t2, CP0_STATUS
4277ff5e	103	_ehb
41c594ab RB	104	andi t1, t1, VPECONTROL_TE
	105	beqz t1, 1f
	106	EMT
	107	1:
	108	mfc0 v1, CP0_TCSTATUS
477654fc	109	/* We set IXMT above, XOR should clear it here */
41c594ab RB	110	xori v1, v1, TCSTATUS_IXMT
	111	or v1, v0, v1
	112	mtc0 v1, CP0_TCSTATUS
4277ff5e	113	_ehb
41c594ab RB	114	xor t0, t0, t3
	115	mtc0 t0, CP0_TCCONTEXT
	116	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	117	.set noat
	118	RESTORE_TEMP
	119	RESTORE_AT
	120	RESTORE_STATIC
	121	FEXPORT(restore_partial) # restore partial frame
192ef366 RB	122	#ifdef CONFIG_TRACE_IRQFLAGS
	123	SAVE_STATIC
	124	SAVE_AT
	125	SAVE_TEMP
	126	LONG_L v0, PT_STATUS(sp)
	127	and v0, 1
	128	beqz v0, 1f
	129	jal trace_hardirqs_on
	130	b 2f
	131	1: jal trace_hardirqs_off
	132	2:
	133	RESTORE_TEMP
	134	RESTORE_AT
	135	RESTORE_STATIC
	136	#endif
1da177e4 LT	137	RESTORE_SOME
	138	RESTORE_SP_AND_RET
	139	.set at
	140
c2648527 TS	141	work_pending:
c2648527 TS	142	andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS
1da177e4 LT	143	beqz t0, work_notifysig
	144	work_resched:
	145	jal schedule
	146
c2648527	147	local_irq_disable # make sure need_resched and
1da177e4 LT	148	# signals dont change between
	149	# sampling and return
	150	LONG_L a2, TI_FLAGS($28)
	151	andi t0, a2, _TIF_WORK_MASK # is there any work to be done
	152	# other than syscall tracing?
	153	beqz t0, restore_all
	154	andi t0, a2, _TIF_NEED_RESCHED
	155	bnez t0, work_resched
	156
	157	work_notifysig: # deal with pending signals and
	158	# notify-resume requests
	159	move a0, sp
	160	li a1, 0
	161	jal do_notify_resume # a2 already loaded
0bf0e3e2	162	j resume_userspace
1da177e4 LT	163
	164	FEXPORT(syscall_exit_work_partial)
	165	SAVE_STATIC
c2648527 TS	166	syscall_exit_work:
	167	li t0, _TIF_SYSCALL_TRACE \| _TIF_SYSCALL_AUDIT
	168	and t0, a2 # a2 is preloaded with TI_FLAGS
	169	beqz t0, work_pending # trace bit set?
1da177e4 LT	170	local_irq_enable # could let do_syscall_trace()
	171	# call schedule() instead
	172	move a0, sp
	173	li a1, 1
	174	jal do_syscall_trace
	175	b resume_userspace
bce1a286 RB	176
	177	#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_MIPS_MT)
	178
	179	/*
	180	* MIPS32R2 Instruction Hazard Barrier - must be called
	181	*
	182	* For C code use the inline version named instruction_hazard().
	183	*/
	184	LEAF(mips_ihb)
	185	.set mips32r2
	186	jr.hb ra
	187	nop
	188	END(mips_ihb)
	189
	190	#endif /* CONFIG_CPU_MIPSR2 or CONFIG_MIPS_MT */