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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994, 1995 Waldorf Electronics | |
7 | * Written by Ralf Baechle and Andreas Busse | |
192ef366 | 8 | * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle |
1da177e4 LT |
9 | * Copyright (C) 1996 Paul M. Antoine |
10 | * Modified for DECStation and hence R3000 support by Paul M. Antoine | |
11 | * Further modifications by David S. Miller and Harald Koerfgen | |
12 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
13 | * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
14 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | |
15 | */ | |
1da177e4 LT |
16 | #include <linux/init.h> |
17 | #include <linux/threads.h> | |
18 | ||
9267a30d | 19 | #include <asm/addrspace.h> |
1da177e4 | 20 | #include <asm/asm.h> |
41c594ab | 21 | #include <asm/asmmacro.h> |
192ef366 | 22 | #include <asm/irqflags.h> |
1da177e4 | 23 | #include <asm/regdef.h> |
1da177e4 LT |
24 | #include <asm/mipsregs.h> |
25 | #include <asm/stackframe.h> | |
7e35952b RB |
26 | |
27 | #include <kernel-entry-init.h> | |
1da177e4 | 28 | |
1da177e4 LT |
29 | /* |
30 | * For the moment disable interrupts, mark the kernel mode and | |
31 | * set ST0_KX so that the CPU does not spit fire when using | |
32 | * 64-bit addresses. A full initialization of the CPU's status | |
33 | * register is done later in per_cpu_trap_init(). | |
34 | */ | |
35 | .macro setup_c0_status set clr | |
36 | .set push | |
37 | mfc0 t0, CP0_STATUS | |
38 | or t0, ST0_CU0|\set|0x1f|\clr | |
39 | xor t0, 0x1f|\clr | |
40 | mtc0 t0, CP0_STATUS | |
41 | .set noreorder | |
42 | sll zero,3 # ehb | |
43 | .set pop | |
44 | .endm | |
45 | ||
46 | .macro setup_c0_status_pri | |
875d43e7 | 47 | #ifdef CONFIG_64BIT |
1da177e4 LT |
48 | setup_c0_status ST0_KX 0 |
49 | #else | |
50 | setup_c0_status 0 0 | |
51 | #endif | |
52 | .endm | |
53 | ||
54 | .macro setup_c0_status_sec | |
875d43e7 | 55 | #ifdef CONFIG_64BIT |
1da177e4 LT |
56 | setup_c0_status ST0_KX ST0_BEV |
57 | #else | |
58 | setup_c0_status 0 ST0_BEV | |
59 | #endif | |
60 | .endm | |
61 | ||
9267a30d | 62 | #ifndef CONFIG_NO_EXCEPT_FILL |
1da177e4 LT |
63 | /* |
64 | * Reserved space for exception handlers. | |
65 | * Necessary for machines which link their kernels at KSEG0. | |
66 | */ | |
67 | .fill 0x400 | |
9267a30d | 68 | #endif |
1da177e4 | 69 | |
1da177e4 LT |
70 | EXPORT(_stext) |
71 | ||
396a2ae0 | 72 | #ifdef CONFIG_BOOT_RAW |
b490ff42 RB |
73 | /* |
74 | * Give us a fighting chance of running if execution beings at the | |
70342287 | 75 | * kernel load address. This is needed because this platform does |
b490ff42 RB |
76 | * not have a ELF loader yet. |
77 | */ | |
ba820c5c RB |
78 | FEXPORT(__kernel_entry) |
79 | j kernel_entry | |
f6e2373a | 80 | #endif |
1da177e4 | 81 | |
a055917e | 82 | __REF |
396a2ae0 | 83 | |
1da177e4 | 84 | NESTED(kernel_entry, 16, sp) # kernel entry point |
1da177e4 | 85 | |
7e35952b RB |
86 | kernel_entry_setup # cpu specific setup |
87 | ||
88 | setup_c0_status_pri | |
1da177e4 | 89 | |
15ad838d TB |
90 | /* We might not get launched at the address the kernel is linked to, |
91 | so we jump there. */ | |
92 | PTR_LA t0, 0f | |
93 | jr t0 | |
94 | 0: | |
1da177e4 | 95 | |
1da8f179 JG |
96 | #ifdef CONFIG_MIPS_RAW_APPENDED_DTB |
97 | PTR_LA t0, __appended_dtb | |
98 | ||
99 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
100 | li t1, 0xd00dfeed | |
101 | #else | |
102 | li t1, 0xedfe0dd0 | |
103 | #endif | |
104 | lw t2, (t0) | |
105 | bne t1, t2, not_found | |
106 | nop | |
107 | ||
108 | move a1, t0 | |
109 | PTR_LI a0, -2 | |
110 | not_found: | |
111 | #endif | |
1da177e4 LT |
112 | PTR_LA t0, __bss_start # clear .bss |
113 | LONG_S zero, (t0) | |
114 | PTR_LA t1, __bss_stop - LONGSIZE | |
115 | 1: | |
116 | PTR_ADDIU t0, LONGSIZE | |
117 | LONG_S zero, (t0) | |
118 | bne t0, t1, 1b | |
119 | ||
120 | LONG_S a0, fw_arg0 # firmware arguments | |
121 | LONG_S a1, fw_arg1 | |
122 | LONG_S a2, fw_arg2 | |
123 | LONG_S a3, fw_arg3 | |
124 | ||
1b3a6e97 | 125 | MTC0 zero, CP0_CONTEXT # clear context register |
1da177e4 | 126 | PTR_LA $28, init_thread_union |
484889fc DD |
127 | /* Set the SP after an empty pt_regs. */ |
128 | PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE | |
242954b5 | 129 | PTR_ADDU sp, $28 |
c2ea1d56 | 130 | back_to_back_c0_hazard |
1da177e4 LT |
131 | set_saved_sp sp, t0, t1 |
132 | PTR_SUBU sp, 4 * SZREG # init stack pointer | |
133 | ||
af09ab5e MR |
134 | #ifdef CONFIG_RELOCATABLE |
135 | /* Copy kernel and apply the relocations */ | |
136 | jal relocate_kernel | |
137 | ||
138 | /* Repoint the sp into the new kernel image */ | |
139 | PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE | |
140 | PTR_ADDU sp, $28 | |
141 | set_saved_sp sp, t0, t1 | |
142 | PTR_SUBU sp, 4 * SZREG # init stack pointer | |
143 | ||
144 | /* | |
145 | * relocate_kernel returns the entry point either | |
146 | * in the relocated kernel or the original if for | |
147 | * some reason relocation failed - jump there now | |
148 | * with instruction hazard barrier because of the | |
149 | * newly sync'd icache. | |
150 | */ | |
151 | jr.hb v0 | |
152 | #else | |
1da177e4 | 153 | j start_kernel |
af09ab5e | 154 | #endif |
1da177e4 LT |
155 | END(kernel_entry) |
156 | ||
157 | #ifdef CONFIG_SMP | |
158 | /* | |
70342287 | 159 | * SMP slave cpus entry point. Board specific code for bootstrap calls this |
1da177e4 LT |
160 | * function after setting up the stack and gp registers. |
161 | */ | |
162 | NESTED(smp_bootstrap, 16, sp) | |
7e35952b | 163 | smp_slave_setup |
d0ba3544 | 164 | setup_c0_status_sec |
1da177e4 LT |
165 | j start_secondary |
166 | END(smp_bootstrap) | |
167 | #endif /* CONFIG_SMP */ |