Commit | Line | Data |
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d865bea4 RB |
1 | /* |
2 | * i8253.c 8253/PIT functions | |
3 | * | |
4 | */ | |
5 | #include <linux/clockchips.h> | |
6 | #include <linux/init.h> | |
7 | #include <linux/interrupt.h> | |
8 | #include <linux/jiffies.h> | |
9 | #include <linux/module.h> | |
631330f5 | 10 | #include <linux/smp.h> |
d865bea4 | 11 | #include <linux/spinlock.h> |
ca4d3e67 | 12 | #include <linux/irq.h> |
d865bea4 RB |
13 | |
14 | #include <asm/delay.h> | |
15 | #include <asm/i8253.h> | |
16 | #include <asm/io.h> | |
dd3db6eb | 17 | #include <asm/time.h> |
d865bea4 | 18 | |
ced918eb | 19 | DEFINE_RAW_SPINLOCK(i8253_lock); |
a05e623f | 20 | EXPORT_SYMBOL(i8253_lock); |
d865bea4 RB |
21 | |
22 | /* | |
23 | * Initialize the PIT timer. | |
24 | * | |
25 | * This is also called after resume to bring the PIT into operation again. | |
26 | */ | |
27 | static void init_pit_timer(enum clock_event_mode mode, | |
28 | struct clock_event_device *evt) | |
29 | { | |
ced918eb | 30 | raw_spin_lock(&i8253_lock); |
d865bea4 RB |
31 | |
32 | switch(mode) { | |
33 | case CLOCK_EVT_MODE_PERIODIC: | |
34 | /* binary, mode 2, LSB/MSB, ch 0 */ | |
35 | outb_p(0x34, PIT_MODE); | |
36 | outb_p(LATCH & 0xff , PIT_CH0); /* LSB */ | |
37 | outb(LATCH >> 8 , PIT_CH0); /* MSB */ | |
38 | break; | |
39 | ||
40 | case CLOCK_EVT_MODE_SHUTDOWN: | |
41 | case CLOCK_EVT_MODE_UNUSED: | |
42 | if (evt->mode == CLOCK_EVT_MODE_PERIODIC || | |
43 | evt->mode == CLOCK_EVT_MODE_ONESHOT) { | |
44 | outb_p(0x30, PIT_MODE); | |
45 | outb_p(0, PIT_CH0); | |
46 | outb_p(0, PIT_CH0); | |
47 | } | |
48 | break; | |
49 | ||
50 | case CLOCK_EVT_MODE_ONESHOT: | |
51 | /* One shot setup */ | |
52 | outb_p(0x38, PIT_MODE); | |
53 | break; | |
54 | ||
55 | case CLOCK_EVT_MODE_RESUME: | |
56 | /* Nothing to do here */ | |
57 | break; | |
58 | } | |
ced918eb | 59 | raw_spin_unlock(&i8253_lock); |
d865bea4 RB |
60 | } |
61 | ||
62 | /* | |
63 | * Program the next event in oneshot mode | |
64 | * | |
65 | * Delta is given in PIT ticks | |
66 | */ | |
67 | static int pit_next_event(unsigned long delta, struct clock_event_device *evt) | |
68 | { | |
ced918eb | 69 | raw_spin_lock(&i8253_lock); |
d865bea4 RB |
70 | outb_p(delta & 0xff , PIT_CH0); /* LSB */ |
71 | outb(delta >> 8 , PIT_CH0); /* MSB */ | |
ced918eb | 72 | raw_spin_unlock(&i8253_lock); |
d865bea4 RB |
73 | |
74 | return 0; | |
75 | } | |
76 | ||
77 | /* | |
78 | * On UP the PIT can serve all of the possible timer functions. On SMP systems | |
79 | * it can be solely used for the global tick. | |
80 | * | |
81 | * The profiling and update capabilites are switched off once the local apic is | |
82 | * registered. This mechanism replaces the previous #ifdef LOCAL_APIC - | |
83 | * !using_apic_timer decisions in do_timer_interrupt_hook() | |
84 | */ | |
1ea6428c | 85 | static struct clock_event_device pit_clockevent = { |
d865bea4 RB |
86 | .name = "pit", |
87 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
88 | .set_mode = init_pit_timer, | |
89 | .set_next_event = pit_next_event, | |
d865bea4 RB |
90 | .irq = 0, |
91 | }; | |
92 | ||
dd3db6eb | 93 | static irqreturn_t timer_interrupt(int irq, void *dev_id) |
d865bea4 RB |
94 | { |
95 | pit_clockevent.event_handler(&pit_clockevent); | |
96 | ||
97 | return IRQ_HANDLED; | |
98 | } | |
99 | ||
100 | static struct irqaction irq0 = { | |
101 | .handler = timer_interrupt, | |
f45e5183 | 102 | .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER, |
d865bea4 RB |
103 | .name = "timer" |
104 | }; | |
105 | ||
106 | /* | |
107 | * Initialize the conversion factor and the min/max deltas of the clock event | |
108 | * structure and register the clock event source with the framework. | |
109 | */ | |
110 | void __init setup_pit_timer(void) | |
111 | { | |
dd3db6eb RB |
112 | struct clock_event_device *cd = &pit_clockevent; |
113 | unsigned int cpu = smp_processor_id(); | |
114 | ||
d865bea4 RB |
115 | /* |
116 | * Start pit with the boot cpu mask and make it global after the | |
117 | * IO_APIC has been initialized. | |
118 | */ | |
320ab2b0 | 119 | cd->cpumask = cpumask_of(cpu); |
dd3db6eb RB |
120 | clockevent_set_clock(cd, CLOCK_TICK_RATE); |
121 | cd->max_delta_ns = clockevent_delta2ns(0x7FFF, cd); | |
122 | cd->min_delta_ns = clockevent_delta2ns(0xF, cd); | |
123 | clockevents_register_device(cd); | |
124 | ||
d865bea4 RB |
125 | setup_irq(0, &irq0); |
126 | } | |
127 | ||
128 | /* | |
129 | * Since the PIT overflows every tick, its not very useful | |
130 | * to just read by itself. So use jiffies to emulate a free | |
131 | * running counter: | |
132 | */ | |
8e19608e | 133 | static cycle_t pit_read(struct clocksource *cs) |
d865bea4 RB |
134 | { |
135 | unsigned long flags; | |
136 | int count; | |
137 | u32 jifs; | |
138 | static int old_count; | |
139 | static u32 old_jifs; | |
140 | ||
ced918eb | 141 | raw_spin_lock_irqsave(&i8253_lock, flags); |
d865bea4 RB |
142 | /* |
143 | * Although our caller may have the read side of xtime_lock, | |
144 | * this is now a seqlock, and we are cheating in this routine | |
145 | * by having side effects on state that we cannot undo if | |
146 | * there is a collision on the seqlock and our caller has to | |
147 | * retry. (Namely, old_jifs and old_count.) So we must treat | |
148 | * jiffies as volatile despite the lock. We read jiffies | |
149 | * before latching the timer count to guarantee that although | |
150 | * the jiffies value might be older than the count (that is, | |
151 | * the counter may underflow between the last point where | |
152 | * jiffies was incremented and the point where we latch the | |
153 | * count), it cannot be newer. | |
154 | */ | |
155 | jifs = jiffies; | |
156 | outb_p(0x00, PIT_MODE); /* latch the count ASAP */ | |
157 | count = inb_p(PIT_CH0); /* read the latched count */ | |
158 | count |= inb_p(PIT_CH0) << 8; | |
159 | ||
160 | /* VIA686a test code... reset the latch if count > max + 1 */ | |
161 | if (count > LATCH) { | |
162 | outb_p(0x34, PIT_MODE); | |
163 | outb_p(LATCH & 0xff, PIT_CH0); | |
164 | outb(LATCH >> 8, PIT_CH0); | |
165 | count = LATCH - 1; | |
166 | } | |
167 | ||
168 | /* | |
169 | * It's possible for count to appear to go the wrong way for a | |
170 | * couple of reasons: | |
171 | * | |
172 | * 1. The timer counter underflows, but we haven't handled the | |
173 | * resulting interrupt and incremented jiffies yet. | |
174 | * 2. Hardware problem with the timer, not giving us continuous time, | |
175 | * the counter does small "jumps" upwards on some Pentium systems, | |
176 | * (see c't 95/10 page 335 for Neptun bug.) | |
177 | * | |
178 | * Previous attempts to handle these cases intelligently were | |
179 | * buggy, so we just do the simple thing now. | |
180 | */ | |
181 | if (count > old_count && jifs == old_jifs) { | |
182 | count = old_count; | |
183 | } | |
184 | old_count = count; | |
185 | old_jifs = jifs; | |
186 | ||
ced918eb | 187 | raw_spin_unlock_irqrestore(&i8253_lock, flags); |
d865bea4 RB |
188 | |
189 | count = (LATCH - 1) - count; | |
190 | ||
191 | return (cycle_t)(jifs * LATCH) + count; | |
192 | } | |
193 | ||
194 | static struct clocksource clocksource_pit = { | |
195 | .name = "pit", | |
196 | .rating = 110, | |
197 | .read = pit_read, | |
198 | .mask = CLOCKSOURCE_MASK(32), | |
d865bea4 RB |
199 | }; |
200 | ||
201 | static int __init init_pit_clocksource(void) | |
202 | { | |
203 | if (num_possible_cpus() > 1) /* PIT does not scale! */ | |
204 | return 0; | |
205 | ||
75c4fd8c | 206 | return clocksource_register_hz(&clocksource_pit, CLOCK_TICK_RATE); |
d865bea4 RB |
207 | } |
208 | arch_initcall(init_pit_clocksource); |