[deliverable/linux.git] / arch / mips / kernel / i8259.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Code to handle x86 style IRQs plus some generic interrupt stuff.
 *
 * Copyright (C) 1992 Linus Torvalds
 * Copyright (C) 1994 - 2000 Ralf Baechle
 */
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/syscore_ops.h>
#include <linux/irq.h>

#include <asm/i8259.h>
#include <asm/io.h>

/*
 * This is the 'legacy' 8259A Programmable Interrupt Controller,
 * present in the majority of PC/AT boxes.
 * plus some generic x86 specific things if generic specifics makes
 * any sense at all.
 * this file should become arch/i386/kernel/irq.c when the old irq.c
 * moves to arch independent land
 */

static int i8259A_auto_eoi = -1;
DEFINE_RAW_SPINLOCK(i8259A_lock);
static void disable_8259A_irq(struct irq_data *d);
static void enable_8259A_irq(struct irq_data *d);
static void mask_and_ack_8259A(struct irq_data *d);
static void init_8259A(int auto_eoi);

static struct irq_chip i8259A_chip = {
	.name			= "XT-PIC",
	.irq_mask		= disable_8259A_irq,
	.irq_disable		= disable_8259A_irq,
	.irq_unmask		= enable_8259A_irq,
	.irq_mask_ack		= mask_and_ack_8259A,
};

/*
 * 8259A PIC functions to handle ISA devices:
 */

/*
 * This contains the irq mask for both 8259A irq controllers,
 */
static unsigned int cached_irq_mask = 0xffff;

#define cached_master_mask	(cached_irq_mask)
#define cached_slave_mask	(cached_irq_mask >> 8)

static void disable_8259A_irq(struct irq_data *d)
{
	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
	unsigned long flags;

	mask = 1 << irq;
	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask |= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void enable_8259A_irq(struct irq_data *d)
{
	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
	unsigned long flags;

	mask = ~(1 << irq);
	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask &= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

int i8259A_irq_pending(unsigned int irq)
{
	unsigned int mask;
	unsigned long flags;
	int ret;

	irq -= I8259A_IRQ_BASE;
	mask = 1 << irq;
	raw_spin_lock_irqsave(&i8259A_lock, flags);
	if (irq < 8)
		ret = inb(PIC_MASTER_CMD) & mask;
	else
		ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);

	return ret;
}

void make_8259A_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
	enable_irq(irq);
}

/*
 * This function assumes to be called rarely. Switching between
 * 8259A registers is slow.
 * This has to be protected by the irq controller spinlock
 * before being called.
 */
static inline int i8259A_irq_real(unsigned int irq)
{
	int value;
	int irqmask = 1 << irq;

	if (irq < 8) {
		outb(0x0B, PIC_MASTER_CMD);	/* ISR register */
		value = inb(PIC_MASTER_CMD) & irqmask;
		outb(0x0A, PIC_MASTER_CMD);	/* back to the IRR register */
		return value;
	}
	outb(0x0B, PIC_SLAVE_CMD);	/* ISR register */
	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	outb(0x0A, PIC_SLAVE_CMD);	/* back to the IRR register */
	return value;
}

/*
 * Careful! The 8259A is a fragile beast, it pretty
 * much _has_ to be done exactly like this (mask it
 * first, _then_ send the EOI, and the order of EOI
 * to the two 8259s is important!
 */
static void mask_and_ack_8259A(struct irq_data *d)
{
	unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE;
	unsigned long flags;

	irqmask = 1 << irq;
	raw_spin_lock_irqsave(&i8259A_lock, flags);
	/*
	 * Lightweight spurious IRQ detection. We do not want
	 * to overdo spurious IRQ handling - it's usually a sign
	 * of hardware problems, so we only do the checks we can
	 * do without slowing down good hardware unnecessarily.
	 *
	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
	 * usually resulting from the 8259A-1|2 PICs) occur
	 * even if the IRQ is masked in the 8259A. Thus we
	 * can check spurious 8259A IRQs without doing the
	 * quite slow i8259A_irq_real() call for every IRQ.
	 * This does not cover 100% of spurious interrupts,
	 * but should be enough to warn the user that there
	 * is something bad going on ...
	 */
	if (cached_irq_mask & irqmask)
		goto spurious_8259A_irq;
	cached_irq_mask |= irqmask;

handle_real_irq:
	if (irq & 8) {
		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_slave_mask, PIC_SLAVE_IMR);
		outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
		outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
	} else {
		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_master_mask, PIC_MASTER_IMR);
		outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
	}
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	return;

spurious_8259A_irq:
	/*
	 * this is the slow path - should happen rarely.
	 */
	if (i8259A_irq_real(irq))
		/*
		 * oops, the IRQ _is_ in service according to the
		 * 8259A - not spurious, go handle it.
		 */
		goto handle_real_irq;

	{
		static int spurious_irq_mask;
		/*
		 * At this point we can be sure the IRQ is spurious,
		 * lets ACK and report it. [once per IRQ]
		 */
		if (!(spurious_irq_mask & irqmask)) {
			printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
			spurious_irq_mask |= irqmask;
		}
		atomic_inc(&irq_err_count);
		/*
		 * Theoretically we do not have to handle this IRQ,
		 * but in Linux this does not cause problems and is
		 * simpler for us.
		 */
		goto handle_real_irq;
	}
}

static void i8259A_resume(void)
{
	if (i8259A_auto_eoi >= 0)
		init_8259A(i8259A_auto_eoi);
}

static void i8259A_shutdown(void)
{
	/* Put the i8259A into a quiescent state that
	 * the kernel initialization code can get it
	 * out of.
	 */
	if (i8259A_auto_eoi >= 0) {
		outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
		outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */
	}
}

static struct syscore_ops i8259_syscore_ops = {
	.resume = i8259A_resume,
	.shutdown = i8259A_shutdown,
};

static int __init i8259A_init_sysfs(void)
{
	register_syscore_ops(&i8259_syscore_ops);
	return 0;
}

device_initcall(i8259A_init_sysfs);

static void init_8259A(int auto_eoi)
{
	unsigned long flags;

	i8259A_auto_eoi = auto_eoi;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	/*
	 * outb_p - this has to work on a wide range of PC hardware.
	 */
	outb_p(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */
	outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR);	/* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
	outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);	/* 8259A-1 (the master) has a slave on IR2 */
	if (auto_eoi)	/* master does Auto EOI */
		outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
	else		/* master expects normal EOI */
		outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

	outb_p(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */
	outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR);	/* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);	/* 8259A-2 is a slave on master's IR2 */
	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
	if (auto_eoi)
		/*
		 * In AEOI mode we just have to mask the interrupt
		 * when acking.
		 */
		i8259A_chip.irq_mask_ack = disable_8259A_irq;
	else
		i8259A_chip.irq_mask_ack = mask_and_ack_8259A;

	udelay(100);		/* wait for 8259A to initialize */

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

/*
 * IRQ2 is cascade interrupt to second interrupt controller
 */
static struct irqaction irq2 = {
	.handler = no_action,
	.name = "cascade",
	.flags = IRQF_NO_THREAD,
};

static struct resource pic1_io_resource = {
	.name = "pic1",
	.start = PIC_MASTER_CMD,
	.end = PIC_MASTER_IMR,
	.flags = IORESOURCE_BUSY
};

static struct resource pic2_io_resource = {
	.name = "pic2",
	.start = PIC_SLAVE_CMD,
	.end = PIC_SLAVE_IMR,
	.flags = IORESOURCE_BUSY
};

/*
 * On systems with i8259-style interrupt controllers we assume for
 * driver compatibility reasons interrupts 0 - 15 to be the i8259
 * interrupts even if the hardware uses a different interrupt numbering.
 */
void __init init_i8259_irqs(void)
{
	int i;

	insert_resource(&ioport_resource, &pic1_io_resource);
	insert_resource(&ioport_resource, &pic2_io_resource);

	init_8259A(0);

	for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
		irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq);
		irq_set_probe(i);
	}

	setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Code to handle x86 style IRQs plus some generic interrupt stuff.
	7	*
	8	* Copyright (C) 1992 Linus Torvalds
	9	* Copyright (C) 1994 - 2000 Ralf Baechle
	10	*/
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13	#include <linux/ioport.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/kernel.h>
	16	#include <linux/spinlock.h>
84652e83	17	#include <linux/syscore_ops.h>
ca4d3e67	18	#include <linux/irq.h>
1da177e4 LT	19
	20	#include <asm/i8259.h>
	21	#include <asm/io.h>
	22
1da177e4 LT	23	/*
	24	* This is the 'legacy' 8259A Programmable Interrupt Controller,
	25	* present in the majority of PC/AT boxes.
	26	* plus some generic x86 specific things if generic specifics makes
	27	* any sense at all.
	28	* this file should become arch/i386/kernel/irq.c when the old irq.c
	29	* moves to arch independent land
	30	*/
	31
a0be2f79	32	static int i8259A_auto_eoi = -1;
89650870	33	DEFINE_RAW_SPINLOCK(i8259A_lock);
7c8d948f TG	34	static void disable_8259A_irq(struct irq_data *d);
	35	static void enable_8259A_irq(struct irq_data *d);
	36	static void mask_and_ack_8259A(struct irq_data *d);
d80c1c0b	37	static void init_8259A(int auto_eoi);
1da177e4	38
2cafe978	39	static struct irq_chip i8259A_chip = {
7c8d948f TG	40	.name = "XT-PIC",
	41	.irq_mask = disable_8259A_irq,
	42	.irq_disable = disable_8259A_irq,
	43	.irq_unmask = enable_8259A_irq,
	44	.irq_mask_ack = mask_and_ack_8259A,
1da177e4 LT	45	};
	46
	47	/*
	48	* 8259A PIC functions to handle ISA devices:
	49	*/
	50
	51	/*
	52	* This contains the irq mask for both 8259A irq controllers,
	53	*/
	54	static unsigned int cached_irq_mask = 0xffff;
	55
2cafe978 AN	56	#define cached_master_mask (cached_irq_mask)
2cafe978 AN	57	#define cached_slave_mask (cached_irq_mask >> 8)
1da177e4	58
7c8d948f	59	static void disable_8259A_irq(struct irq_data *d)
1da177e4	60	{
7c8d948f	61	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
1da177e4 LT	62	unsigned long flags;
1da177e4 LT	63
2fa7937b	64	mask = 1 << irq;
89650870	65	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4 LT	66	cached_irq_mask \|= mask;
1da177e4 LT	67	if (irq & 8)
2cafe978	68	outb(cached_slave_mask, PIC_SLAVE_IMR);
1da177e4	69	else
2cafe978	70	outb(cached_master_mask, PIC_MASTER_IMR);
89650870	71	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	72	}
1da177e4 LT	73
7c8d948f	74	static void enable_8259A_irq(struct irq_data *d)
1da177e4	75	{
7c8d948f	76	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
1da177e4 LT	77	unsigned long flags;
1da177e4 LT	78
2fa7937b	79	mask = ~(1 << irq);
89650870	80	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4 LT	81	cached_irq_mask &= mask;
1da177e4 LT	82	if (irq & 8)
2cafe978	83	outb(cached_slave_mask, PIC_SLAVE_IMR);
1da177e4	84	else
2cafe978	85	outb(cached_master_mask, PIC_MASTER_IMR);
89650870	86	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	87	}
	88
	89	int i8259A_irq_pending(unsigned int irq)
	90	{
2fa7937b	91	unsigned int mask;
1da177e4 LT	92	unsigned long flags;
	93	int ret;
	94
2fa7937b AN	95	irq -= I8259A_IRQ_BASE;
2fa7937b AN	96	mask = 1 << irq;
89650870	97	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4	98	if (irq < 8)
2cafe978	99	ret = inb(PIC_MASTER_CMD) & mask;
1da177e4	100	else
2cafe978	101	ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
89650870	102	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	103
	104	return ret;
	105	}
	106
	107	void make_8259A_irq(unsigned int irq)
	108	{
	109	disable_irq_nosync(irq);
e4ec7989	110	irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
1da177e4 LT	111	enable_irq(irq);
	112	}
	113
	114	/*
	115	* This function assumes to be called rarely. Switching between
	116	* 8259A registers is slow.
	117	* This has to be protected by the irq controller spinlock
	118	* before being called.
	119	*/
	120	static inline int i8259A_irq_real(unsigned int irq)
	121	{
	122	int value;
	123	int irqmask = 1 << irq;
	124
	125	if (irq < 8) {
21a151d8	126	outb(0x0B, PIC_MASTER_CMD); /* ISR register */
2cafe978	127	value = inb(PIC_MASTER_CMD) & irqmask;
21a151d8	128	outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
1da177e4 LT	129	return value;
1da177e4 LT	130	}
21a151d8	131	outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
2cafe978	132	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
21a151d8	133	outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
1da177e4 LT	134	return value;
	135	}
	136
	137	/*
	138	* Careful! The 8259A is a fragile beast, it pretty
	139	* much _has_ to be done exactly like this (mask it
	140	* first, _then_ send the EOI, and the order of EOI
	141	* to the two 8259s is important!
	142	*/
7c8d948f	143	static void mask_and_ack_8259A(struct irq_data *d)
1da177e4	144	{
7c8d948f	145	unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE;
1da177e4 LT	146	unsigned long flags;
1da177e4 LT	147
2fa7937b	148	irqmask = 1 << irq;
89650870	149	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4	150	/*
2cafe978 AN	151	* Lightweight spurious IRQ detection. We do not want
	152	* to overdo spurious IRQ handling - it's usually a sign
	153	* of hardware problems, so we only do the checks we can
	154	* do without slowing down good hardware unnecessarily.
1da177e4	155	*
2cafe978 AN	156	* Note that IRQ7 and IRQ15 (the two spurious IRQs
	157	* usually resulting from the 8259A-1\|2 PICs) occur
	158	* even if the IRQ is masked in the 8259A. Thus we
	159	* can check spurious 8259A IRQs without doing the
	160	* quite slow i8259A_irq_real() call for every IRQ.
	161	* This does not cover 100% of spurious interrupts,
	162	* but should be enough to warn the user that there
	163	* is something bad going on ...
1da177e4 LT	164	*/
	165	if (cached_irq_mask & irqmask)
	166	goto spurious_8259A_irq;
	167	cached_irq_mask \|= irqmask;
	168
	169	handle_real_irq:
	170	if (irq & 8) {
2cafe978 AN	171	inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
2cafe978 AN	172	outb(cached_slave_mask, PIC_SLAVE_IMR);
21a151d8 RB	173	outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
21a151d8 RB	174	outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
1da177e4	175	} else {
2cafe978 AN	176	inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
2cafe978 AN	177	outb(cached_master_mask, PIC_MASTER_IMR);
70342287	178	outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
1da177e4	179	}
89650870	180	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	181	return;
	182
	183	spurious_8259A_irq:
	184	/*
	185	* this is the slow path - should happen rarely.
	186	*/
	187	if (i8259A_irq_real(irq))
	188	/*
	189	* oops, the IRQ _is_ in service according to the
	190	* 8259A - not spurious, go handle it.
	191	*/
	192	goto handle_real_irq;
	193
	194	{
2cafe978	195	static int spurious_irq_mask;
1da177e4 LT	196	/*
	197	* At this point we can be sure the IRQ is spurious,
	198	* lets ACK and report it. [once per IRQ]
	199	*/
	200	if (!(spurious_irq_mask & irqmask)) {
	201	printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
	202	spurious_irq_mask \|= irqmask;
	203	}
	204	atomic_inc(&irq_err_count);
	205	/*
	206	* Theoretically we do not have to handle this IRQ,
	207	* but in Linux this does not cause problems and is
	208	* simpler for us.
	209	*/
	210	goto handle_real_irq;
	211	}
	212	}
	213
84652e83	214	static void i8259A_resume(void)
1da177e4	215	{
a0be2f79 AN	216	if (i8259A_auto_eoi >= 0)
a0be2f79 AN	217	init_8259A(i8259A_auto_eoi);
2cafe978 AN	218	}
2cafe978 AN	219
84652e83	220	static void i8259A_shutdown(void)
2cafe978 AN	221	{
	222	/* Put the i8259A into a quiescent state that
	223	* the kernel initialization code can get it
	224	* out of.
	225	*/
a0be2f79 AN	226	if (i8259A_auto_eoi >= 0) {
a0be2f79 AN	227	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
fe0b030c	228	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
a0be2f79	229	}
1da177e4 LT	230	}
1da177e4 LT	231
84652e83	232	static struct syscore_ops i8259_syscore_ops = {
1da177e4	233	.resume = i8259A_resume,
2cafe978	234	.shutdown = i8259A_shutdown,
1da177e4 LT	235	};
1da177e4 LT	236
1da177e4 LT	237	static int __init i8259A_init_sysfs(void)
1da177e4 LT	238	{
84652e83 RW	239	register_syscore_ops(&i8259_syscore_ops);
84652e83 RW	240	return 0;
1da177e4 LT	241	}
	242
	243	device_initcall(i8259A_init_sysfs);
	244
d80c1c0b	245	static void init_8259A(int auto_eoi)
1da177e4 LT	246	{
	247	unsigned long flags;
	248
2cafe978 AN	249	i8259A_auto_eoi = auto_eoi;
2cafe978 AN	250
89650870	251	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4	252
2cafe978 AN	253	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
2cafe978 AN	254	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
1da177e4 LT	255
	256	/*
	257	* outb_p - this has to work on a wide range of PC hardware.
	258	*/
2cafe978 AN	259	outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
	260	outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
	261	outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
	262	if (auto_eoi) /* master does Auto EOI */
	263	outb_p(MASTER_ICW4_DEFAULT \| PIC_ICW4_AEOI, PIC_MASTER_IMR);
	264	else /* master expects normal EOI */
	265	outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
	266
	267	outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
	268	outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
	269	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
	270	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
1da177e4 LT	271	if (auto_eoi)
1da177e4 LT	272	/*
2cafe978	273	* In AEOI mode we just have to mask the interrupt
1da177e4 LT	274	* when acking.
1da177e4 LT	275	*/
7c8d948f	276	i8259A_chip.irq_mask_ack = disable_8259A_irq;
1da177e4	277	else
7c8d948f	278	i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
1da177e4 LT	279
	280	udelay(100); /* wait for 8259A to initialize */
	281
2cafe978 AN	282	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
2cafe978 AN	283	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
1da177e4	284
89650870	285	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	286	}
	287
	288	/*
	289	* IRQ2 is cascade interrupt to second interrupt controller
	290	*/
	291	static struct irqaction irq2 = {
4e45171c	292	.handler = no_action,
4e45171c	293	.name = "cascade",
5c22cd40	294	.flags = IRQF_NO_THREAD,
1da177e4 LT	295	};
	296
	297	static struct resource pic1_io_resource = {
2cafe978 AN	298	.name = "pic1",
	299	.start = PIC_MASTER_CMD,
	300	.end = PIC_MASTER_IMR,
	301	.flags = IORESOURCE_BUSY
1da177e4 LT	302	};
	303
	304	static struct resource pic2_io_resource = {
2cafe978 AN	305	.name = "pic2",
	306	.start = PIC_SLAVE_CMD,
	307	.end = PIC_SLAVE_IMR,
	308	.flags = IORESOURCE_BUSY
1da177e4 LT	309	};
	310
	311	/*
	312	* On systems with i8259-style interrupt controllers we assume for
28a7879d	313	* driver compatibility reasons interrupts 0 - 15 to be the i8259
1da177e4 LT	314	* interrupts even if the hardware uses a different interrupt numbering.
1da177e4 LT	315	*/
49a89efb	316	void __init init_i8259_irqs(void)
1da177e4 LT	317	{
	318	int i;
	319
639702bd TB	320	insert_resource(&ioport_resource, &pic1_io_resource);
639702bd TB	321	insert_resource(&ioport_resource, &pic2_io_resource);
1da177e4 LT	322
	323	init_8259A(0);
	324
24649c00	325	for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
e4ec7989 TG	326	irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq);
e4ec7989 TG	327	irq_set_probe(i);
24649c00	328	}
1da177e4	329
2fa7937b	330	setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
1da177e4	331	}