[deliverable/linux.git] / arch / mips / kernel / irq-msc01.c

/*
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Copyright (c) 2004 MIPS Inc
 * Author: chris@mips.com
 *
 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
 */
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/msc01_ic.h>
#include <asm/traps.h>

static unsigned long _icctrl_msc;
#define MSC01_IC_REG_BASE	_icctrl_msc

#define MSCIC_WRITE(reg, data)	do { *(volatile u32 *)(reg) = data; } while (0)
#define MSCIC_READ(reg, data)	do { data = *(volatile u32 *)(reg); } while (0)

static unsigned int irq_base;

/* mask off an interrupt */
static inline void mask_msc_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	if (irq < (irq_base + 32))
		MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
	else
		MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
}

/* unmask an interrupt */
static inline void unmask_msc_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	if (irq < (irq_base + 32))
		MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
	else
		MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
}

/*
 * Masks and ACKs an IRQ
 */
static void level_mask_and_ack_msc_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	mask_msc_irq(d);
	if (!cpu_has_veic)
		MSCIC_WRITE(MSC01_IC_EOI, 0);
	/* This actually needs to be a call into platform code */
	smtc_im_ack_irq(irq);
}

/*
 * Masks and ACKs an IRQ
 */
static void edge_mask_and_ack_msc_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	mask_msc_irq(d);
	if (!cpu_has_veic)
		MSCIC_WRITE(MSC01_IC_EOI, 0);
	else {
		u32 r;
		MSCIC_READ(MSC01_IC_SUP+irq*8, r);
		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
	}
	smtc_im_ack_irq(irq);
}

/*
 * Interrupt handler for interrupts coming from SOC-it.
 */
void ll_msc_irq(void)
{
	unsigned int irq;

	/* read the interrupt vector register */
	MSCIC_READ(MSC01_IC_VEC, irq);
	if (irq < 64)
		do_IRQ(irq + irq_base);
	else {
		/* Ignore spurious interrupt */
	}
}

static void msc_bind_eic_interrupt(int irq, int set)
{
	MSCIC_WRITE(MSC01_IC_RAMW,
		    (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
}

static struct irq_chip msc_levelirq_type = {
	.name = "SOC-it-Level",
	.irq_ack = level_mask_and_ack_msc_irq,
	.irq_mask = mask_msc_irq,
	.irq_mask_ack = level_mask_and_ack_msc_irq,
	.irq_unmask = unmask_msc_irq,
	.irq_eoi = unmask_msc_irq,
};

static struct irq_chip msc_edgeirq_type = {
	.name = "SOC-it-Edge",
	.irq_ack = edge_mask_and_ack_msc_irq,
	.irq_mask = mask_msc_irq,
	.irq_mask_ack = edge_mask_and_ack_msc_irq,
	.irq_unmask = unmask_msc_irq,
	.irq_eoi = unmask_msc_irq,
};


void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
{
	_icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);

	/* Reset interrupt controller - initialises all registers to 0 */
	MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);

	board_bind_eic_interrupt = &msc_bind_eic_interrupt;

	for (; nirq >= 0; nirq--, imp++) {
		int n = imp->im_irq;

		switch (imp->im_type) {
		case MSC01_IRQ_EDGE:
			irq_set_chip_and_handler_name(irqbase + n,
						      &msc_edgeirq_type,
						      handle_edge_irq,
						      "edge");
			if (cpu_has_veic)
				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
			else
				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
			break;
		case MSC01_IRQ_LEVEL:
			irq_set_chip_and_handler_name(irqbase + n,
						      &msc_levelirq_type,
						      handle_level_irq,
						      "level");
			if (cpu_has_veic)
				MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
			else
				MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
		}
	}

	irq_base = irqbase;

	MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT);	/* Enable interrupt generation */

}
Commit	Line	Data
1da177e4	1	/*
70342287 RB	2	* This program is free software; you can redistribute it and/or modify it
70342287 RB	3	* under the terms of the GNU General Public License as published by the
1da177e4 LT	4	* Free Software Foundation; either version 2 of the License, or (at your
1da177e4 LT	5	* option) any later version.
27f76819 RB	6	*
	7	* Copyright (c) 2004 MIPS Inc
	8	* Author: chris@mips.com
	9	*
	10	* Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
1da177e4	11	*/
1da177e4 LT	12	#include <linux/interrupt.h>
1da177e4 LT	13	#include <linux/kernel.h>
1da177e4 LT	14	#include <linux/sched.h>
	15	#include <linux/kernel_stat.h>
	16	#include <asm/io.h>
	17	#include <asm/irq.h>
	18	#include <asm/msc01_ic.h>
411ba7fc	19	#include <asm/traps.h>
1da177e4 LT	20
	21	static unsigned long _icctrl_msc;
	22	#define MSC01_IC_REG_BASE _icctrl_msc
	23
	24	#define MSCIC_WRITE(reg, data) do { (volatile u32 )(reg) = data; } while (0)
	25	#define MSCIC_READ(reg, data) do { data = (volatile u32 )(reg); } while (0)
	26
	27	static unsigned int irq_base;
	28
	29	/* mask off an interrupt */
e15883da	30	static inline void mask_msc_irq(struct irq_data *d)
1da177e4	31	{
e15883da TG	32	unsigned int irq = d->irq;
e15883da TG	33
1da177e4 LT	34	if (irq < (irq_base + 32))
	35	MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
	36	else
	37	MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
	38	}
	39
	40	/* unmask an interrupt */
e15883da	41	static inline void unmask_msc_irq(struct irq_data *d)
1da177e4	42	{
e15883da TG	43	unsigned int irq = d->irq;
e15883da TG	44
1da177e4 LT	45	if (irq < (irq_base + 32))
	46	MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
	47	else
	48	MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
	49	}
	50
1da177e4 LT	51	/*
	52	* Masks and ACKs an IRQ
	53	*/
e15883da	54	static void level_mask_and_ack_msc_irq(struct irq_data *d)
1da177e4	55	{
e15883da TG	56	unsigned int irq = d->irq;
	57
	58	mask_msc_irq(d);
e01402b1	59	if (!cpu_has_veic)
1da177e4	60	MSCIC_WRITE(MSC01_IC_EOI, 0);
41c594ab	61	/* This actually needs to be a call into platform code */
1146fe30	62	smtc_im_ack_irq(irq);
1da177e4 LT	63	}
	64
	65	/*
	66	* Masks and ACKs an IRQ
	67	*/
e15883da	68	static void edge_mask_and_ack_msc_irq(struct irq_data *d)
1da177e4	69	{
e15883da TG	70	unsigned int irq = d->irq;
	71
	72	mask_msc_irq(d);
e01402b1	73	if (!cpu_has_veic)
1da177e4 LT	74	MSCIC_WRITE(MSC01_IC_EOI, 0);
	75	else {
	76	u32 r;
	77	MSCIC_READ(MSC01_IC_SUP+irq*8, r);
	78	MSCIC_WRITE(MSC01_IC_SUP+irq*8, r \| ~MSC01_IC_SUP_EDGE_BIT);
	79	MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
	80	}
1146fe30	81	smtc_im_ack_irq(irq);
1da177e4 LT	82	}
1da177e4 LT	83
1da177e4 LT	84	/*
	85	* Interrupt handler for interrupts coming from SOC-it.
	86	*/
937a8015	87	void ll_msc_irq(void)
1da177e4	88	{
70342287	89	unsigned int irq;
1da177e4 LT	90
	91	/* read the interrupt vector register */
	92	MSCIC_READ(MSC01_IC_VEC, irq);
	93	if (irq < 64)
937a8015	94	do_IRQ(irq + irq_base);
1da177e4 LT	95	else {
	96	/* Ignore spurious interrupt */
	97	}
	98	}
	99
411ba7fc	100	static void msc_bind_eic_interrupt(int irq, int set)
1da177e4 LT	101	{
	102	MSCIC_WRITE(MSC01_IC_RAMW,
	103	(irq<<MSC01_IC_RAMW_ADDR_SHF) \| (set<<MSC01_IC_RAMW_DATA_SHF));
	104	}
	105
411ba7fc	106	static struct irq_chip msc_levelirq_type = {
70d21cde	107	.name = "SOC-it-Level",
e15883da TG	108	.irq_ack = level_mask_and_ack_msc_irq,
	109	.irq_mask = mask_msc_irq,
	110	.irq_mask_ack = level_mask_and_ack_msc_irq,
	111	.irq_unmask = unmask_msc_irq,
	112	.irq_eoi = unmask_msc_irq,
1da177e4 LT	113	};
1da177e4 LT	114
411ba7fc	115	static struct irq_chip msc_edgeirq_type = {
70d21cde	116	.name = "SOC-it-Edge",
e15883da TG	117	.irq_ack = edge_mask_and_ack_msc_irq,
	118	.irq_mask = mask_msc_irq,
	119	.irq_mask_ack = edge_mask_and_ack_msc_irq,
	120	.irq_unmask = unmask_msc_irq,
	121	.irq_eoi = unmask_msc_irq,
1da177e4 LT	122	};
	123
	124
d725cf38	125	void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
1da177e4	126	{
49a89efb	127	_icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
1da177e4 LT	128
	129	/* Reset interrupt controller - initialises all registers to 0 */
	130	MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
	131
	132	board_bind_eic_interrupt = &msc_bind_eic_interrupt;
	133
	134	for (; nirq >= 0; nirq--, imp++) {
	135	int n = imp->im_irq;
	136
	137	switch (imp->im_type) {
	138	case MSC01_IRQ_EDGE:
e4ec7989 TG	139	irq_set_chip_and_handler_name(irqbase + n,
	140	&msc_edgeirq_type,
	141	handle_edge_irq,
	142	"edge");
e01402b1	143	if (cpu_has_veic)
1da177e4 LT	144	MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
	145	else
	146	MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT \| imp->im_lvl);
	147	break;
	148	case MSC01_IRQ_LEVEL:
e4ec7989 TG	149	irq_set_chip_and_handler_name(irqbase + n,
	150	&msc_levelirq_type,
	151	handle_level_irq,
	152	"level");
e01402b1	153	if (cpu_has_veic)
1da177e4 LT	154	MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
	155	else
	156	MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
	157	}
	158	}
	159
d725cf38	160	irq_base = irqbase;
1da177e4 LT	161
	162	MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
	163
	164	}