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1 | /* |
2 | * Copyright 2001 MontaVista Software Inc. | |
3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | |
4 | * | |
5 | * Copyright (C) 2001 Ralf Baechle | |
925ddb04 MR |
6 | * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. |
7 | * Author: Maciej W. Rozycki <macro@mips.com> | |
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8 | * |
9 | * This file define the irq handler for MIPS CPU interrupts. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | */ | |
16 | ||
17 | /* | |
18 | * Almost all MIPS CPUs define 8 interrupt sources. They are typically | |
19 | * level triggered (i.e., cannot be cleared from CPU; must be cleared from | |
20 | * device). The first two are software interrupts which we don't really | |
21 | * use or support. The last one is usually the CPU timer interrupt if | |
22 | * counter register is present or, for CPUs with an external FPU, by | |
23 | * convention it's the FPU exception interrupt. | |
24 | * | |
25 | * Don't even think about using this on SMP. You have been warned. | |
26 | * | |
27 | * This file exports one global function: | |
97dcb82d | 28 | * void mips_cpu_irq_init(void); |
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29 | */ |
30 | #include <linux/init.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/kernel.h> | |
33 | ||
34 | #include <asm/irq_cpu.h> | |
35 | #include <asm/mipsregs.h> | |
d03d0a57 | 36 | #include <asm/mipsmtregs.h> |
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37 | #include <asm/system.h> |
38 | ||
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39 | static inline void unmask_mips_irq(unsigned int irq) |
40 | { | |
97dcb82d | 41 | set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); |
569f75bd | 42 | irq_enable_hazard(); |
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43 | } |
44 | ||
45 | static inline void mask_mips_irq(unsigned int irq) | |
46 | { | |
97dcb82d | 47 | clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); |
569f75bd | 48 | irq_disable_hazard(); |
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49 | } |
50 | ||
94dee171 | 51 | static struct irq_chip mips_cpu_irq_controller = { |
70d21cde | 52 | .name = "MIPS", |
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53 | .ack = mask_mips_irq, |
54 | .mask = mask_mips_irq, | |
55 | .mask_ack = mask_mips_irq, | |
56 | .unmask = unmask_mips_irq, | |
1417836e | 57 | .eoi = unmask_mips_irq, |
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58 | }; |
59 | ||
d03d0a57 RB |
60 | /* |
61 | * Basically the same as above but taking care of all the MT stuff | |
62 | */ | |
63 | ||
64 | #define unmask_mips_mt_irq unmask_mips_irq | |
65 | #define mask_mips_mt_irq mask_mips_irq | |
d03d0a57 RB |
66 | |
67 | static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) | |
68 | { | |
69 | unsigned int vpflags = dvpe(); | |
70 | ||
97dcb82d | 71 | clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); |
d03d0a57 | 72 | evpe(vpflags); |
1603b5ac | 73 | unmask_mips_mt_irq(irq); |
d03d0a57 RB |
74 | |
75 | return 0; | |
76 | } | |
77 | ||
d03d0a57 RB |
78 | /* |
79 | * While we ack the interrupt interrupts are disabled and thus we don't need | |
80 | * to deal with concurrency issues. Same for mips_cpu_irq_end. | |
81 | */ | |
82 | static void mips_mt_cpu_irq_ack(unsigned int irq) | |
83 | { | |
84 | unsigned int vpflags = dvpe(); | |
97dcb82d | 85 | clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); |
d03d0a57 RB |
86 | evpe(vpflags); |
87 | mask_mips_mt_irq(irq); | |
88 | } | |
89 | ||
94dee171 | 90 | static struct irq_chip mips_mt_cpu_irq_controller = { |
70d21cde | 91 | .name = "MIPS", |
d03d0a57 | 92 | .startup = mips_mt_cpu_irq_startup, |
d03d0a57 | 93 | .ack = mips_mt_cpu_irq_ack, |
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94 | .mask = mask_mips_mt_irq, |
95 | .mask_ack = mips_mt_cpu_irq_ack, | |
96 | .unmask = unmask_mips_mt_irq, | |
1417836e | 97 | .eoi = unmask_mips_mt_irq, |
d03d0a57 | 98 | }; |
1da177e4 | 99 | |
97dcb82d | 100 | void __init mips_cpu_irq_init(void) |
1da177e4 | 101 | { |
97dcb82d | 102 | int irq_base = MIPS_CPU_IRQ_BASE; |
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103 | int i; |
104 | ||
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105 | /* Mask interrupts. */ |
106 | clear_c0_status(ST0_IM); | |
107 | clear_c0_cause(CAUSEF_IP); | |
108 | ||
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109 | /* |
110 | * Only MT is using the software interrupts currently, so we just | |
111 | * leave them uninitialized for other processors. | |
112 | */ | |
113 | if (cpu_has_mipsmt) | |
1603b5ac | 114 | for (i = irq_base; i < irq_base + 2; i++) |
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115 | set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller, |
116 | handle_percpu_irq); | |
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117 | |
118 | for (i = irq_base + 2; i < irq_base + 8; i++) | |
1417836e | 119 | set_irq_chip_and_handler(i, &mips_cpu_irq_controller, |
30e748a5 | 120 | handle_percpu_irq); |
1da177e4 | 121 | } |