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1 | /* |
2 | * Copyright (C) 2013 Imagination Technologies | |
3 | * Author: Paul Burton <paul.burton@imgtec.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | */ | |
10 | ||
11 | #include <linux/errno.h> | |
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12 | #include <linux/percpu.h> |
13 | #include <linux/spinlock.h> | |
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14 | |
15 | #include <asm/mips-cm.h> | |
16 | #include <asm/mips-cpc.h> | |
17 | ||
18 | void __iomem *mips_cpc_base; | |
19 | ||
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20 | static DEFINE_PER_CPU_ALIGNED(spinlock_t, cpc_core_lock); |
21 | ||
22 | static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags); | |
23 | ||
8dedde6b BH |
24 | /** |
25 | * mips_cpc_phys_base - retrieve the physical base address of the CPC | |
26 | * | |
27 | * This function returns the physical base address of the Cluster Power | |
28 | * Controller memory mapped registers, or 0 if no Cluster Power Controller | |
29 | * is present. | |
30 | */ | |
31 | static phys_addr_t mips_cpc_phys_base(void) | |
9c38cf44 | 32 | { |
391057d9 | 33 | unsigned long cpc_base; |
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34 | |
35 | if (!mips_cm_present()) | |
36 | return 0; | |
37 | ||
38 | if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK)) | |
39 | return 0; | |
40 | ||
41 | /* If the CPC is already enabled, leave it so */ | |
42 | cpc_base = read_gcr_cpc_base(); | |
43 | if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK) | |
44 | return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK; | |
45 | ||
46 | /* Otherwise, give it the default address & enable it */ | |
47 | cpc_base = mips_cpc_default_phys_base(); | |
48 | write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK); | |
49 | return cpc_base; | |
50 | } | |
51 | ||
52 | int mips_cpc_probe(void) | |
53 | { | |
15d45cce | 54 | phys_addr_t addr; |
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55 | unsigned cpu; |
56 | ||
57 | for_each_possible_cpu(cpu) | |
58 | spin_lock_init(&per_cpu(cpc_core_lock, cpu)); | |
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59 | |
60 | addr = mips_cpc_phys_base(); | |
61 | if (!addr) | |
62 | return -ENODEV; | |
63 | ||
64 | mips_cpc_base = ioremap_nocache(addr, 0x8000); | |
65 | if (!mips_cpc_base) | |
66 | return -ENXIO; | |
67 | ||
68 | return 0; | |
69 | } | |
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70 | |
71 | void mips_cpc_lock_other(unsigned int core) | |
72 | { | |
73 | unsigned curr_core; | |
74 | preempt_disable(); | |
75 | curr_core = current_cpu_data.core; | |
76 | spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core), | |
77 | per_cpu(cpc_core_lock_flags, curr_core)); | |
78 | write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF); | |
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79 | |
80 | /* | |
81 | * Ensure the core-other region reflects the appropriate core & | |
82 | * VP before any accesses to it occur. | |
83 | */ | |
84 | mb(); | |
76ae6584 PB |
85 | } |
86 | ||
87 | void mips_cpc_unlock_other(void) | |
88 | { | |
89 | unsigned curr_core = current_cpu_data.core; | |
90 | spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core), | |
91 | per_cpu(cpc_core_lock_flags, curr_core)); | |
92 | preempt_enable(); | |
93 | } |