[deliverable/linux.git] / arch / mips / kernel / mips-mt.c

/*
 * General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels
 * Copyright (C) 2005 Mips Technologies, Inc
 */

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/security.h>

#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/atomic.h>
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
#include <asm/mipsmtregs.h>
#include <asm/r4kcache.h>
#include <asm/cacheflush.h>

/*
 * CPU mask used to set process affinity for MT VPEs/TCs with FPUs
 */

cpumask_t mt_fpu_cpumask;

#ifdef CONFIG_MIPS_MT_FPAFF

#include <linux/cpu.h>
#include <linux/delay.h>
#include <asm/uaccess.h>

unsigned long mt_fpemul_threshold = 0;

/*
 * Replacement functions for the sys_sched_setaffinity() and
 * sys_sched_getaffinity() system calls, so that we can integrate
 * FPU affinity with the user's requested processor affinity.
 * This code is 98% identical with the sys_sched_setaffinity()
 * and sys_sched_getaffinity() system calls, and should be
 * updated when kernel/sched.c changes.
 */

/*
 * find_process_by_pid - find a process with a matching PID value.
 * used in sys_sched_set/getaffinity() in kernel/sched.c, so
 * cloned here.
 */
static inline struct task_struct *find_process_by_pid(pid_t pid)
{
	return pid ? find_task_by_pid(pid) : current;
}


/*
 * mipsmt_sys_sched_setaffinity - set the cpu affinity of a process
 */
asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
				      unsigned long __user *user_mask_ptr)
{
	cpumask_t new_mask;
	cpumask_t effective_mask;
	int retval;
	struct task_struct *p;

	if (len < sizeof(new_mask))
		return -EINVAL;

	if (copy_from_user(&new_mask, user_mask_ptr, sizeof(new_mask)))
		return -EFAULT;

	lock_cpu_hotplug();
	read_lock(&tasklist_lock);

	p = find_process_by_pid(pid);
	if (!p) {
		read_unlock(&tasklist_lock);
		unlock_cpu_hotplug();
		return -ESRCH;
	}

	/*
	 * It is not safe to call set_cpus_allowed with the
	 * tasklist_lock held.  We will bump the task_struct's
	 * usage count and drop tasklist_lock before invoking
	 * set_cpus_allowed.
	 */
	get_task_struct(p);

	retval = -EPERM;
	if ((current->euid != p->euid) && (current->euid != p->uid) &&
			!capable(CAP_SYS_NICE)) {
		read_unlock(&tasklist_lock);
		goto out_unlock;
	}

	/* Record new user-specified CPU set for future reference */
	p->thread.user_cpus_allowed = new_mask;

	/* Unlock the task list */
	read_unlock(&tasklist_lock);

	/* Compute new global allowed CPU set if necessary */
	if( (p->thread.mflags & MF_FPUBOUND)
	&& cpus_intersects(new_mask, mt_fpu_cpumask)) {
		cpus_and(effective_mask, new_mask, mt_fpu_cpumask);
		retval = set_cpus_allowed(p, effective_mask);
	} else {
		p->thread.mflags &= ~MF_FPUBOUND;
		retval = set_cpus_allowed(p, new_mask);
	}


out_unlock:
	put_task_struct(p);
	unlock_cpu_hotplug();
	return retval;
}

/*
 * mipsmt_sys_sched_getaffinity - get the cpu affinity of a process
 */
asmlinkage long mipsmt_sys_sched_getaffinity(pid_t pid, unsigned int len,
				      unsigned long __user *user_mask_ptr)
{
	unsigned int real_len;
	cpumask_t mask;
	int retval;
	struct task_struct *p;

	real_len = sizeof(mask);
	if (len < real_len)
		return -EINVAL;

	lock_cpu_hotplug();
	read_lock(&tasklist_lock);

	retval = -ESRCH;
	p = find_process_by_pid(pid);
	if (!p)
		goto out_unlock;

	retval = 0;

	cpus_and(mask, p->thread.user_cpus_allowed, cpu_possible_map);

out_unlock:
	read_unlock(&tasklist_lock);
	unlock_cpu_hotplug();
	if (retval)
		return retval;
	if (copy_to_user(user_mask_ptr, &mask, real_len))
		return -EFAULT;
	return real_len;
}

#endif /* CONFIG_MIPS_MT_FPAFF */

/*
 * Dump new MIPS MT state for the core. Does not leave TCs halted.
 * Takes an argument which taken to be a pre-call MVPControl value.
 */

void mips_mt_regdump(unsigned long mvpctl)
{
	unsigned long flags;
	unsigned long vpflags;
	unsigned long mvpconf0;
	int nvpe;
	int ntc;
	int i;
	int tc;
	unsigned long haltval;
	unsigned long tcstatval;
#ifdef CONFIG_MIPS_MT_SMTC
	void smtc_soft_dump(void);
#endif /* CONFIG_MIPT_MT_SMTC */

	local_irq_save(flags);
	vpflags = dvpe();
	printk("=== MIPS MT State Dump ===\n");
	printk("-- Global State --\n");
	printk("   MVPControl Passed: %08lx\n", mvpctl);
	printk("   MVPControl Read: %08lx\n", vpflags);
	printk("   MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
	printk("-- per-VPE State --\n");
	for(i = 0; i < nvpe; i++) {
	    for(tc = 0; tc < ntc; tc++) {
			settc(tc);
		if((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
		    printk("  VPE %d\n", i);
		    printk("   VPEControl : %08lx\n", read_vpe_c0_vpecontrol());
		    printk("   VPEConf0 : %08lx\n", read_vpe_c0_vpeconf0());
		    printk("   VPE%d.Status : %08lx\n",
				i, read_vpe_c0_status());
		    printk("   VPE%d.EPC : %08lx\n", i, read_vpe_c0_epc());
		    printk("   VPE%d.Cause : %08lx\n", i, read_vpe_c0_cause());
		    printk("   VPE%d.Config7 : %08lx\n",
				i, read_vpe_c0_config7());
		    break; /* Next VPE */
		}
	    }
	}
	printk("-- per-TC State --\n");
	for(tc = 0; tc < ntc; tc++) {
		settc(tc);
		if(read_tc_c0_tcbind() == read_c0_tcbind()) {
			/* Are we dumping ourself?  */
			haltval = 0; /* Then we're not halted, and mustn't be */
			tcstatval = flags; /* And pre-dump TCStatus is flags */
			printk("  TC %d (current TC with VPE EPC above)\n", tc);
		} else {
			haltval = read_tc_c0_tchalt();
			write_tc_c0_tchalt(1);
			tcstatval = read_tc_c0_tcstatus();
			printk("  TC %d\n", tc);
		}
		printk("   TCStatus : %08lx\n", tcstatval);
		printk("   TCBind : %08lx\n", read_tc_c0_tcbind());
		printk("   TCRestart : %08lx\n", read_tc_c0_tcrestart());
		printk("   TCHalt : %08lx\n", haltval);
		printk("   TCContext : %08lx\n", read_tc_c0_tccontext());
		if (!haltval)
			write_tc_c0_tchalt(0);
	}
#ifdef CONFIG_MIPS_MT_SMTC
	smtc_soft_dump();
#endif /* CONFIG_MIPT_MT_SMTC */
	printk("===========================\n");
	evpe(vpflags);
	local_irq_restore(flags);
}

static int mt_opt_norps = 0;
static int mt_opt_rpsctl = -1;
static int mt_opt_nblsu = -1;
static int mt_opt_forceconfig7 = 0;
static int mt_opt_config7 = -1;

static int __init rps_disable(char *s)
{
	mt_opt_norps = 1;
	return 1;
}
__setup("norps", rps_disable);

static int __init rpsctl_set(char *str)
{
	get_option(&str, &mt_opt_rpsctl);
	return 1;
}
__setup("rpsctl=", rpsctl_set);

static int __init nblsu_set(char *str)
{
	get_option(&str, &mt_opt_nblsu);
	return 1;
}
__setup("nblsu=", nblsu_set);

static int __init config7_set(char *str)
{
	get_option(&str, &mt_opt_config7);
	mt_opt_forceconfig7 = 1;
	return 1;
}
__setup("config7=", config7_set);

/* Experimental cache flush control parameters that should go away some day */
int mt_protiflush = 0;
int mt_protdflush = 0;
int mt_n_iflushes = 1;
int mt_n_dflushes = 1;

static int __init set_protiflush(char *s)
{
	mt_protiflush = 1;
	return 1;
}
__setup("protiflush", set_protiflush);

static int __init set_protdflush(char *s)
{
	mt_protdflush = 1;
	return 1;
}
__setup("protdflush", set_protdflush);

static int __init niflush(char *s)
{
	get_option(&s, &mt_n_iflushes);
	return 1;
}
__setup("niflush=", niflush);

static int __init ndflush(char *s)
{
	get_option(&s, &mt_n_dflushes);
	return 1;
}
__setup("ndflush=", ndflush);
#ifdef CONFIG_MIPS_MT_FPAFF
static int fpaff_threshold = -1;

static int __init fpaff_thresh(char *str)
{
	get_option(&str, &fpaff_threshold);
	return 1;
}

__setup("fpaff=", fpaff_thresh);
#endif /* CONFIG_MIPS_MT_FPAFF */

static unsigned int itc_base = 0;

static int __init set_itc_base(char *str)
{
	get_option(&str, &itc_base);
	return 1;
}

__setup("itcbase=", set_itc_base);

void mips_mt_set_cpuoptions(void)
{
	unsigned int oconfig7 = read_c0_config7();
	unsigned int nconfig7 = oconfig7;

	if (mt_opt_norps) {
		printk("\"norps\" option deprectated: use \"rpsctl=\"\n");
	}
	if (mt_opt_rpsctl >= 0) {
		printk("34K return prediction stack override set to %d.\n",
			mt_opt_rpsctl);
		if (mt_opt_rpsctl)
			nconfig7 |= (1 << 2);
		else
			nconfig7 &= ~(1 << 2);
	}
	if (mt_opt_nblsu >= 0) {
		printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
		if (mt_opt_nblsu)
			nconfig7 |= (1 << 5);
		else
			nconfig7 &= ~(1 << 5);
	}
	if (mt_opt_forceconfig7) {
		printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
		nconfig7 = mt_opt_config7;
	}
	if (oconfig7 != nconfig7) {
		__asm__ __volatile("sync");
		write_c0_config7(nconfig7);
		ehb ();
		printk("Config7: 0x%08x\n", read_c0_config7());
	}

	/* Report Cache management debug options */
	if (mt_protiflush)
		printk("I-cache flushes single-threaded\n");
	if (mt_protdflush)
		printk("D-cache flushes single-threaded\n");
	if (mt_n_iflushes != 1)
		printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
	if (mt_n_dflushes != 1)
		printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);

#ifdef CONFIG_MIPS_MT_FPAFF
	/* FPU Use Factor empirically derived from experiments on 34K */
#define FPUSEFACTOR 333

	if (fpaff_threshold >= 0) {
		mt_fpemul_threshold = fpaff_threshold;
	} else {
		mt_fpemul_threshold =
			(FPUSEFACTOR * (loops_per_jiffy/(500000/HZ))) / HZ;
	}
	printk("FPU Affinity set after %ld emulations\n",
			mt_fpemul_threshold);
#endif /* CONFIG_MIPS_MT_FPAFF */

	if (itc_base != 0) {
		/*
		 * Configure ITC mapping.  This code is very
		 * specific to the 34K core family, which uses
		 * a special mode bit ("ITC") in the ErrCtl
		 * register to enable access to ITC control
		 * registers via cache "tag" operations.
		 */
		unsigned long ectlval;
		unsigned long itcblkgrn;

		/* ErrCtl register is known as "ecc" to Linux */
		ectlval = read_c0_ecc();
		write_c0_ecc(ectlval | (0x1 << 26));
		ehb();
#define INDEX_0 (0x80000000)
#define INDEX_8 (0x80000008)
		/* Read "cache tag" for Dcache pseudo-index 8 */
		cache_op(Index_Load_Tag_D, INDEX_8);
		ehb();
		itcblkgrn = read_c0_dtaglo();
		itcblkgrn &= 0xfffe0000;
		/* Set for 128 byte pitch of ITC cells */
		itcblkgrn |= 0x00000c00;
		/* Stage in Tag register */
		write_c0_dtaglo(itcblkgrn);
		ehb();
		/* Write out to ITU with CACHE op */
		cache_op(Index_Store_Tag_D, INDEX_8);
		/* Now set base address, and turn ITC on with 0x1 bit */
		write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
		ehb();
		/* Write out to ITU with CACHE op */
		cache_op(Index_Store_Tag_D, INDEX_0);
		write_c0_ecc(ectlval);
		ehb();
		printk("Mapped %ld ITC cells starting at 0x%08x\n",
			((itcblkgrn & 0x7fe00000) >> 20), itc_base);
	}
}

/*
 * Function to protect cache flushes from concurrent execution
 * depends on MP software model chosen.
 */

void mt_cflush_lockdown(void)
{
#ifdef CONFIG_MIPS_MT_SMTC
	void smtc_cflush_lockdown(void);

	smtc_cflush_lockdown();
#endif /* CONFIG_MIPS_MT_SMTC */
	/* FILL IN VSMP and AP/SP VERSIONS HERE */
}

void mt_cflush_release(void)
{
#ifdef CONFIG_MIPS_MT_SMTC
	void smtc_cflush_release(void);

	smtc_cflush_release();
#endif /* CONFIG_MIPS_MT_SMTC */
	/* FILL IN VSMP and AP/SP VERSIONS HERE */
}
Commit	Line	Data
41c594ab RB	1	/*
	2	* General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels
	3	* Copyright (C) 2005 Mips Technologies, Inc
	4	*/
	5
	6	#include <linux/kernel.h>
	7	#include <linux/sched.h>
	8	#include <linux/cpumask.h>
	9	#include <linux/interrupt.h>
f72af3cf	10	#include <linux/security.h>
41c594ab RB	11
	12	#include <asm/cpu.h>
	13	#include <asm/processor.h>
	14	#include <asm/atomic.h>
	15	#include <asm/system.h>
	16	#include <asm/hardirq.h>
	17	#include <asm/mmu_context.h>
	18	#include <asm/smp.h>
	19	#include <asm/mipsmtregs.h>
	20	#include <asm/r4kcache.h>
	21	#include <asm/cacheflush.h>
	22
	23	/*
	24	* CPU mask used to set process affinity for MT VPEs/TCs with FPUs
	25	*/
	26
	27	cpumask_t mt_fpu_cpumask;
	28
	29	#ifdef CONFIG_MIPS_MT_FPAFF
	30
	31	#include <linux/cpu.h>
	32	#include <linux/delay.h>
	33	#include <asm/uaccess.h>
	34
	35	unsigned long mt_fpemul_threshold = 0;
	36
	37	/*
	38	* Replacement functions for the sys_sched_setaffinity() and
	39	* sys_sched_getaffinity() system calls, so that we can integrate
	40	* FPU affinity with the user's requested processor affinity.
	41	* This code is 98% identical with the sys_sched_setaffinity()
	42	* and sys_sched_getaffinity() system calls, and should be
	43	* updated when kernel/sched.c changes.
	44	*/
	45
	46	/*
	47	* find_process_by_pid - find a process with a matching PID value.
	48	* used in sys_sched_set/getaffinity() in kernel/sched.c, so
	49	* cloned here.
	50	*/
36c8b586	51	static inline struct task_struct *find_process_by_pid(pid_t pid)
41c594ab RB	52	{
	53	return pid ? find_task_by_pid(pid) : current;
	54	}
	55
	56
	57	/*
	58	* mipsmt_sys_sched_setaffinity - set the cpu affinity of a process
	59	*/
	60	asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
	61	unsigned long __user *user_mask_ptr)
	62	{
	63	cpumask_t new_mask;
	64	cpumask_t effective_mask;
	65	int retval;
36c8b586	66	struct task_struct *p;
41c594ab RB	67
	68	if (len < sizeof(new_mask))
	69	return -EINVAL;
	70
	71	if (copy_from_user(&new_mask, user_mask_ptr, sizeof(new_mask)))
	72	return -EFAULT;
	73
	74	lock_cpu_hotplug();
	75	read_lock(&tasklist_lock);
	76
	77	p = find_process_by_pid(pid);
	78	if (!p) {
	79	read_unlock(&tasklist_lock);
	80	unlock_cpu_hotplug();
	81	return -ESRCH;
	82	}
	83
	84	/*
	85	* It is not safe to call set_cpus_allowed with the
	86	* tasklist_lock held. We will bump the task_struct's
	87	* usage count and drop tasklist_lock before invoking
	88	* set_cpus_allowed.
	89	*/
	90	get_task_struct(p);
	91
	92	retval = -EPERM;
	93	if ((current->euid != p->euid) && (current->euid != p->uid) &&
	94	!capable(CAP_SYS_NICE)) {
	95	read_unlock(&tasklist_lock);
	96	goto out_unlock;
	97	}
	98
	99	/* Record new user-specified CPU set for future reference */
	100	p->thread.user_cpus_allowed = new_mask;
	101
	102	/* Unlock the task list */
	103	read_unlock(&tasklist_lock);
	104
	105	/* Compute new global allowed CPU set if necessary */
	106	if( (p->thread.mflags & MF_FPUBOUND)
	107	&& cpus_intersects(new_mask, mt_fpu_cpumask)) {
	108	cpus_and(effective_mask, new_mask, mt_fpu_cpumask);
	109	retval = set_cpus_allowed(p, effective_mask);
	110	} else {
	111	p->thread.mflags &= ~MF_FPUBOUND;
	112	retval = set_cpus_allowed(p, new_mask);
	113	}
	114
	115
	116	out_unlock:
	117	put_task_struct(p);
	118	unlock_cpu_hotplug();
	119	return retval;
	120	}
	121
	122	/*
	123	* mipsmt_sys_sched_getaffinity - get the cpu affinity of a process
	124	*/
	125	asmlinkage long mipsmt_sys_sched_getaffinity(pid_t pid, unsigned int len,
	126	unsigned long __user *user_mask_ptr)
	127	{
	128	unsigned int real_len;
	129	cpumask_t mask;
	130	int retval;
36c8b586	131	struct task_struct *p;
41c594ab RB	132
	133	real_len = sizeof(mask);
	134	if (len < real_len)
	135	return -EINVAL;
	136
	137	lock_cpu_hotplug();
	138	read_lock(&tasklist_lock);
	139
	140	retval = -ESRCH;
	141	p = find_process_by_pid(pid);
	142	if (!p)
	143	goto out_unlock;
	144
	145	retval = 0;
	146
	147	cpus_and(mask, p->thread.user_cpus_allowed, cpu_possible_map);
	148
	149	out_unlock:
	150	read_unlock(&tasklist_lock);
	151	unlock_cpu_hotplug();
	152	if (retval)
	153	return retval;
	154	if (copy_to_user(user_mask_ptr, &mask, real_len))
	155	return -EFAULT;
	156	return real_len;
	157	}
	158
	159	#endif /* CONFIG_MIPS_MT_FPAFF */
	160
	161	/*
	162	* Dump new MIPS MT state for the core. Does not leave TCs halted.
	163	* Takes an argument which taken to be a pre-call MVPControl value.
	164	*/
	165
	166	void mips_mt_regdump(unsigned long mvpctl)
	167	{
	168	unsigned long flags;
	169	unsigned long vpflags;
	170	unsigned long mvpconf0;
	171	int nvpe;
	172	int ntc;
	173	int i;
	174	int tc;
	175	unsigned long haltval;
	176	unsigned long tcstatval;
	177	#ifdef CONFIG_MIPS_MT_SMTC
	178	void smtc_soft_dump(void);
	179	#endif /* CONFIG_MIPT_MT_SMTC */
	180
	181	local_irq_save(flags);
	182	vpflags = dvpe();
	183	printk("=== MIPS MT State Dump ===\n");
	184	printk("-- Global State --\n");
	185	printk(" MVPControl Passed: %08lx\n", mvpctl);
	186	printk(" MVPControl Read: %08lx\n", vpflags);
	187	printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
	188	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	189	ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
	190	printk("-- per-VPE State --\n");
	191	for(i = 0; i < nvpe; i++) {
	192	for(tc = 0; tc < ntc; tc++) {
	193	settc(tc);
	194	if((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
	195	printk(" VPE %d\n", i);
196	printk(" VPEControl : %08lx\n", read_vpe_c0_vpecontrol());
197	printk(" VPEConf0 : %08lx\n", read_vpe_c0_vpeconf0());
198	printk(" VPE%d.Status : %08lx\n",
199	i, read_vpe_c0_status());
200	printk(" VPE%d.EPC : %08lx\n", i, read_vpe_c0_epc());
201	printk(" VPE%d.Cause : %08lx\n", i, read_vpe_c0_cause());
202	printk(" VPE%d.Config7 : %08lx\n",
203	i, read_vpe_c0_config7());
204	break; /* Next VPE */
205	}
206	}
207	}
208	printk("-- per-TC State --\n");
209	for(tc = 0; tc < ntc; tc++) {
210	settc(tc);
211	if(read_tc_c0_tcbind() == read_c0_tcbind()) {
212	/* Are we dumping ourself? */
213	haltval = 0; /* Then we're not halted, and mustn't be */
214	tcstatval = flags; /* And pre-dump TCStatus is flags */
215	printk(" TC %d (current TC with VPE EPC above)\n", tc);
216	} else {
217	haltval = read_tc_c0_tchalt();
218	write_tc_c0_tchalt(1);
219	tcstatval = read_tc_c0_tcstatus();
220	printk(" TC %d\n", tc);
221	}
222	printk(" TCStatus : %08lx\n", tcstatval);
223	printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
224	printk(" TCRestart : %08lx\n", read_tc_c0_tcrestart());
225	printk(" TCHalt : %08lx\n", haltval);
226	printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
227	if (!haltval)
228	write_tc_c0_tchalt(0);
229	}
230	#ifdef CONFIG_MIPS_MT_SMTC
231	smtc_soft_dump();
232	#endif /* CONFIG_MIPT_MT_SMTC */
233	printk("===========================\n");
234	evpe(vpflags);
235	local_irq_restore(flags);
236	}
237
238	static int mt_opt_norps = 0;
239	static int mt_opt_rpsctl = -1;
240	static int mt_opt_nblsu = -1;
241	static int mt_opt_forceconfig7 = 0;
242	static int mt_opt_config7 = -1;
243
244	static int __init rps_disable(char *s)
245	{
246	mt_opt_norps = 1;
247	return 1;
248	}
249	__setup("norps", rps_disable);
250
251	static int __init rpsctl_set(char *str)
252	{
253	get_option(&str, &mt_opt_rpsctl);
254	return 1;
255	}
256	__setup("rpsctl=", rpsctl_set);
257
258	static int __init nblsu_set(char *str)
259	{
260	get_option(&str, &mt_opt_nblsu);
261	return 1;
262	}
263	__setup("nblsu=", nblsu_set);
264
265	static int __init config7_set(char *str)
266	{
267	get_option(&str, &mt_opt_config7);
268	mt_opt_forceconfig7 = 1;
269	return 1;
270	}
271	__setup("config7=", config7_set);
272
273	/* Experimental cache flush control parameters that should go away some day */
274	int mt_protiflush = 0;
275	int mt_protdflush = 0;
276	int mt_n_iflushes = 1;
277	int mt_n_dflushes = 1;
278
279	static int __init set_protiflush(char *s)
280	{
281	mt_protiflush = 1;
282	return 1;
283	}
284	__setup("protiflush", set_protiflush);
285
286	static int __init set_protdflush(char *s)
287	{
288	mt_protdflush = 1;
289	return 1;
290	}
291	__setup("protdflush", set_protdflush);
292
293	static int __init niflush(char *s)
294	{
295	get_option(&s, &mt_n_iflushes);
296	return 1;
297	}
298	__setup("niflush=", niflush);
299
300	static int __init ndflush(char *s)
301	{
302	get_option(&s, &mt_n_dflushes);
303	return 1;
304	}
305	__setup("ndflush=", ndflush);
306	#ifdef CONFIG_MIPS_MT_FPAFF
307	static int fpaff_threshold = -1;
308
309	static int __init fpaff_thresh(char *str)
310	{
311	get_option(&str, &fpaff_threshold);
312	return 1;
313	}
314
315	__setup("fpaff=", fpaff_thresh);
316	#endif /* CONFIG_MIPS_MT_FPAFF */
317
318	static unsigned int itc_base = 0;
319
320	static int __init set_itc_base(char *str)
321	{
322	get_option(&str, &itc_base);
323	return 1;
324	}
325
326	__setup("itcbase=", set_itc_base);
327
328	void mips_mt_set_cpuoptions(void)
329	{
330	unsigned int oconfig7 = read_c0_config7();
331	unsigned int nconfig7 = oconfig7;
332
333	if (mt_opt_norps) {
334	printk("\"norps\" option deprectated: use \"rpsctl=\"\n");
335	}
336	if (mt_opt_rpsctl >= 0) {
337	printk("34K return prediction stack override set to %d.\n",
338	mt_opt_rpsctl);
339	if (mt_opt_rpsctl)
340	nconfig7 \|= (1 << 2);
341	else
342	nconfig7 &= ~(1 << 2);
343	}
344	if (mt_opt_nblsu >= 0) {
345	printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
346	if (mt_opt_nblsu)
347	nconfig7 \|= (1 << 5);
348	else
349	nconfig7 &= ~(1 << 5);
350	}
351	if (mt_opt_forceconfig7) {
352	printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
353	nconfig7 = mt_opt_config7;
354	}
355	if (oconfig7 != nconfig7) {
356	__asm__ __volatile("sync");
357	write_c0_config7(nconfig7);
358	ehb ();
359	printk("Config7: 0x%08x\n", read_c0_config7());
360	}
361
362	/* Report Cache management debug options */
363	if (mt_protiflush)
364	printk("I-cache flushes single-threaded\n");
365	if (mt_protdflush)
366	printk("D-cache flushes single-threaded\n");
367	if (mt_n_iflushes != 1)
368	printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
369	if (mt_n_dflushes != 1)
370	printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
371
372	#ifdef CONFIG_MIPS_MT_FPAFF
373	/* FPU Use Factor empirically derived from experiments on 34K */
374	#define FPUSEFACTOR 333
375
376	if (fpaff_threshold >= 0) {
377	mt_fpemul_threshold = fpaff_threshold;
378	} else {
379	mt_fpemul_threshold =
380	(FPUSEFACTOR * (loops_per_jiffy/(500000/HZ))) / HZ;
381	}
382	printk("FPU Affinity set after %ld emulations\n",
383	mt_fpemul_threshold);
384	#endif /* CONFIG_MIPS_MT_FPAFF */
385
386	if (itc_base != 0) {
387	/*
388	* Configure ITC mapping. This code is very
389	* specific to the 34K core family, which uses
390	* a special mode bit ("ITC") in the ErrCtl
391	* register to enable access to ITC control
392	* registers via cache "tag" operations.
393	*/
394	unsigned long ectlval;
395	unsigned long itcblkgrn;
396
397	/* ErrCtl register is known as "ecc" to Linux */
398	ectlval = read_c0_ecc();
399	write_c0_ecc(ectlval \| (0x1 << 26));
400	ehb();
401	#define INDEX_0 (0x80000000)
402	#define INDEX_8 (0x80000008)
403	/* Read "cache tag" for Dcache pseudo-index 8 */
404	cache_op(Index_Load_Tag_D, INDEX_8);
405	ehb();
406	itcblkgrn = read_c0_dtaglo();
407	itcblkgrn &= 0xfffe0000;
408	/* Set for 128 byte pitch of ITC cells */
409	itcblkgrn \|= 0x00000c00;
410	/* Stage in Tag register */
411	write_c0_dtaglo(itcblkgrn);
412	ehb();
413	/* Write out to ITU with CACHE op */
414	cache_op(Index_Store_Tag_D, INDEX_8);
415	/* Now set base address, and turn ITC on with 0x1 bit */
416	write_c0_dtaglo((itc_base & 0xfffffc00) \| 0x1 );
417	ehb();
418	/* Write out to ITU with CACHE op */
419	cache_op(Index_Store_Tag_D, INDEX_0);
420	write_c0_ecc(ectlval);
421	ehb();
422	printk("Mapped %ld ITC cells starting at 0x%08x\n",
423	((itcblkgrn & 0x7fe00000) >> 20), itc_base);
424	}
425	}
426
427	/*
428	* Function to protect cache flushes from concurrent execution
429	* depends on MP software model chosen.
430	*/
431
432	void mt_cflush_lockdown(void)
433	{
434	#ifdef CONFIG_MIPS_MT_SMTC
435	void smtc_cflush_lockdown(void);
436
437	smtc_cflush_lockdown();
438	#endif /* CONFIG_MIPS_MT_SMTC */
439	/* FILL IN VSMP and AP/SP VERSIONS HERE */
440	}
441
442	void mt_cflush_release(void)
443	{
444	#ifdef CONFIG_MIPS_MT_SMTC
445	void smtc_cflush_release(void);
446
447	smtc_cflush_release();
448	#endif /* CONFIG_MIPS_MT_SMTC */
449	/* FILL IN VSMP and AP/SP VERSIONS HERE */
450	}