[deliverable/linux.git] / arch / mips / kernel / octeon_switch.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
 * Copyright (C) 1999 Silicon Graphics, Inc.
 * Copyright (C) 2000 MIPS Technologies, Inc.
 *    written by Carsten Langgaard, carstenl@mips.com
 */

#define USE_ALTERNATE_RESUME_IMPL 1
	.set push
	.set arch=mips64r2
#include "r4k_switch.S"
	.set pop
/*
 * task_struct *resume(task_struct *prev, task_struct *next,
 *		       struct thread_info *next_ti, int usedfpu)
 */
	.align	7
	LEAF(resume)
	.set arch=octeon
	mfc0	t1, CP0_STATUS
	LONG_S	t1, THREAD_STATUS(a0)
	cpu_save_nonscratch a0
	LONG_S	ra, THREAD_REG31(a0)

	/*
	 * check if we need to save FPU registers
	 */
	PTR_L	t3, TASK_THREAD_INFO(a0)
	LONG_L	t0, TI_FLAGS(t3)
	li	t1, _TIF_USEDFPU
	and	t2, t0, t1
	beqz	t2, 1f
	nor	t1, zero, t1

	and	t0, t0, t1
	LONG_S	t0, TI_FLAGS(t3)

	/*
	 * clear saved user stack CU1 bit
	 */
	LONG_L	t0, ST_OFF(t3)
	li	t1, ~ST0_CU1
	and	t0, t0, t1
	LONG_S	t0, ST_OFF(t3)

	.set push
	.set arch=mips64r2
	fpu_save_double a0 t0 t1		# c0_status passed in t0
						# clobbers t1
	.set pop
1:

	/* check if we need to save COP2 registers */
	PTR_L	t2, TASK_THREAD_INFO(a0)
	LONG_L	t0, ST_OFF(t2)
	bbit0	t0, 30, 1f

	/* Disable COP2 in the stored process state */
	li	t1, ST0_CU2
	xor	t0, t1
	LONG_S	t0, ST_OFF(t2)

	/* Enable COP2 so we can save it */
	mfc0	t0, CP0_STATUS
	or	t0, t1
	mtc0	t0, CP0_STATUS

	/* Save COP2 */
	daddu	a0, THREAD_CP2
	jal octeon_cop2_save
	dsubu	a0, THREAD_CP2

	/* Disable COP2 now that we are done */
	mfc0	t0, CP0_STATUS
	li	t1, ST0_CU2
	xor	t0, t1
	mtc0	t0, CP0_STATUS

1:
#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
	/* Check if we need to store CVMSEG state */
	mfc0	t0, $11,7	/* CvmMemCtl */
	bbit0	t0, 6, 3f	/* Is user access enabled? */

	/* Store the CVMSEG state */
	/* Extract the size of CVMSEG */
	andi	t0, 0x3f
	/* Multiply * (cache line size/sizeof(long)/2) */
	sll	t0, 7-LONGLOG-1
	li	t1, -32768	/* Base address of CVMSEG */
	LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
	synciobdma
2:
	.set noreorder
	LONG_L	t8, 0(t1)	/* Load from CVMSEG */
	subu	t0, 1		/* Decrement loop var */
	LONG_L	t9, LONGSIZE(t1)/* Load from CVMSEG */
	LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
	LONG_S	t8, 0(t2)	/* Store CVMSEG to thread storage */
	LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
	bnez	t0, 2b		/* Loop until we've copied it all */
	 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
	.set reorder

	/* Disable access to CVMSEG */
	mfc0	t0, $11,7	/* CvmMemCtl */
	xori	t0, t0, 0x40	/* Bit 6 is CVMSEG user enable */
	mtc0	t0, $11,7	/* CvmMemCtl */
#endif
3:

#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
	PTR_LA	t8, __stack_chk_guard
	LONG_L	t9, TASK_STACK_CANARY(a1)
	LONG_S	t9, 0(t8)
#endif

	/*
	 * The order of restoring the registers takes care of the race
	 * updating $28, $29 and kernelsp without disabling ints.
	 */
	move	$28, a2
	cpu_restore_nonscratch a1

	PTR_ADDU	t0, $28, _THREAD_SIZE - 32
	set_saved_sp	t0, t1, t2

	mfc0	t1, CP0_STATUS		/* Do we really need this? */
	li	a3, 0xff01
	and	t1, a3
	LONG_L	a2, THREAD_STATUS(a1)
	nor	a3, $0, a3
	and	a2, a3
	or	a2, t1
	mtc0	a2, CP0_STATUS
	move	v0, a0
	jr	ra
	END(resume)

/*
 * void octeon_cop2_save(struct octeon_cop2_state *a0)
 */
	.align	7
	LEAF(octeon_cop2_save)

	dmfc0	t9, $9,7	/* CvmCtl register. */

	/* Save the COP2 CRC state */
	dmfc2	t0, 0x0201
	dmfc2	t1, 0x0202
	dmfc2	t2, 0x0200
	sd	t0, OCTEON_CP2_CRC_IV(a0)
	sd	t1, OCTEON_CP2_CRC_LENGTH(a0)
	sd	t2, OCTEON_CP2_CRC_POLY(a0)
	/* Skip next instructions if CvmCtl[NODFA_CP2] set */
	bbit1	t9, 28, 1f

	/* Save the LLM state */
	dmfc2	t0, 0x0402
	dmfc2	t1, 0x040A
	sd	t0, OCTEON_CP2_LLM_DAT(a0)
	sd	t1, OCTEON_CP2_LLM_DAT+8(a0)

1:	bbit1	t9, 26, 3f	/* done if CvmCtl[NOCRYPTO] set */

	/* Save the COP2 crypto state */
	/* this part is mostly common to both pass 1 and later revisions */
	dmfc2	t0, 0x0084
	dmfc2	t1, 0x0080
	dmfc2	t2, 0x0081
	dmfc2	t3, 0x0082
	sd	t0, OCTEON_CP2_3DES_IV(a0)
	dmfc2	t0, 0x0088
	sd	t1, OCTEON_CP2_3DES_KEY(a0)
	dmfc2	t1, 0x0111			/* only necessary for pass 1 */
	sd	t2, OCTEON_CP2_3DES_KEY+8(a0)
	dmfc2	t2, 0x0102
	sd	t3, OCTEON_CP2_3DES_KEY+16(a0)
	dmfc2	t3, 0x0103
	sd	t0, OCTEON_CP2_3DES_RESULT(a0)
	dmfc2	t0, 0x0104
	sd	t1, OCTEON_CP2_AES_INP0(a0)	/* only necessary for pass 1 */
	dmfc2	t1, 0x0105
	sd	t2, OCTEON_CP2_AES_IV(a0)
	dmfc2	t2, 0x0106
	sd	t3, OCTEON_CP2_AES_IV+8(a0)
	dmfc2	t3, 0x0107
	sd	t0, OCTEON_CP2_AES_KEY(a0)
	dmfc2	t0, 0x0110
	sd	t1, OCTEON_CP2_AES_KEY+8(a0)
	dmfc2	t1, 0x0100
	sd	t2, OCTEON_CP2_AES_KEY+16(a0)
	dmfc2	t2, 0x0101
	sd	t3, OCTEON_CP2_AES_KEY+24(a0)
	mfc0	t3, $15,0	/* Get the processor ID register */
	sd	t0, OCTEON_CP2_AES_KEYLEN(a0)
	li	t0, 0x000d0000	/* This is the processor ID of Octeon Pass1 */
	sd	t1, OCTEON_CP2_AES_RESULT(a0)
	sd	t2, OCTEON_CP2_AES_RESULT+8(a0)
	/* Skip to the Pass1 version of the remainder of the COP2 state */
	beq	t3, t0, 2f

	/* the non-pass1 state when !CvmCtl[NOCRYPTO] */
	dmfc2	t1, 0x0240
	dmfc2	t2, 0x0241
	dmfc2	t3, 0x0242
	dmfc2	t0, 0x0243
	sd	t1, OCTEON_CP2_HSH_DATW(a0)
	dmfc2	t1, 0x0244
	sd	t2, OCTEON_CP2_HSH_DATW+8(a0)
	dmfc2	t2, 0x0245
	sd	t3, OCTEON_CP2_HSH_DATW+16(a0)
	dmfc2	t3, 0x0246
	sd	t0, OCTEON_CP2_HSH_DATW+24(a0)
	dmfc2	t0, 0x0247
	sd	t1, OCTEON_CP2_HSH_DATW+32(a0)
	dmfc2	t1, 0x0248
	sd	t2, OCTEON_CP2_HSH_DATW+40(a0)
	dmfc2	t2, 0x0249
	sd	t3, OCTEON_CP2_HSH_DATW+48(a0)
	dmfc2	t3, 0x024A
	sd	t0, OCTEON_CP2_HSH_DATW+56(a0)
	dmfc2	t0, 0x024B
	sd	t1, OCTEON_CP2_HSH_DATW+64(a0)
	dmfc2	t1, 0x024C
	sd	t2, OCTEON_CP2_HSH_DATW+72(a0)
	dmfc2	t2, 0x024D
	sd	t3, OCTEON_CP2_HSH_DATW+80(a0)
	dmfc2	t3, 0x024E
	sd	t0, OCTEON_CP2_HSH_DATW+88(a0)
	dmfc2	t0, 0x0250
	sd	t1, OCTEON_CP2_HSH_DATW+96(a0)
	dmfc2	t1, 0x0251
	sd	t2, OCTEON_CP2_HSH_DATW+104(a0)
	dmfc2	t2, 0x0252
	sd	t3, OCTEON_CP2_HSH_DATW+112(a0)
	dmfc2	t3, 0x0253
	sd	t0, OCTEON_CP2_HSH_IVW(a0)
	dmfc2	t0, 0x0254
	sd	t1, OCTEON_CP2_HSH_IVW+8(a0)
	dmfc2	t1, 0x0255
	sd	t2, OCTEON_CP2_HSH_IVW+16(a0)
	dmfc2	t2, 0x0256
	sd	t3, OCTEON_CP2_HSH_IVW+24(a0)
	dmfc2	t3, 0x0257
	sd	t0, OCTEON_CP2_HSH_IVW+32(a0)
	dmfc2	t0, 0x0258
	sd	t1, OCTEON_CP2_HSH_IVW+40(a0)
	dmfc2	t1, 0x0259
	sd	t2, OCTEON_CP2_HSH_IVW+48(a0)
	dmfc2	t2, 0x025E
	sd	t3, OCTEON_CP2_HSH_IVW+56(a0)
	dmfc2	t3, 0x025A
	sd	t0, OCTEON_CP2_GFM_MULT(a0)
	dmfc2	t0, 0x025B
	sd	t1, OCTEON_CP2_GFM_MULT+8(a0)
	sd	t2, OCTEON_CP2_GFM_POLY(a0)
	sd	t3, OCTEON_CP2_GFM_RESULT(a0)
	sd	t0, OCTEON_CP2_GFM_RESULT+8(a0)
	jr	ra

2:	/* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
	dmfc2	t3, 0x0040
	dmfc2	t0, 0x0041
	dmfc2	t1, 0x0042
	dmfc2	t2, 0x0043
	sd	t3, OCTEON_CP2_HSH_DATW(a0)
	dmfc2	t3, 0x0044
	sd	t0, OCTEON_CP2_HSH_DATW+8(a0)
	dmfc2	t0, 0x0045
	sd	t1, OCTEON_CP2_HSH_DATW+16(a0)
	dmfc2	t1, 0x0046
	sd	t2, OCTEON_CP2_HSH_DATW+24(a0)
	dmfc2	t2, 0x0048
	sd	t3, OCTEON_CP2_HSH_DATW+32(a0)
	dmfc2	t3, 0x0049
	sd	t0, OCTEON_CP2_HSH_DATW+40(a0)
	dmfc2	t0, 0x004A
	sd	t1, OCTEON_CP2_HSH_DATW+48(a0)
	sd	t2, OCTEON_CP2_HSH_IVW(a0)
	sd	t3, OCTEON_CP2_HSH_IVW+8(a0)
	sd	t0, OCTEON_CP2_HSH_IVW+16(a0)

3:	/* pass 1 or CvmCtl[NOCRYPTO] set */
	jr	ra
	END(octeon_cop2_save)

/*
 * void octeon_cop2_restore(struct octeon_cop2_state *a0)
 */
	.align	7
	.set push
	.set noreorder
	LEAF(octeon_cop2_restore)
	/* First cache line was prefetched before the call */
	pref	4,  128(a0)
	dmfc0	t9, $9,7	/* CvmCtl register. */

	pref	4,  256(a0)
	ld	t0, OCTEON_CP2_CRC_IV(a0)
	pref	4,  384(a0)
	ld	t1, OCTEON_CP2_CRC_LENGTH(a0)
	ld	t2, OCTEON_CP2_CRC_POLY(a0)

	/* Restore the COP2 CRC state */
	dmtc2	t0, 0x0201
	dmtc2	t1, 0x1202
	bbit1	t9, 28, 2f	/* Skip LLM if CvmCtl[NODFA_CP2] is set */
	 dmtc2	t2, 0x4200

	/* Restore the LLM state */
	ld	t0, OCTEON_CP2_LLM_DAT(a0)
	ld	t1, OCTEON_CP2_LLM_DAT+8(a0)
	dmtc2	t0, 0x0402
	dmtc2	t1, 0x040A

2:
	bbit1	t9, 26, done_restore	/* done if CvmCtl[NOCRYPTO] set */
	 nop

	/* Restore the COP2 crypto state common to pass 1 and pass 2 */
	ld	t0, OCTEON_CP2_3DES_IV(a0)
	ld	t1, OCTEON_CP2_3DES_KEY(a0)
	ld	t2, OCTEON_CP2_3DES_KEY+8(a0)
	dmtc2	t0, 0x0084
	ld	t0, OCTEON_CP2_3DES_KEY+16(a0)
	dmtc2	t1, 0x0080
	ld	t1, OCTEON_CP2_3DES_RESULT(a0)
	dmtc2	t2, 0x0081
	ld	t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
	dmtc2	t0, 0x0082
	ld	t0, OCTEON_CP2_AES_IV(a0)
	dmtc2	t1, 0x0098
	ld	t1, OCTEON_CP2_AES_IV+8(a0)
	dmtc2	t2, 0x010A		    /* only really needed for pass 1 */
	ld	t2, OCTEON_CP2_AES_KEY(a0)
	dmtc2	t0, 0x0102
	ld	t0, OCTEON_CP2_AES_KEY+8(a0)
	dmtc2	t1, 0x0103
	ld	t1, OCTEON_CP2_AES_KEY+16(a0)
	dmtc2	t2, 0x0104
	ld	t2, OCTEON_CP2_AES_KEY+24(a0)
	dmtc2	t0, 0x0105
	ld	t0, OCTEON_CP2_AES_KEYLEN(a0)
	dmtc2	t1, 0x0106
	ld	t1, OCTEON_CP2_AES_RESULT(a0)
	dmtc2	t2, 0x0107
	ld	t2, OCTEON_CP2_AES_RESULT+8(a0)
	mfc0	t3, $15,0	/* Get the processor ID register */
	dmtc2	t0, 0x0110
	li	t0, 0x000d0000	/* This is the processor ID of Octeon Pass1 */
	dmtc2	t1, 0x0100
	bne	t0, t3, 3f	/* Skip the next stuff for non-pass1 */
	 dmtc2	t2, 0x0101

	/* this code is specific for pass 1 */
	ld	t0, OCTEON_CP2_HSH_DATW(a0)
	ld	t1, OCTEON_CP2_HSH_DATW+8(a0)
	ld	t2, OCTEON_CP2_HSH_DATW+16(a0)
	dmtc2	t0, 0x0040
	ld	t0, OCTEON_CP2_HSH_DATW+24(a0)
	dmtc2	t1, 0x0041
	ld	t1, OCTEON_CP2_HSH_DATW+32(a0)
	dmtc2	t2, 0x0042
	ld	t2, OCTEON_CP2_HSH_DATW+40(a0)
	dmtc2	t0, 0x0043
	ld	t0, OCTEON_CP2_HSH_DATW+48(a0)
	dmtc2	t1, 0x0044
	ld	t1, OCTEON_CP2_HSH_IVW(a0)
	dmtc2	t2, 0x0045
	ld	t2, OCTEON_CP2_HSH_IVW+8(a0)
	dmtc2	t0, 0x0046
	ld	t0, OCTEON_CP2_HSH_IVW+16(a0)
	dmtc2	t1, 0x0048
	dmtc2	t2, 0x0049
	b done_restore	 /* unconditional branch */
	 dmtc2	t0, 0x004A

3:	/* this is post-pass1 code */
	ld	t2, OCTEON_CP2_HSH_DATW(a0)
	ld	t0, OCTEON_CP2_HSH_DATW+8(a0)
	ld	t1, OCTEON_CP2_HSH_DATW+16(a0)
	dmtc2	t2, 0x0240
	ld	t2, OCTEON_CP2_HSH_DATW+24(a0)
	dmtc2	t0, 0x0241
	ld	t0, OCTEON_CP2_HSH_DATW+32(a0)
	dmtc2	t1, 0x0242
	ld	t1, OCTEON_CP2_HSH_DATW+40(a0)
	dmtc2	t2, 0x0243
	ld	t2, OCTEON_CP2_HSH_DATW+48(a0)
	dmtc2	t0, 0x0244
	ld	t0, OCTEON_CP2_HSH_DATW+56(a0)
	dmtc2	t1, 0x0245
	ld	t1, OCTEON_CP2_HSH_DATW+64(a0)
	dmtc2	t2, 0x0246
	ld	t2, OCTEON_CP2_HSH_DATW+72(a0)
	dmtc2	t0, 0x0247
	ld	t0, OCTEON_CP2_HSH_DATW+80(a0)
	dmtc2	t1, 0x0248
	ld	t1, OCTEON_CP2_HSH_DATW+88(a0)
	dmtc2	t2, 0x0249
	ld	t2, OCTEON_CP2_HSH_DATW+96(a0)
	dmtc2	t0, 0x024A
	ld	t0, OCTEON_CP2_HSH_DATW+104(a0)
	dmtc2	t1, 0x024B
	ld	t1, OCTEON_CP2_HSH_DATW+112(a0)
	dmtc2	t2, 0x024C
	ld	t2, OCTEON_CP2_HSH_IVW(a0)
	dmtc2	t0, 0x024D
	ld	t0, OCTEON_CP2_HSH_IVW+8(a0)
	dmtc2	t1, 0x024E
	ld	t1, OCTEON_CP2_HSH_IVW+16(a0)
	dmtc2	t2, 0x0250
	ld	t2, OCTEON_CP2_HSH_IVW+24(a0)
	dmtc2	t0, 0x0251
	ld	t0, OCTEON_CP2_HSH_IVW+32(a0)
	dmtc2	t1, 0x0252
	ld	t1, OCTEON_CP2_HSH_IVW+40(a0)
	dmtc2	t2, 0x0253
	ld	t2, OCTEON_CP2_HSH_IVW+48(a0)
	dmtc2	t0, 0x0254
	ld	t0, OCTEON_CP2_HSH_IVW+56(a0)
	dmtc2	t1, 0x0255
	ld	t1, OCTEON_CP2_GFM_MULT(a0)
	dmtc2	t2, 0x0256
	ld	t2, OCTEON_CP2_GFM_MULT+8(a0)
	dmtc2	t0, 0x0257
	ld	t0, OCTEON_CP2_GFM_POLY(a0)
	dmtc2	t1, 0x0258
	ld	t1, OCTEON_CP2_GFM_RESULT(a0)
	dmtc2	t2, 0x0259
	ld	t2, OCTEON_CP2_GFM_RESULT+8(a0)
	dmtc2	t0, 0x025E
	dmtc2	t1, 0x025A
	dmtc2	t2, 0x025B

done_restore:
	jr	ra
	 nop
	END(octeon_cop2_restore)
	.set pop

/*
 * void octeon_mult_save()
 * sp is assumed to point to a struct pt_regs
 *
 * NOTE: This is called in SAVE_TEMP in stackframe.h. It can
 *       safely modify v1,k0, k1,$10-$15, and $24.  It will
 *	 be overwritten with a processor specific version of the code.
 */
	.p2align 7
	.set push
	.set noreorder
	LEAF(octeon_mult_save)
	jr	ra
	 nop
	.space 30 * 4, 0
octeon_mult_save_end:
	EXPORT(octeon_mult_save_end)
	END(octeon_mult_save)

	LEAF(octeon_mult_save2)
	/* Save the multiplier state OCTEON II and earlier*/
	v3mulu	k0, $0, $0
	v3mulu	k1, $0, $0
	sd	k0, PT_MTP(sp)	      /* PT_MTP	   has P0 */
	v3mulu	k0, $0, $0
	sd	k1, PT_MTP+8(sp)      /* PT_MTP+8  has P1 */
	ori	k1, $0, 1
	v3mulu	k1, k1, $0
	sd	k0, PT_MTP+16(sp)     /* PT_MTP+16 has P2 */
	v3mulu	k0, $0, $0
	sd	k1, PT_MPL(sp)	      /* PT_MPL	   has MPL0 */
	v3mulu	k1, $0, $0
	sd	k0, PT_MPL+8(sp)      /* PT_MPL+8  has MPL1 */
	jr	ra
	 sd	k1, PT_MPL+16(sp)     /* PT_MPL+16 has MPL2 */
octeon_mult_save2_end:
	EXPORT(octeon_mult_save2_end)
	END(octeon_mult_save2)

	LEAF(octeon_mult_save3)
	/* Save the multiplier state OCTEON III */
	v3mulu	$10, $0, $0		/* read P0 */
	v3mulu	$11, $0, $0		/* read P1 */
	v3mulu	$12, $0, $0		/* read P2 */
	sd	$10, PT_MTP+(0*8)(sp)	/* store P0 */
	v3mulu	$10, $0, $0		/* read P3 */
	sd	$11, PT_MTP+(1*8)(sp)	/*  store P1 */
	v3mulu	$11, $0, $0		/* read P4 */
	sd	$12, PT_MTP+(2*8)(sp)	/* store P2 */
	ori	$13, $0, 1
	v3mulu	$12, $0, $0		/* read P5 */
	sd	$10, PT_MTP+(3*8)(sp)	/* store P3 */
	v3mulu	$13, $13, $0		/* P4-P0 = MPL5-MPL1, $13 = MPL0 */
	sd	$11, PT_MTP+(4*8)(sp)	/* store P4 */
	v3mulu	$10, $0, $0		/* read MPL1 */
	sd	$12, PT_MTP+(5*8)(sp)	/* store P5 */
	v3mulu	$11, $0, $0		/* read MPL2 */
	sd	$13, PT_MPL+(0*8)(sp)	/* store MPL0 */
	v3mulu	$12, $0, $0		/* read MPL3 */
	sd	$10, PT_MPL+(1*8)(sp)	/* store MPL1 */
	v3mulu	$10, $0, $0		/* read MPL4 */
	sd	$11, PT_MPL+(2*8)(sp)	/* store MPL2 */
	v3mulu	$11, $0, $0		/* read MPL5 */
	sd	$12, PT_MPL+(3*8)(sp)	/* store MPL3 */
	sd	$10, PT_MPL+(4*8)(sp)	/* store MPL4 */
	jr	ra
	 sd	$11, PT_MPL+(5*8)(sp)	/* store MPL5 */
octeon_mult_save3_end:
	EXPORT(octeon_mult_save3_end)
	END(octeon_mult_save3)
	.set pop

/*
 * void octeon_mult_restore()
 * sp is assumed to point to a struct pt_regs
 *
 * NOTE: This is called in RESTORE_TEMP in stackframe.h.
 */
	.p2align 7
	.set push
	.set noreorder
	LEAF(octeon_mult_restore)
	jr	ra
	 nop
	.space 30 * 4, 0
octeon_mult_restore_end:
	EXPORT(octeon_mult_restore_end)
	END(octeon_mult_restore)

	LEAF(octeon_mult_restore2)
	ld	v0, PT_MPL(sp)        	/* MPL0 */
	ld	v1, PT_MPL+8(sp)      	/* MPL1 */
	ld	k0, PT_MPL+16(sp)     	/* MPL2 */
	/* Restore the multiplier state */
	ld	k1, PT_MTP+16(sp)     	/* P2 */
	mtm0	v0			/* MPL0 */
	ld	v0, PT_MTP+8(sp)	/* P1 */
	mtm1	v1			/* MPL1 */
	ld	v1, PT_MTP(sp)   	/* P0 */
	mtm2	k0			/* MPL2 */
	mtp2	k1			/* P2 */
	mtp1	v0			/* P1 */
	jr	ra
	 mtp0	v1			/* P0 */
octeon_mult_restore2_end:
	EXPORT(octeon_mult_restore2_end)
	END(octeon_mult_restore2)

	LEAF(octeon_mult_restore3)
	ld	$12, PT_MPL+(0*8)(sp)	/* read MPL0 */
	ld	$13, PT_MPL+(3*8)(sp)	/* read MPL3 */
	ld	$10, PT_MPL+(1*8)(sp)	/* read MPL1 */
	ld	$11, PT_MPL+(4*8)(sp)	/* read MPL4 */
	.word	0x718d0008
	/* mtm0	$12, $13		   restore MPL0 and MPL3 */
	ld	$12, PT_MPL+(2*8)(sp)	/* read MPL2 */
	.word	0x714b000c
	/* mtm1	$10, $11		   restore MPL1 and MPL4 */
	ld	$13, PT_MPL+(5*8)(sp)	/* read MPL5 */
	ld	$10, PT_MTP+(0*8)(sp)	/* read P0 */
	ld	$11, PT_MTP+(3*8)(sp)	/* read P3 */
	.word	0x718d000d
	/* mtm2	$12, $13		   restore MPL2 and MPL5 */
	ld	$12, PT_MTP+(1*8)(sp)	/* read P1 */
	.word	0x714b0009
	/* mtp0	$10, $11		   restore P0 and P3 */
	ld	$13, PT_MTP+(4*8)(sp)	/* read P4 */
	ld	$10, PT_MTP+(2*8)(sp)	/* read P2 */
	ld	$11, PT_MTP+(5*8)(sp)	/* read P5 */
	.word	0x718d000a
	/* mtp1	$12, $13		   restore P1 and P4 */
	jr	ra
	.word	0x714b000b
	/* mtp2	$10, $11		   restore P2 and P5 */

octeon_mult_restore3_end:
	EXPORT(octeon_mult_restore3_end)
	END(octeon_mult_restore3)
	.set pop
Commit	Line	Data
5b3b1688 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
79add627	7	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
5b3b1688 DD	8	* Copyright (C) 1994, 1995, 1996, by Andreas Busse
	9	* Copyright (C) 1999 Silicon Graphics, Inc.
	10	* Copyright (C) 2000 MIPS Technologies, Inc.
	11	* written by Carsten Langgaard, carstenl@mips.com
	12	*/
5b3b1688	13
a36d8225 DD	14	#define USE_ALTERNATE_RESUME_IMPL 1
	15	.set push
	16	.set arch=mips64r2
	17	#include "r4k_switch.S"
	18	.set pop
5b3b1688 DD	19	/*
5b3b1688 DD	20	* task_struct resume(task_struct prev, task_struct *next,
70342287	21	* struct thread_info *next_ti, int usedfpu)
5b3b1688 DD	22	*/
	23	.align 7
	24	LEAF(resume)
	25	.set arch=octeon
5b3b1688 DD	26	mfc0 t1, CP0_STATUS
	27	LONG_S t1, THREAD_STATUS(a0)
	28	cpu_save_nonscratch a0
	29	LONG_S ra, THREAD_REG31(a0)
	30
a36d8225 DD	31	/*
	32	* check if we need to save FPU registers
	33	*/
	34	PTR_L t3, TASK_THREAD_INFO(a0)
	35	LONG_L t0, TI_FLAGS(t3)
	36	li t1, _TIF_USEDFPU
	37	and t2, t0, t1
	38	beqz t2, 1f
	39	nor t1, zero, t1
	40
	41	and t0, t0, t1
	42	LONG_S t0, TI_FLAGS(t3)
	43
	44	/*
	45	* clear saved user stack CU1 bit
	46	*/
	47	LONG_L t0, ST_OFF(t3)
	48	li t1, ~ST0_CU1
	49	and t0, t0, t1
	50	LONG_S t0, ST_OFF(t3)
	51
	52	.set push
	53	.set arch=mips64r2
	54	fpu_save_double a0 t0 t1 # c0_status passed in t0
	55	# clobbers t1
	56	.set pop
	57	1:
	58
	59	/* check if we need to save COP2 registers */
	60	PTR_L t2, TASK_THREAD_INFO(a0)
	61	LONG_L t0, ST_OFF(t2)
	62	bbit0 t0, 30, 1f
	63
	64	/* Disable COP2 in the stored process state */
	65	li t1, ST0_CU2
	66	xor t0, t1
	67	LONG_S t0, ST_OFF(t2)
	68
	69	/* Enable COP2 so we can save it */
	70	mfc0 t0, CP0_STATUS
	71	or t0, t1
	72	mtc0 t0, CP0_STATUS
	73
	74	/* Save COP2 */
	75	daddu a0, THREAD_CP2
	76	jal octeon_cop2_save
	77	dsubu a0, THREAD_CP2
	78
	79	/* Disable COP2 now that we are done */
	80	mfc0 t0, CP0_STATUS
	81	li t1, ST0_CU2
	82	xor t0, t1
	83	mtc0 t0, CP0_STATUS
	84
	85	1:
5b3b1688 DD	86	#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
5b3b1688 DD	87	/* Check if we need to store CVMSEG state */
70342287	88	mfc0 t0, $11,7 /* CvmMemCtl */
5b3b1688 DD	89	bbit0 t0, 6, 3f /* Is user access enabled? */
	90
	91	/* Store the CVMSEG state */
	92	/* Extract the size of CVMSEG */
	93	andi t0, 0x3f
	94	/* Multiply * (cache line size/sizeof(long)/2) */
	95	sll t0, 7-LONGLOG-1
70342287 RB	96	li t1, -32768 /* Base address of CVMSEG */
70342287 RB	97	LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
5b3b1688 DD	98	synciobdma
	99	2:
	100	.set noreorder
	101	LONG_L t8, 0(t1) /* Load from CVMSEG */
	102	subu t0, 1 /* Decrement loop var */
	103	LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
	104	LONG_ADDU t1, LONGSIZE2 / Increment loc in CVMSEG */
	105	LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
	106	LONG_ADDU t2, LONGSIZE2 / Increment loc in thread storage */
	107	bnez t0, 2b /* Loop until we've copied it all */
70342287	108	LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
5b3b1688 DD	109	.set reorder
	110
	111	/* Disable access to CVMSEG */
70342287	112	mfc0 t0, $11,7 /* CvmMemCtl */
5b3b1688	113	xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
70342287	114	mtc0 t0, $11,7 /* CvmMemCtl */
5b3b1688 DD	115	#endif
5b3b1688 DD	116	3:
1400eb65 GF	117
1400eb65 GF	118	#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
8b3c569a	119	PTR_LA t8, __stack_chk_guard
1400eb65 GF	120	LONG_L t9, TASK_STACK_CANARY(a1)
	121	LONG_S t9, 0(t8)
	122	#endif
	123
5b3b1688 DD	124	/*
	125	* The order of restoring the registers takes care of the race
	126	* updating $28, $29 and kernelsp without disabling ints.
	127	*/
	128	move $28, a2
	129	cpu_restore_nonscratch a1
	130
a36d8225	131	PTR_ADDU t0, $28, _THREAD_SIZE - 32
5b3b1688 DD	132	set_saved_sp t0, t1, t2
	133
	134	mfc0 t1, CP0_STATUS /* Do we really need this? */
	135	li a3, 0xff01
	136	and t1, a3
	137	LONG_L a2, THREAD_STATUS(a1)
	138	nor a3, $0, a3
	139	and a2, a3
	140	or a2, t1
	141	mtc0 a2, CP0_STATUS
	142	move v0, a0
	143	jr ra
	144	END(resume)
	145
	146	/*
	147	* void octeon_cop2_save(struct octeon_cop2_state *a0)
	148	*/
	149	.align 7
	150	LEAF(octeon_cop2_save)
	151
	152	dmfc0 t9, $9,7 /* CvmCtl register. */
	153
70342287	154	/* Save the COP2 CRC state */
5b3b1688 DD	155	dmfc2 t0, 0x0201
	156	dmfc2 t1, 0x0202
	157	dmfc2 t2, 0x0200
	158	sd t0, OCTEON_CP2_CRC_IV(a0)
	159	sd t1, OCTEON_CP2_CRC_LENGTH(a0)
	160	sd t2, OCTEON_CP2_CRC_POLY(a0)
	161	/* Skip next instructions if CvmCtl[NODFA_CP2] set */
	162	bbit1 t9, 28, 1f
	163
	164	/* Save the LLM state */
	165	dmfc2 t0, 0x0402
	166	dmfc2 t1, 0x040A
	167	sd t0, OCTEON_CP2_LLM_DAT(a0)
	168	sd t1, OCTEON_CP2_LLM_DAT+8(a0)
	169
70342287	170	1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
5b3b1688 DD	171
5b3b1688 DD	172	/* Save the COP2 crypto state */
70342287 RB	173	/* this part is mostly common to both pass 1 and later revisions */
	174	dmfc2 t0, 0x0084
	175	dmfc2 t1, 0x0080
	176	dmfc2 t2, 0x0081
	177	dmfc2 t3, 0x0082
5b3b1688	178	sd t0, OCTEON_CP2_3DES_IV(a0)
70342287	179	dmfc2 t0, 0x0088
5b3b1688	180	sd t1, OCTEON_CP2_3DES_KEY(a0)
70342287	181	dmfc2 t1, 0x0111 /* only necessary for pass 1 */
5b3b1688	182	sd t2, OCTEON_CP2_3DES_KEY+8(a0)
70342287	183	dmfc2 t2, 0x0102
5b3b1688	184	sd t3, OCTEON_CP2_3DES_KEY+16(a0)
70342287	185	dmfc2 t3, 0x0103
5b3b1688	186	sd t0, OCTEON_CP2_3DES_RESULT(a0)
70342287 RB	187	dmfc2 t0, 0x0104
	188	sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
	189	dmfc2 t1, 0x0105
5b3b1688 DD	190	sd t2, OCTEON_CP2_AES_IV(a0)
	191	dmfc2 t2, 0x0106
	192	sd t3, OCTEON_CP2_AES_IV+8(a0)
70342287	193	dmfc2 t3, 0x0107
5b3b1688 DD	194	sd t0, OCTEON_CP2_AES_KEY(a0)
	195	dmfc2 t0, 0x0110
	196	sd t1, OCTEON_CP2_AES_KEY+8(a0)
	197	dmfc2 t1, 0x0100
	198	sd t2, OCTEON_CP2_AES_KEY+16(a0)
	199	dmfc2 t2, 0x0101
	200	sd t3, OCTEON_CP2_AES_KEY+24(a0)
70342287	201	mfc0 t3, $15,0 /* Get the processor ID register */
5b3b1688 DD	202	sd t0, OCTEON_CP2_AES_KEYLEN(a0)
	203	li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
	204	sd t1, OCTEON_CP2_AES_RESULT(a0)
	205	sd t2, OCTEON_CP2_AES_RESULT+8(a0)
	206	/* Skip to the Pass1 version of the remainder of the COP2 state */
	207	beq t3, t0, 2f
	208
70342287	209	/* the non-pass1 state when !CvmCtl[NOCRYPTO] */
5b3b1688 DD	210	dmfc2 t1, 0x0240
	211	dmfc2 t2, 0x0241
	212	dmfc2 t3, 0x0242
	213	dmfc2 t0, 0x0243
	214	sd t1, OCTEON_CP2_HSH_DATW(a0)
	215	dmfc2 t1, 0x0244
	216	sd t2, OCTEON_CP2_HSH_DATW+8(a0)
	217	dmfc2 t2, 0x0245
	218	sd t3, OCTEON_CP2_HSH_DATW+16(a0)
	219	dmfc2 t3, 0x0246
	220	sd t0, OCTEON_CP2_HSH_DATW+24(a0)
	221	dmfc2 t0, 0x0247
	222	sd t1, OCTEON_CP2_HSH_DATW+32(a0)
	223	dmfc2 t1, 0x0248
	224	sd t2, OCTEON_CP2_HSH_DATW+40(a0)
	225	dmfc2 t2, 0x0249
	226	sd t3, OCTEON_CP2_HSH_DATW+48(a0)
	227	dmfc2 t3, 0x024A
	228	sd t0, OCTEON_CP2_HSH_DATW+56(a0)
	229	dmfc2 t0, 0x024B
	230	sd t1, OCTEON_CP2_HSH_DATW+64(a0)
	231	dmfc2 t1, 0x024C
	232	sd t2, OCTEON_CP2_HSH_DATW+72(a0)
	233	dmfc2 t2, 0x024D
	234	sd t3, OCTEON_CP2_HSH_DATW+80(a0)
70342287	235	dmfc2 t3, 0x024E
5b3b1688 DD	236	sd t0, OCTEON_CP2_HSH_DATW+88(a0)
	237	dmfc2 t0, 0x0250
	238	sd t1, OCTEON_CP2_HSH_DATW+96(a0)
	239	dmfc2 t1, 0x0251
	240	sd t2, OCTEON_CP2_HSH_DATW+104(a0)
	241	dmfc2 t2, 0x0252
	242	sd t3, OCTEON_CP2_HSH_DATW+112(a0)
	243	dmfc2 t3, 0x0253
	244	sd t0, OCTEON_CP2_HSH_IVW(a0)
	245	dmfc2 t0, 0x0254
	246	sd t1, OCTEON_CP2_HSH_IVW+8(a0)
	247	dmfc2 t1, 0x0255
	248	sd t2, OCTEON_CP2_HSH_IVW+16(a0)
	249	dmfc2 t2, 0x0256
	250	sd t3, OCTEON_CP2_HSH_IVW+24(a0)
	251	dmfc2 t3, 0x0257
	252	sd t0, OCTEON_CP2_HSH_IVW+32(a0)
70342287	253	dmfc2 t0, 0x0258
5b3b1688	254	sd t1, OCTEON_CP2_HSH_IVW+40(a0)
70342287	255	dmfc2 t1, 0x0259
5b3b1688 DD	256	sd t2, OCTEON_CP2_HSH_IVW+48(a0)
	257	dmfc2 t2, 0x025E
	258	sd t3, OCTEON_CP2_HSH_IVW+56(a0)
	259	dmfc2 t3, 0x025A
	260	sd t0, OCTEON_CP2_GFM_MULT(a0)
	261	dmfc2 t0, 0x025B
	262	sd t1, OCTEON_CP2_GFM_MULT+8(a0)
	263	sd t2, OCTEON_CP2_GFM_POLY(a0)
	264	sd t3, OCTEON_CP2_GFM_RESULT(a0)
	265	sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
	266	jr ra
	267
70342287	268	2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
5b3b1688 DD	269	dmfc2 t3, 0x0040
	270	dmfc2 t0, 0x0041
	271	dmfc2 t1, 0x0042
	272	dmfc2 t2, 0x0043
	273	sd t3, OCTEON_CP2_HSH_DATW(a0)
	274	dmfc2 t3, 0x0044
	275	sd t0, OCTEON_CP2_HSH_DATW+8(a0)
	276	dmfc2 t0, 0x0045
	277	sd t1, OCTEON_CP2_HSH_DATW+16(a0)
	278	dmfc2 t1, 0x0046
	279	sd t2, OCTEON_CP2_HSH_DATW+24(a0)
	280	dmfc2 t2, 0x0048
	281	sd t3, OCTEON_CP2_HSH_DATW+32(a0)
	282	dmfc2 t3, 0x0049
	283	sd t0, OCTEON_CP2_HSH_DATW+40(a0)
	284	dmfc2 t0, 0x004A
	285	sd t1, OCTEON_CP2_HSH_DATW+48(a0)
	286	sd t2, OCTEON_CP2_HSH_IVW(a0)
	287	sd t3, OCTEON_CP2_HSH_IVW+8(a0)
	288	sd t0, OCTEON_CP2_HSH_IVW+16(a0)
	289
70342287	290	3: /* pass 1 or CvmCtl[NOCRYPTO] set */
5b3b1688 DD	291	jr ra
	292	END(octeon_cop2_save)
	293
	294	/*
	295	* void octeon_cop2_restore(struct octeon_cop2_state *a0)
	296	*/
	297	.align 7
	298	.set push
	299	.set noreorder
	300	LEAF(octeon_cop2_restore)
70342287 RB	301	/* First cache line was prefetched before the call */
70342287 RB	302	pref 4, 128(a0)
5b3b1688 DD	303	dmfc0 t9, $9,7 /* CvmCtl register. */
5b3b1688 DD	304
70342287	305	pref 4, 256(a0)
5b3b1688	306	ld t0, OCTEON_CP2_CRC_IV(a0)
70342287	307	pref 4, 384(a0)
5b3b1688 DD	308	ld t1, OCTEON_CP2_CRC_LENGTH(a0)
	309	ld t2, OCTEON_CP2_CRC_POLY(a0)
	310
	311	/* Restore the COP2 CRC state */
	312	dmtc2 t0, 0x0201
70342287	313	dmtc2 t1, 0x1202
5b3b1688 DD	314	bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
	315	dmtc2 t2, 0x4200
	316
	317	/* Restore the LLM state */
	318	ld t0, OCTEON_CP2_LLM_DAT(a0)
	319	ld t1, OCTEON_CP2_LLM_DAT+8(a0)
	320	dmtc2 t0, 0x0402
	321	dmtc2 t1, 0x040A
	322
	323	2:
	324	bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
	325	nop
	326
	327	/* Restore the COP2 crypto state common to pass 1 and pass 2 */
	328	ld t0, OCTEON_CP2_3DES_IV(a0)
	329	ld t1, OCTEON_CP2_3DES_KEY(a0)
	330	ld t2, OCTEON_CP2_3DES_KEY+8(a0)
70342287	331	dmtc2 t0, 0x0084
5b3b1688	332	ld t0, OCTEON_CP2_3DES_KEY+16(a0)
70342287	333	dmtc2 t1, 0x0080
5b3b1688	334	ld t1, OCTEON_CP2_3DES_RESULT(a0)
70342287	335	dmtc2 t2, 0x0081
5b3b1688 DD	336	ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
	337	dmtc2 t0, 0x0082
	338	ld t0, OCTEON_CP2_AES_IV(a0)
70342287	339	dmtc2 t1, 0x0098
5b3b1688	340	ld t1, OCTEON_CP2_AES_IV+8(a0)
70342287	341	dmtc2 t2, 0x010A /* only really needed for pass 1 */
5b3b1688	342	ld t2, OCTEON_CP2_AES_KEY(a0)
70342287	343	dmtc2 t0, 0x0102
5b3b1688 DD	344	ld t0, OCTEON_CP2_AES_KEY+8(a0)
	345	dmtc2 t1, 0x0103
	346	ld t1, OCTEON_CP2_AES_KEY+16(a0)
	347	dmtc2 t2, 0x0104
	348	ld t2, OCTEON_CP2_AES_KEY+24(a0)
	349	dmtc2 t0, 0x0105
	350	ld t0, OCTEON_CP2_AES_KEYLEN(a0)
	351	dmtc2 t1, 0x0106
	352	ld t1, OCTEON_CP2_AES_RESULT(a0)
	353	dmtc2 t2, 0x0107
	354	ld t2, OCTEON_CP2_AES_RESULT+8(a0)
70342287	355	mfc0 t3, $15,0 /* Get the processor ID register */
5b3b1688 DD	356	dmtc2 t0, 0x0110
	357	li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
	358	dmtc2 t1, 0x0100
	359	bne t0, t3, 3f /* Skip the next stuff for non-pass1 */
	360	dmtc2 t2, 0x0101
	361
70342287	362	/* this code is specific for pass 1 */
5b3b1688 DD	363	ld t0, OCTEON_CP2_HSH_DATW(a0)
	364	ld t1, OCTEON_CP2_HSH_DATW+8(a0)
	365	ld t2, OCTEON_CP2_HSH_DATW+16(a0)
	366	dmtc2 t0, 0x0040
	367	ld t0, OCTEON_CP2_HSH_DATW+24(a0)
	368	dmtc2 t1, 0x0041
	369	ld t1, OCTEON_CP2_HSH_DATW+32(a0)
	370	dmtc2 t2, 0x0042
	371	ld t2, OCTEON_CP2_HSH_DATW+40(a0)
	372	dmtc2 t0, 0x0043
	373	ld t0, OCTEON_CP2_HSH_DATW+48(a0)
	374	dmtc2 t1, 0x0044
	375	ld t1, OCTEON_CP2_HSH_IVW(a0)
	376	dmtc2 t2, 0x0045
	377	ld t2, OCTEON_CP2_HSH_IVW+8(a0)
	378	dmtc2 t0, 0x0046
	379	ld t0, OCTEON_CP2_HSH_IVW+16(a0)
	380	dmtc2 t1, 0x0048
	381	dmtc2 t2, 0x0049
70342287	382	b done_restore /* unconditional branch */
5b3b1688 DD	383	dmtc2 t0, 0x004A
5b3b1688 DD	384
70342287	385	3: /* this is post-pass1 code */
5b3b1688 DD	386	ld t2, OCTEON_CP2_HSH_DATW(a0)
	387	ld t0, OCTEON_CP2_HSH_DATW+8(a0)
	388	ld t1, OCTEON_CP2_HSH_DATW+16(a0)
	389	dmtc2 t2, 0x0240
	390	ld t2, OCTEON_CP2_HSH_DATW+24(a0)
	391	dmtc2 t0, 0x0241
	392	ld t0, OCTEON_CP2_HSH_DATW+32(a0)
	393	dmtc2 t1, 0x0242
	394	ld t1, OCTEON_CP2_HSH_DATW+40(a0)
	395	dmtc2 t2, 0x0243
	396	ld t2, OCTEON_CP2_HSH_DATW+48(a0)
	397	dmtc2 t0, 0x0244
	398	ld t0, OCTEON_CP2_HSH_DATW+56(a0)
	399	dmtc2 t1, 0x0245
	400	ld t1, OCTEON_CP2_HSH_DATW+64(a0)
	401	dmtc2 t2, 0x0246
	402	ld t2, OCTEON_CP2_HSH_DATW+72(a0)
	403	dmtc2 t0, 0x0247
	404	ld t0, OCTEON_CP2_HSH_DATW+80(a0)
	405	dmtc2 t1, 0x0248
	406	ld t1, OCTEON_CP2_HSH_DATW+88(a0)
	407	dmtc2 t2, 0x0249
	408	ld t2, OCTEON_CP2_HSH_DATW+96(a0)
	409	dmtc2 t0, 0x024A
	410	ld t0, OCTEON_CP2_HSH_DATW+104(a0)
	411	dmtc2 t1, 0x024B
	412	ld t1, OCTEON_CP2_HSH_DATW+112(a0)
	413	dmtc2 t2, 0x024C
	414	ld t2, OCTEON_CP2_HSH_IVW(a0)
	415	dmtc2 t0, 0x024D
	416	ld t0, OCTEON_CP2_HSH_IVW+8(a0)
	417	dmtc2 t1, 0x024E
	418	ld t1, OCTEON_CP2_HSH_IVW+16(a0)
	419	dmtc2 t2, 0x0250
	420	ld t2, OCTEON_CP2_HSH_IVW+24(a0)
	421	dmtc2 t0, 0x0251
	422	ld t0, OCTEON_CP2_HSH_IVW+32(a0)
	423	dmtc2 t1, 0x0252
	424	ld t1, OCTEON_CP2_HSH_IVW+40(a0)
	425	dmtc2 t2, 0x0253
	426	ld t2, OCTEON_CP2_HSH_IVW+48(a0)
	427	dmtc2 t0, 0x0254
	428	ld t0, OCTEON_CP2_HSH_IVW+56(a0)
	429	dmtc2 t1, 0x0255
	430	ld t1, OCTEON_CP2_GFM_MULT(a0)
	431	dmtc2 t2, 0x0256
	432	ld t2, OCTEON_CP2_GFM_MULT+8(a0)
	433	dmtc2 t0, 0x0257
	434	ld t0, OCTEON_CP2_GFM_POLY(a0)
	435	dmtc2 t1, 0x0258
	436	ld t1, OCTEON_CP2_GFM_RESULT(a0)
	437	dmtc2 t2, 0x0259
	438	ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
	439	dmtc2 t0, 0x025E
	440	dmtc2 t1, 0x025A
	441	dmtc2 t2, 0x025B
	442
	443	done_restore:
	444	jr ra
	445	nop
	446	END(octeon_cop2_restore)
	447	.set pop
	448
	449	/*
450	* void octeon_mult_save()
451	* sp is assumed to point to a struct pt_regs
452	*
ac655fb7 DD	453	* NOTE: This is called in SAVE_TEMP in stackframe.h. It can
	454	* safely modify v1,k0, k1,$10-$15, and $24. It will
	455	* be overwritten with a processor specific version of the code.
5b3b1688	456	*/
ac655fb7	457	.p2align 7
5b3b1688 DD	458	.set push
	459	.set noreorder
	460	LEAF(octeon_mult_save)
ac655fb7	461	jr ra
5b3b1688	462	nop
ac655fb7 DD	463	.space 30 * 4, 0
	464	octeon_mult_save_end:
	465	EXPORT(octeon_mult_save_end)
	466	END(octeon_mult_save)
5b3b1688	467
ac655fb7 DD	468	LEAF(octeon_mult_save2)
ac655fb7 DD	469	/* Save the multiplier state OCTEON II and earlier*/
5b3b1688 DD	470	v3mulu k0, $0, $0
5b3b1688 DD	471	v3mulu k1, $0, $0
70342287	472	sd k0, PT_MTP(sp) /* PT_MTP has P0 */
5b3b1688 DD	473	v3mulu k0, $0, $0
	474	sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
	475	ori k1, $0, 1
	476	v3mulu k1, k1, $0
	477	sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
	478	v3mulu k0, $0, $0
70342287	479	sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
5b3b1688 DD	480	v3mulu k1, $0, $0
	481	sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
	482	jr ra
	483	sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
ac655fb7 DD	484	octeon_mult_save2_end:
	485	EXPORT(octeon_mult_save2_end)
	486	END(octeon_mult_save2)
	487
	488	LEAF(octeon_mult_save3)
	489	/* Save the multiplier state OCTEON III */
	490	v3mulu $10, $0, $0 /* read P0 */
	491	v3mulu $11, $0, $0 /* read P1 */
	492	v3mulu $12, $0, $0 /* read P2 */
	493	sd $10, PT_MTP+(08)(sp) / store P0 */
	494	v3mulu $10, $0, $0 /* read P3 */
	495	sd $11, PT_MTP+(18)(sp) / store P1 */
	496	v3mulu $11, $0, $0 /* read P4 */
	497	sd $12, PT_MTP+(28)(sp) / store P2 */
	498	ori $13, $0, 1
	499	v3mulu $12, $0, $0 /* read P5 */
	500	sd $10, PT_MTP+(38)(sp) / store P3 */
	501	v3mulu $13, $13, $0 /* P4-P0 = MPL5-MPL1, $13 = MPL0 */
	502	sd $11, PT_MTP+(48)(sp) / store P4 */
	503	v3mulu $10, $0, $0 /* read MPL1 */
	504	sd $12, PT_MTP+(58)(sp) / store P5 */
	505	v3mulu $11, $0, $0 /* read MPL2 */
	506	sd $13, PT_MPL+(08)(sp) / store MPL0 */
	507	v3mulu $12, $0, $0 /* read MPL3 */
	508	sd $10, PT_MPL+(18)(sp) / store MPL1 */
	509	v3mulu $10, $0, $0 /* read MPL4 */
	510	sd $11, PT_MPL+(28)(sp) / store MPL2 */
	511	v3mulu $11, $0, $0 /* read MPL5 */
	512	sd $12, PT_MPL+(38)(sp) / store MPL3 */
	513	sd $10, PT_MPL+(48)(sp) / store MPL4 */
5b3b1688	514	jr ra
ac655fb7 DD	515	sd $11, PT_MPL+(58)(sp) / store MPL5 */
	516	octeon_mult_save3_end:
	517	EXPORT(octeon_mult_save3_end)
	518	END(octeon_mult_save3)
5b3b1688 DD	519	.set pop
	520
	521	/*
	522	* void octeon_mult_restore()
	523	* sp is assumed to point to a struct pt_regs
	524	*
ac655fb7	525	* NOTE: This is called in RESTORE_TEMP in stackframe.h.
5b3b1688	526	*/
ac655fb7	527	.p2align 7
5b3b1688 DD	528	.set push
	529	.set noreorder
	530	LEAF(octeon_mult_restore)
ac655fb7 DD	531	jr ra
	532	nop
	533	.space 30 * 4, 0
	534	octeon_mult_restore_end:
	535	EXPORT(octeon_mult_restore_end)
	536	END(octeon_mult_restore)
5b3b1688	537
ac655fb7 DD	538	LEAF(octeon_mult_restore2)
	539	ld v0, PT_MPL(sp) /* MPL0 */
	540	ld v1, PT_MPL+8(sp) /* MPL1 */
	541	ld k0, PT_MPL+16(sp) /* MPL2 */
5b3b1688	542	/* Restore the multiplier state */
ac655fb7 DD	543	ld k1, PT_MTP+16(sp) /* P2 */
ac655fb7 DD	544	mtm0 v0 /* MPL0 */
5b3b1688	545	ld v0, PT_MTP+8(sp) /* P1 */
ac655fb7 DD	546	mtm1 v1 /* MPL1 */
	547	ld v1, PT_MTP(sp) /* P0 */
	548	mtm2 k0 /* MPL2 */
	549	mtp2 k1 /* P2 */
	550	mtp1 v0 /* P1 */
5b3b1688	551	jr ra
ac655fb7 DD	552	mtp0 v1 /* P0 */
	553	octeon_mult_restore2_end:
	554	EXPORT(octeon_mult_restore2_end)
	555	END(octeon_mult_restore2)
	556
	557	LEAF(octeon_mult_restore3)
	558	ld $12, PT_MPL+(08)(sp) / read MPL0 */
	559	ld $13, PT_MPL+(38)(sp) / read MPL3 */
	560	ld $10, PT_MPL+(18)(sp) / read MPL1 */
	561	ld $11, PT_MPL+(48)(sp) / read MPL4 */
	562	.word 0x718d0008
	563	/* mtm0 $12, $13 restore MPL0 and MPL3 */
	564	ld $12, PT_MPL+(28)(sp) / read MPL2 */
	565	.word 0x714b000c
	566	/* mtm1 $10, $11 restore MPL1 and MPL4 */
	567	ld $13, PT_MPL+(58)(sp) / read MPL5 */
	568	ld $10, PT_MTP+(08)(sp) / read P0 */
	569	ld $11, PT_MTP+(38)(sp) / read P3 */
	570	.word 0x718d000d
	571	/* mtm2 $12, $13 restore MPL2 and MPL5 */
	572	ld $12, PT_MTP+(18)(sp) / read P1 */
	573	.word 0x714b0009
	574	/* mtp0 $10, $11 restore P0 and P3 */
	575	ld $13, PT_MTP+(48)(sp) / read P4 */
	576	ld $10, PT_MTP+(28)(sp) / read P2 */
	577	ld $11, PT_MTP+(58)(sp) / read P5 */
	578	.word 0x718d000a
	579	/* mtp1 $12, $13 restore P1 and P4 */
5b3b1688	580	jr ra
ac655fb7 DD	581	.word 0x714b000b
	582	/* mtp2 $10, $11 restore P2 and P5 */
	583
	584	octeon_mult_restore3_end:
	585	EXPORT(octeon_mult_restore3_end)
	586	END(octeon_mult_restore3)
5b3b1688	587	.set pop