[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2
[deliverable/linux.git] / arch / mips / kernel / proc.c
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1/*
2 * linux/arch/mips/kernel/proc.c
3 *
4 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
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5 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
6 * Copyright (C) 2004 Maciej W. Rozycki
1da177e4 7 */
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8#include <linux/delay.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/seq_file.h>
12#include <asm/bootinfo.h>
13#include <asm/cpu.h>
14#include <asm/cpu-features.h>
15#include <asm/mipsregs.h>
16#include <asm/processor.h>
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17
18unsigned int vced_count, vcei_count;
19
20static const char *cpu_name[] = {
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21 [CPU_UNKNOWN] = "unknown",
22 [CPU_R2000] = "R2000",
23 [CPU_R3000] = "R3000",
24 [CPU_R3000A] = "R3000A",
25 [CPU_R3041] = "R3041",
26 [CPU_R3051] = "R3051",
27 [CPU_R3052] = "R3052",
28 [CPU_R3081] = "R3081",
29 [CPU_R3081E] = "R3081E",
30 [CPU_R4000PC] = "R4000PC",
31 [CPU_R4000SC] = "R4000SC",
32 [CPU_R4000MC] = "R4000MC",
e0daad44 33 [CPU_R4200] = "R4200",
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34 [CPU_R4400PC] = "R4400PC",
35 [CPU_R4400SC] = "R4400SC",
36 [CPU_R4400MC] = "R4400MC",
37 [CPU_R4600] = "R4600",
38 [CPU_R6000] = "R6000",
e0daad44 39 [CPU_R6000A] = "R6000A",
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40 [CPU_R8000] = "R8000",
41 [CPU_R10000] = "R10000",
42 [CPU_R12000] = "R12000",
44d921b2 43 [CPU_R14000] = "R14000",
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44 [CPU_R4300] = "R4300",
45 [CPU_R4650] = "R4650",
46 [CPU_R4700] = "R4700",
47 [CPU_R5000] = "R5000",
e0daad44 48 [CPU_R5000A] = "R5000A",
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49 [CPU_R4640] = "R4640",
50 [CPU_NEVADA] = "Nevada",
51 [CPU_RM7000] = "RM7000",
52 [CPU_RM9000] = "RM9000",
53 [CPU_R5432] = "R5432",
54 [CPU_4KC] = "MIPS 4Kc",
e0daad44 55 [CPU_5KC] = "MIPS 5Kc",
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56 [CPU_R4310] = "R4310",
57 [CPU_SB1] = "SiByte SB1",
93ce2f52 58 [CPU_SB1A] = "SiByte SB1A",
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59 [CPU_TX3912] = "TX3912",
60 [CPU_TX3922] = "TX3922",
61 [CPU_TX3927] = "TX3927",
62 [CPU_AU1000] = "Au1000",
63 [CPU_AU1500] = "Au1500",
64 [CPU_AU1100] = "Au1100",
65 [CPU_AU1550] = "Au1550",
66 [CPU_AU1200] = "Au1200",
67 [CPU_4KEC] = "MIPS 4KEc",
68 [CPU_4KSC] = "MIPS 4KSc",
69 [CPU_VR41XX] = "NEC Vr41xx",
70 [CPU_R5500] = "R5500",
71 [CPU_TX49XX] = "TX49xx",
72 [CPU_20KC] = "MIPS 20Kc",
73 [CPU_24K] = "MIPS 24K",
74 [CPU_25KF] = "MIPS 25Kf",
bbc7f22f 75 [CPU_34K] = "MIPS 34K",
c620953c 76 [CPU_74K] = "MIPS 74K",
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77 [CPU_VR4111] = "NEC VR4111",
78 [CPU_VR4121] = "NEC VR4121",
79 [CPU_VR4122] = "NEC VR4122",
80 [CPU_VR4131] = "NEC VR4131",
81 [CPU_VR4133] = "NEC VR4133",
82 [CPU_VR4181] = "NEC VR4181",
83 [CPU_VR4181A] = "NEC VR4181A",
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84 [CPU_SR71000] = "Sandcraft SR71000",
85 [CPU_PR4450] = "Philips PR4450",
2a21c730 86 [CPU_LOONGSON2] = "ICT Loongson-2",
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87};
88
89
90static int show_cpuinfo(struct seq_file *m, void *v)
91{
1da177e4 92 unsigned long n = (unsigned long) v - 1;
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93 unsigned int version = cpu_data[n].processor_id;
94 unsigned int fp_vers = cpu_data[n].fpu_id;
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95 char fmt [64];
96
97#ifdef CONFIG_SMP
98 if (!cpu_isset(n, cpu_online_map))
99 return 0;
100#endif
101
102 /*
103 * For the first processor also print the system type
104 */
105 if (n == 0)
106 seq_printf(m, "system type\t\t: %s\n", get_system_type());
107
108 seq_printf(m, "processor\t\t: %ld\n", n);
109 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
e04582b7 110 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
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111 seq_printf(m, fmt, cpu_name[cpu_data[n].cputype <= CPU_LAST ?
112 cpu_data[n].cputype : CPU_UNKNOWN],
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113 (version >> 4) & 0x0f, version & 0x0f,
114 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
115 seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
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116 cpu_data[n].udelay_val / (500000/HZ),
117 (cpu_data[n].udelay_val / (5000/HZ)) % 100);
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118 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
119 seq_printf(m, "microsecond timers\t: %s\n",
120 cpu_has_counter ? "yes" : "no");
31aa3665 121 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
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122 seq_printf(m, "extra interrupt vector\t: %s\n",
123 cpu_has_divec ? "yes" : "no");
124 seq_printf(m, "hardware watchpoint\t: %s\n",
125 cpu_has_watch ? "yes" : "no");
e027802e 126 seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
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127 cpu_has_mips16 ? " mips16" : "",
128 cpu_has_mdmx ? " mdmx" : "",
129 cpu_has_mips3d ? " mips3d" : "",
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130 cpu_has_smartmips ? " smartmips" : "",
131 cpu_has_dsp ? " dsp" : "",
132 cpu_has_mipsmt ? " mt" : ""
133 );
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134
135 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
136 cpu_has_vce ? "%u" : "not available");
137 seq_printf(m, fmt, 'D', vced_count);
138 seq_printf(m, fmt, 'I', vcei_count);
17256052 139 seq_printf(m, "\n");
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140
141 return 0;
142}
143
144static void *c_start(struct seq_file *m, loff_t *pos)
145{
146 unsigned long i = *pos;
147
148 return i < NR_CPUS ? (void *) (i + 1) : NULL;
149}
150
151static void *c_next(struct seq_file *m, void *v, loff_t *pos)
152{
153 ++*pos;
154 return c_start(m, pos);
155}
156
157static void c_stop(struct seq_file *m, void *v)
158{
159}
160
161struct seq_operations cpuinfo_op = {
162 .start = c_start,
163 .next = c_next,
164 .stop = c_stop,
165 .show = show_cpuinfo,
166};
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