[deliverable/linux.git] / arch / mips / kernel / ptrace.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 Ross Biro
 * Copyright (C) Linus Torvalds
 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
 * Copyright (C) 1996 David S. Miller
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 1999 MIPS Technologies, Inc.
 * Copyright (C) 2000 Ulf Carlsson
 *
 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
 * binaries.
 */
#include <linux/compiler.h>
#include <linux/context_tracking.h>
#include <linux/elf.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
#include <linux/regset.h>
#include <linux/smp.h>
#include <linux/user.h>
#include <linux/security.h>
#include <linux/tracehook.h>
#include <linux/audit.h>
#include <linux/seccomp.h>
#include <linux/ftrace.h>

#include <asm/byteorder.h>
#include <asm/cpu.h>
#include <asm/dsp.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/syscall.h>
#include <asm/uaccess.h>
#include <asm/bootinfo.h>
#include <asm/reg.h>

#define CREATE_TRACE_POINTS
#include <trace/events/syscalls.h>

/*
 * Called by kernel/ptrace.c when detaching..
 *
 * Make sure single step bits etc are not set.
 */
void ptrace_disable(struct task_struct *child)
{
	/* Don't load the watchpoint registers for the ex-child. */
	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
}

/*
 * Read a general register set.	 We always use the 64-bit format, even
 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
 * Registers are sign extended to fill the available space.
 */
int ptrace_getregs(struct task_struct *child, __s64 __user *data)
{
	struct pt_regs *regs;
	int i;

	if (!access_ok(VERIFY_WRITE, data, 38 * 8))
		return -EIO;

	regs = task_pt_regs(child);

	for (i = 0; i < 32; i++)
		__put_user((long)regs->regs[i], data + i);
	__put_user((long)regs->lo, data + EF_LO - EF_R0);
	__put_user((long)regs->hi, data + EF_HI - EF_R0);
	__put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
	__put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
	__put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
	__put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);

	return 0;
}

/*
 * Write a general register set.  As for PTRACE_GETREGS, we always use
 * the 64-bit format.  On a 32-bit kernel only the lower order half
 * (according to endianness) will be used.
 */
int ptrace_setregs(struct task_struct *child, __s64 __user *data)
{
	struct pt_regs *regs;
	int i;

	if (!access_ok(VERIFY_READ, data, 38 * 8))
		return -EIO;

	regs = task_pt_regs(child);

	for (i = 0; i < 32; i++)
		__get_user(regs->regs[i], data + i);
	__get_user(regs->lo, data + EF_LO - EF_R0);
	__get_user(regs->hi, data + EF_HI - EF_R0);
	__get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);

	/* badvaddr, status, and cause may not be written.  */

	return 0;
}

int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
{
	int i;
	unsigned int tmp;

	if (!access_ok(VERIFY_WRITE, data, 33 * 8))
		return -EIO;

	if (tsk_used_math(child)) {
		fpureg_t *fregs = get_fpu_regs(child);
		for (i = 0; i < 32; i++)
			__put_user(fregs[i], i + (__u64 __user *) data);
	} else {
		for (i = 0; i < 32; i++)
			__put_user((__u64) -1, i + (__u64 __user *) data);
	}

	__put_user(child->thread.fpu.fcr31, data + 64);

	preempt_disable();
	if (cpu_has_fpu) {
		unsigned int flags;

		if (cpu_has_mipsmt) {
			unsigned int vpflags = dvpe();
			flags = read_c0_status();
			__enable_fpu(FPU_AS_IS);
			__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
			write_c0_status(flags);
			evpe(vpflags);
		} else {
			flags = read_c0_status();
			__enable_fpu(FPU_AS_IS);
			__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
			write_c0_status(flags);
		}
	} else {
		tmp = 0;
	}
	preempt_enable();
	__put_user(tmp, data + 65);

	return 0;
}

int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
{
	fpureg_t *fregs;
	int i;

	if (!access_ok(VERIFY_READ, data, 33 * 8))
		return -EIO;

	fregs = get_fpu_regs(child);

	for (i = 0; i < 32; i++)
		__get_user(fregs[i], i + (__u64 __user *) data);

	__get_user(child->thread.fpu.fcr31, data + 64);

	/* FIR may not be written.  */

	return 0;
}

int ptrace_get_watch_regs(struct task_struct *child,
			  struct pt_watch_regs __user *addr)
{
	enum pt_watch_style style;
	int i;

	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
		return -EIO;
	if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
		return -EIO;

#ifdef CONFIG_32BIT
	style = pt_watch_style_mips32;
#define WATCH_STYLE mips32
#else
	style = pt_watch_style_mips64;
#define WATCH_STYLE mips64
#endif

	__put_user(style, &addr->style);
	__put_user(current_cpu_data.watch_reg_use_cnt,
		   &addr->WATCH_STYLE.num_valid);
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		__put_user(child->thread.watch.mips3264.watchlo[i],
			   &addr->WATCH_STYLE.watchlo[i]);
		__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
			   &addr->WATCH_STYLE.watchhi[i]);
		__put_user(current_cpu_data.watch_reg_masks[i],
			   &addr->WATCH_STYLE.watch_masks[i]);
	}
	for (; i < 8; i++) {
		__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
		__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
		__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
	}

	return 0;
}

int ptrace_set_watch_regs(struct task_struct *child,
			  struct pt_watch_regs __user *addr)
{
	int i;
	int watch_active = 0;
	unsigned long lt[NUM_WATCH_REGS];
	u16 ht[NUM_WATCH_REGS];

	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
		return -EIO;
	if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
		return -EIO;
	/* Check the values. */
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
#ifdef CONFIG_32BIT
		if (lt[i] & __UA_LIMIT)
			return -EINVAL;
#else
		if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
			if (lt[i] & 0xffffffff80000000UL)
				return -EINVAL;
		} else {
			if (lt[i] & __UA_LIMIT)
				return -EINVAL;
		}
#endif
		__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
		if (ht[i] & ~0xff8)
			return -EINVAL;
	}
	/* Install them. */
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		if (lt[i] & 7)
			watch_active = 1;
		child->thread.watch.mips3264.watchlo[i] = lt[i];
		/* Set the G bit. */
		child->thread.watch.mips3264.watchhi[i] = ht[i];
	}

	if (watch_active)
		set_tsk_thread_flag(child, TIF_LOAD_WATCH);
	else
		clear_tsk_thread_flag(child, TIF_LOAD_WATCH);

	return 0;
}

/* regset get/set implementations */

static int gpr_get(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   void *kbuf, void __user *ubuf)
{
	struct pt_regs *regs = task_pt_regs(target);

	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
				   regs, 0, sizeof(*regs));
}

static int gpr_set(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   const void *kbuf, const void __user *ubuf)
{
	struct pt_regs newregs;
	int ret;

	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
				 &newregs,
				 0, sizeof(newregs));
	if (ret)
		return ret;

	*task_pt_regs(target) = newregs;

	return 0;
}

static int fpr_get(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   void *kbuf, void __user *ubuf)
{
	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
				   &target->thread.fpu,
				   0, sizeof(elf_fpregset_t));
	/* XXX fcr31  */
}

static int fpr_set(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   const void *kbuf, const void __user *ubuf)
{
	return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
				  &target->thread.fpu,
				  0, sizeof(elf_fpregset_t));
	/* XXX fcr31  */
}

enum mips_regset {
	REGSET_GPR,
	REGSET_FPR,
};

static const struct user_regset mips_regsets[] = {
	[REGSET_GPR] = {
		.core_note_type	= NT_PRSTATUS,
		.n		= ELF_NGREG,
		.size		= sizeof(unsigned int),
		.align		= sizeof(unsigned int),
		.get		= gpr_get,
		.set		= gpr_set,
	},
	[REGSET_FPR] = {
		.core_note_type	= NT_PRFPREG,
		.n		= ELF_NFPREG,
		.size		= sizeof(elf_fpreg_t),
		.align		= sizeof(elf_fpreg_t),
		.get		= fpr_get,
		.set		= fpr_set,
	},
};

static const struct user_regset_view user_mips_view = {
	.name		= "mips",
	.e_machine	= ELF_ARCH,
	.ei_osabi	= ELF_OSABI,
	.regsets	= mips_regsets,
	.n		= ARRAY_SIZE(mips_regsets),
};

static const struct user_regset mips64_regsets[] = {
	[REGSET_GPR] = {
		.core_note_type	= NT_PRSTATUS,
		.n		= ELF_NGREG,
		.size		= sizeof(unsigned long),
		.align		= sizeof(unsigned long),
		.get		= gpr_get,
		.set		= gpr_set,
	},
	[REGSET_FPR] = {
		.core_note_type	= NT_PRFPREG,
		.n		= ELF_NFPREG,
		.size		= sizeof(elf_fpreg_t),
		.align		= sizeof(elf_fpreg_t),
		.get		= fpr_get,
		.set		= fpr_set,
	},
};

static const struct user_regset_view user_mips64_view = {
	.name		= "mips",
	.e_machine	= ELF_ARCH,
	.ei_osabi	= ELF_OSABI,
	.regsets	= mips64_regsets,
	.n		= ARRAY_SIZE(mips_regsets),
};

const struct user_regset_view *task_user_regset_view(struct task_struct *task)
{
#ifdef CONFIG_32BIT
	return &user_mips_view;
#endif

#ifdef CONFIG_MIPS32_O32
		if (test_thread_flag(TIF_32BIT_REGS))
			return &user_mips_view;
#endif

	return &user_mips64_view;
}

long arch_ptrace(struct task_struct *child, long request,
		 unsigned long addr, unsigned long data)
{
	int ret;
	void __user *addrp = (void __user *) addr;
	void __user *datavp = (void __user *) data;
	unsigned long __user *datalp = (void __user *) data;

	switch (request) {
	/* when I and D space are separate, these will need to be fixed. */
	case PTRACE_PEEKTEXT: /* read word at location addr. */
	case PTRACE_PEEKDATA:
		ret = generic_ptrace_peekdata(child, addr, data);
		break;

	/* Read the word at location addr in the USER area. */
	case PTRACE_PEEKUSR: {
		struct pt_regs *regs;
		fpureg_t *fregs;
		unsigned long tmp = 0;

		regs = task_pt_regs(child);
		ret = 0;  /* Default return value. */

		switch (addr) {
		case 0 ... 31:
			tmp = regs->regs[addr];
			break;
		case FPR_BASE ... FPR_BASE + 31:
			if (!tsk_used_math(child)) {
				/* FP not yet used */
				tmp = -1;
				break;
			}
			fregs = get_fpu_regs(child);

#ifdef CONFIG_32BIT
			if (test_thread_flag(TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				if (addr & 1)
					tmp = fregs[(addr & ~1) - 32] >> 32;
				else
					tmp = fregs[addr - 32];
				break;
			}
#endif
			tmp = fregs[addr - FPR_BASE];
			break;
		case PC:
			tmp = regs->cp0_epc;
			break;
		case CAUSE:
			tmp = regs->cp0_cause;
			break;
		case BADVADDR:
			tmp = regs->cp0_badvaddr;
			break;
		case MMHI:
			tmp = regs->hi;
			break;
		case MMLO:
			tmp = regs->lo;
			break;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
		case ACX:
			tmp = regs->acx;
			break;
#endif
		case FPC_CSR:
			tmp = child->thread.fpu.fcr31;
			break;
		case FPC_EIR: { /* implementation / version register */
			unsigned int flags;
#ifdef CONFIG_MIPS_MT_SMTC
			unsigned long irqflags;
			unsigned int mtflags;
#endif /* CONFIG_MIPS_MT_SMTC */

			preempt_disable();
			if (!cpu_has_fpu) {
				preempt_enable();
				break;
			}

#ifdef CONFIG_MIPS_MT_SMTC
			/* Read-modify-write of Status must be atomic */
			local_irq_save(irqflags);
			mtflags = dmt();
#endif /* CONFIG_MIPS_MT_SMTC */
			if (cpu_has_mipsmt) {
				unsigned int vpflags = dvpe();
				flags = read_c0_status();
				__enable_fpu(FPU_AS_IS);
				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
				write_c0_status(flags);
				evpe(vpflags);
			} else {
				flags = read_c0_status();
				__enable_fpu(FPU_AS_IS);
				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
				write_c0_status(flags);
			}
#ifdef CONFIG_MIPS_MT_SMTC
			emt(mtflags);
			local_irq_restore(irqflags);
#endif /* CONFIG_MIPS_MT_SMTC */
			preempt_enable();
			break;
		}
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			dregs = __get_dsp_regs(child);
			tmp = (unsigned long) (dregs[addr - DSP_BASE]);
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			tmp = child->thread.dsp.dspcontrol;
			break;
		default:
			tmp = 0;
			ret = -EIO;
			goto out;
		}
		ret = put_user(tmp, datalp);
		break;
	}

	/* when I and D space are separate, this will have to be fixed. */
	case PTRACE_POKETEXT: /* write the word at location addr. */
	case PTRACE_POKEDATA:
		ret = generic_ptrace_pokedata(child, addr, data);
		break;

	case PTRACE_POKEUSR: {
		struct pt_regs *regs;
		ret = 0;
		regs = task_pt_regs(child);

		switch (addr) {
		case 0 ... 31:
			regs->regs[addr] = data;
			break;
		case FPR_BASE ... FPR_BASE + 31: {
			fpureg_t *fregs = get_fpu_regs(child);

			if (!tsk_used_math(child)) {
				/* FP not yet used  */
				memset(&child->thread.fpu, ~0,
				       sizeof(child->thread.fpu));
				child->thread.fpu.fcr31 = 0;
			}
#ifdef CONFIG_32BIT
			if (test_thread_flag(TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				if (addr & 1) {
					fregs[(addr & ~1) - FPR_BASE] &=
						0xffffffff;
					fregs[(addr & ~1) - FPR_BASE] |=
						((u64)data) << 32;
				} else {
					fregs[addr - FPR_BASE] &= ~0xffffffffLL;
					fregs[addr - FPR_BASE] |= data;
				}
				break;
			}
#endif
			fregs[addr - FPR_BASE] = data;
			break;
		}
		case PC:
			regs->cp0_epc = data;
			break;
		case MMHI:
			regs->hi = data;
			break;
		case MMLO:
			regs->lo = data;
			break;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
		case ACX:
			regs->acx = data;
			break;
#endif
		case FPC_CSR:
			child->thread.fpu.fcr31 = data;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}

			dregs = __get_dsp_regs(child);
			dregs[addr - DSP_BASE] = data;
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}
			child->thread.dsp.dspcontrol = data;
			break;
		default:
			/* The rest are not allowed. */
			ret = -EIO;
			break;
		}
		break;
		}

	case PTRACE_GETREGS:
		ret = ptrace_getregs(child, datavp);
		break;

	case PTRACE_SETREGS:
		ret = ptrace_setregs(child, datavp);
		break;

	case PTRACE_GETFPREGS:
		ret = ptrace_getfpregs(child, datavp);
		break;

	case PTRACE_SETFPREGS:
		ret = ptrace_setfpregs(child, datavp);
		break;

	case PTRACE_GET_THREAD_AREA:
		ret = put_user(task_thread_info(child)->tp_value, datalp);
		break;

	case PTRACE_GET_WATCH_REGS:
		ret = ptrace_get_watch_regs(child, addrp);
		break;

	case PTRACE_SET_WATCH_REGS:
		ret = ptrace_set_watch_regs(child, addrp);
		break;

	default:
		ret = ptrace_request(child, request, addr, data);
		break;
	}
 out:
	return ret;
}

/*
 * Notification of system call entry/exit
 * - triggered by current->work.syscall_trace
 */
asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
{
	long ret = 0;
	user_exit();

	if (secure_computing(syscall) == -1)
		return -1;

	if (test_thread_flag(TIF_SYSCALL_TRACE) &&
	    tracehook_report_syscall_entry(regs))
		ret = -1;

	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
		trace_sys_enter(regs, regs->regs[2]);

	audit_syscall_entry(syscall_get_arch(current, regs),
			    syscall,
			    regs->regs[4], regs->regs[5],
			    regs->regs[6], regs->regs[7]);
	return syscall;
}

/*
 * Notification of system call entry/exit
 * - triggered by current->work.syscall_trace
 */
asmlinkage void syscall_trace_leave(struct pt_regs *regs)
{
        /*
	 * We may come here right after calling schedule_user()
	 * or do_notify_resume(), in which case we can be in RCU
	 * user mode.
	 */
	user_exit();

	audit_syscall_exit(regs);

	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
		trace_sys_exit(regs, regs->regs[2]);

	if (test_thread_flag(TIF_SYSCALL_TRACE))
		tracehook_report_syscall_exit(regs, 0);

	user_enter();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1992 Ross Biro
	7	* Copyright (C) Linus Torvalds
	8	* Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
	9	* Copyright (C) 1996 David S. Miller
	10	* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	11	* Copyright (C) 1999 MIPS Technologies, Inc.
	12	* Copyright (C) 2000 Ulf Carlsson
	13	*
	14	* At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
	15	* binaries.
	16	*/
1da177e4	17	#include <linux/compiler.h>
c3fc5cd5	18	#include <linux/context_tracking.h>
7aeb753b	19	#include <linux/elf.h>
1da177e4 LT	20	#include <linux/kernel.h>
	21	#include <linux/sched.h>
	22	#include <linux/mm.h>
	23	#include <linux/errno.h>
	24	#include <linux/ptrace.h>
7aeb753b	25	#include <linux/regset.h>
1da177e4	26	#include <linux/smp.h>
1da177e4 LT	27	#include <linux/user.h>
1da177e4 LT	28	#include <linux/security.h>
bc3d22c1	29	#include <linux/tracehook.h>
293c5bd1 RB	30	#include <linux/audit.h>
293c5bd1 RB	31	#include <linux/seccomp.h>
1d7bf993	32	#include <linux/ftrace.h>
1da177e4	33
f8280c8d	34	#include <asm/byteorder.h>
1da177e4	35	#include <asm/cpu.h>
e50c0a8f	36	#include <asm/dsp.h>
1da177e4 LT	37	#include <asm/fpu.h>
1da177e4 LT	38	#include <asm/mipsregs.h>
101b3531	39	#include <asm/mipsmtregs.h>
1da177e4 LT	40	#include <asm/pgtable.h>
1da177e4 LT	41	#include <asm/page.h>
bec9b2b2	42	#include <asm/syscall.h>
1da177e4 LT	43	#include <asm/uaccess.h>
1da177e4 LT	44	#include <asm/bootinfo.h>
ea3d710f	45	#include <asm/reg.h>
1da177e4	46
1d7bf993 RB	47	#define CREATE_TRACE_POINTS
	48	#include <trace/events/syscalls.h>
	49
1da177e4 LT	50	/*
	51	* Called by kernel/ptrace.c when detaching..
	52	*
	53	* Make sure single step bits etc are not set.
	54	*/
	55	void ptrace_disable(struct task_struct *child)
	56	{
0926bf95 DD	57	/* Don't load the watchpoint registers for the ex-child. */
0926bf95 DD	58	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
1da177e4 LT	59	}
1da177e4 LT	60
ea3d710f	61	/*
70342287	62	* Read a general register set. We always use the 64-bit format, even
ea3d710f DJ	63	* for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
	64	* Registers are sign extended to fill the available space.
	65	*/
49a89efb	66	int ptrace_getregs(struct task_struct child, __s64 __user data)
ea3d710f DJ	67	{
	68	struct pt_regs *regs;
	69	int i;
	70
	71	if (!access_ok(VERIFY_WRITE, data, 38 * 8))
	72	return -EIO;
	73
40bc9c67	74	regs = task_pt_regs(child);
ea3d710f DJ	75
ea3d710f DJ	76	for (i = 0; i < 32; i++)
62b14c24 AN	77	__put_user((long)regs->regs[i], data + i);
	78	__put_user((long)regs->lo, data + EF_LO - EF_R0);
	79	__put_user((long)regs->hi, data + EF_HI - EF_R0);
	80	__put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
	81	__put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
	82	__put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
	83	__put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
ea3d710f DJ	84
	85	return 0;
	86	}
	87
	88	/*
	89	* Write a general register set. As for PTRACE_GETREGS, we always use
	90	* the 64-bit format. On a 32-bit kernel only the lower order half
	91	* (according to endianness) will be used.
	92	*/
49a89efb	93	int ptrace_setregs(struct task_struct child, __s64 __user data)
ea3d710f DJ	94	{
	95	struct pt_regs *regs;
	96	int i;
	97
	98	if (!access_ok(VERIFY_READ, data, 38 * 8))
	99	return -EIO;
	100
40bc9c67	101	regs = task_pt_regs(child);
ea3d710f DJ	102
ea3d710f DJ	103	for (i = 0; i < 32; i++)
49a89efb RB	104	__get_user(regs->regs[i], data + i);
	105	__get_user(regs->lo, data + EF_LO - EF_R0);
	106	__get_user(regs->hi, data + EF_HI - EF_R0);
	107	__get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
ea3d710f DJ	108
	109	/* badvaddr, status, and cause may not be written. */
	110
	111	return 0;
	112	}
	113
49a89efb	114	int ptrace_getfpregs(struct task_struct child, __u32 __user data)
ea3d710f DJ	115	{
ea3d710f DJ	116	int i;
e04582b7	117	unsigned int tmp;
ea3d710f DJ	118
	119	if (!access_ok(VERIFY_WRITE, data, 33 * 8))
	120	return -EIO;
	121
	122	if (tsk_used_math(child)) {
	123	fpureg_t *fregs = get_fpu_regs(child);
	124	for (i = 0; i < 32; i++)
49a89efb	125	__put_user(fregs[i], i + (__u64 __user *) data);
ea3d710f DJ	126	} else {
ea3d710f DJ	127	for (i = 0; i < 32; i++)
49a89efb	128	__put_user((__u64) -1, i + (__u64 __user *) data);
ea3d710f DJ	129	}
ea3d710f DJ	130
49a89efb	131	__put_user(child->thread.fpu.fcr31, data + 64);
eae89076	132
e04582b7	133	preempt_disable();
ea3d710f	134	if (cpu_has_fpu) {
e04582b7	135	unsigned int flags;
ea3d710f	136
101b3531 RB	137	if (cpu_has_mipsmt) {
	138	unsigned int vpflags = dvpe();
	139	flags = read_c0_status();
597ce172	140	__enable_fpu(FPU_AS_IS);
101b3531 RB	141	__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
	142	write_c0_status(flags);
	143	evpe(vpflags);
	144	} else {
	145	flags = read_c0_status();
597ce172	146	__enable_fpu(FPU_AS_IS);
101b3531 RB	147	__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
	148	write_c0_status(flags);
	149	}
ea3d710f	150	} else {
e04582b7	151	tmp = 0;
ea3d710f	152	}
e04582b7	153	preempt_enable();
49a89efb	154	__put_user(tmp, data + 65);
ea3d710f DJ	155
	156	return 0;
	157	}
	158
49a89efb	159	int ptrace_setfpregs(struct task_struct child, __u32 __user data)
ea3d710f DJ	160	{
	161	fpureg_t *fregs;
	162	int i;
	163
	164	if (!access_ok(VERIFY_READ, data, 33 * 8))
	165	return -EIO;
	166
	167	fregs = get_fpu_regs(child);
	168
	169	for (i = 0; i < 32; i++)
49a89efb	170	__get_user(fregs[i], i + (__u64 __user *) data);
ea3d710f	171
49a89efb	172	__get_user(child->thread.fpu.fcr31, data + 64);
ea3d710f DJ	173
	174	/* FIR may not be written. */
	175
	176	return 0;
	177	}
	178
0926bf95 DD	179	int ptrace_get_watch_regs(struct task_struct *child,
	180	struct pt_watch_regs __user *addr)
	181	{
	182	enum pt_watch_style style;
	183	int i;
	184
	185	if (!cpu_has_watch \|\| current_cpu_data.watch_reg_use_cnt == 0)
	186	return -EIO;
	187	if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
	188	return -EIO;
	189
	190	#ifdef CONFIG_32BIT
	191	style = pt_watch_style_mips32;
	192	#define WATCH_STYLE mips32
	193	#else
	194	style = pt_watch_style_mips64;
	195	#define WATCH_STYLE mips64
	196	#endif
	197
	198	__put_user(style, &addr->style);
	199	__put_user(current_cpu_data.watch_reg_use_cnt,
	200	&addr->WATCH_STYLE.num_valid);
	201	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
	202	__put_user(child->thread.watch.mips3264.watchlo[i],
	203	&addr->WATCH_STYLE.watchlo[i]);
	204	__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
	205	&addr->WATCH_STYLE.watchhi[i]);
	206	__put_user(current_cpu_data.watch_reg_masks[i],
	207	&addr->WATCH_STYLE.watch_masks[i]);
	208	}
	209	for (; i < 8; i++) {
	210	__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
	211	__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
	212	__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
	213	}
	214
	215	return 0;
	216	}
	217
	218	int ptrace_set_watch_regs(struct task_struct *child,
	219	struct pt_watch_regs __user *addr)
	220	{
	221	int i;
	222	int watch_active = 0;
	223	unsigned long lt[NUM_WATCH_REGS];
	224	u16 ht[NUM_WATCH_REGS];
	225
	226	if (!cpu_has_watch \|\| current_cpu_data.watch_reg_use_cnt == 0)
	227	return -EIO;
	228	if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
	229	return -EIO;
	230	/* Check the values. */
	231	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
	232	__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
	233	#ifdef CONFIG_32BIT
	234	if (lt[i] & __UA_LIMIT)
	235	return -EINVAL;
	236	#else
	237	if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
	238	if (lt[i] & 0xffffffff80000000UL)
	239	return -EINVAL;
	240	} else {
	241	if (lt[i] & __UA_LIMIT)
	242	return -EINVAL;
243	}
244	#endif
245	__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
246	if (ht[i] & ~0xff8)
247	return -EINVAL;
248	}
249	/* Install them. */
250	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
251	if (lt[i] & 7)
252	watch_active = 1;
253	child->thread.watch.mips3264.watchlo[i] = lt[i];
254	/* Set the G bit. */
255	child->thread.watch.mips3264.watchhi[i] = ht[i];
256	}
257
258	if (watch_active)
259	set_tsk_thread_flag(child, TIF_LOAD_WATCH);
260	else
261	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
262
263	return 0;
264	}
265
7aeb753b RB	266	/* regset get/set implementations */
	267
	268	static int gpr_get(struct task_struct *target,
	269	const struct user_regset *regset,
	270	unsigned int pos, unsigned int count,
	271	void kbuf, void __user ubuf)
	272	{
	273	struct pt_regs *regs = task_pt_regs(target);
	274
	275	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
	276	regs, 0, sizeof(*regs));
	277	}
	278
	279	static int gpr_set(struct task_struct *target,
	280	const struct user_regset *regset,
	281	unsigned int pos, unsigned int count,
	282	const void kbuf, const void __user ubuf)
	283	{
	284	struct pt_regs newregs;
	285	int ret;
	286
	287	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
	288	&newregs,
	289	0, sizeof(newregs));
	290	if (ret)
	291	return ret;
	292
	293	*task_pt_regs(target) = newregs;
	294
	295	return 0;
	296	}
	297
	298	static int fpr_get(struct task_struct *target,
	299	const struct user_regset *regset,
	300	unsigned int pos, unsigned int count,
	301	void kbuf, void __user ubuf)
	302	{
	303	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
	304	&target->thread.fpu,
	305	0, sizeof(elf_fpregset_t));
	306	/* XXX fcr31 */
	307	}
	308
	309	static int fpr_set(struct task_struct *target,
	310	const struct user_regset *regset,
	311	unsigned int pos, unsigned int count,
	312	const void kbuf, const void __user ubuf)
	313	{
	314	return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
	315	&target->thread.fpu,
	316	0, sizeof(elf_fpregset_t));
	317	/* XXX fcr31 */
	318	}
	319
	320	enum mips_regset {
	321	REGSET_GPR,
	322	REGSET_FPR,
	323	};
	324
	325	static const struct user_regset mips_regsets[] = {
	326	[REGSET_GPR] = {
	327	.core_note_type = NT_PRSTATUS,
	328	.n = ELF_NGREG,
	329	.size = sizeof(unsigned int),
330	.align = sizeof(unsigned int),
331	.get = gpr_get,
332	.set = gpr_set,
333	},
334	[REGSET_FPR] = {
335	.core_note_type = NT_PRFPREG,
336	.n = ELF_NFPREG,
337	.size = sizeof(elf_fpreg_t),
338	.align = sizeof(elf_fpreg_t),
339	.get = fpr_get,
340	.set = fpr_set,
341	},
342	};
343
344	static const struct user_regset_view user_mips_view = {
345	.name = "mips",
346	.e_machine = ELF_ARCH,
347	.ei_osabi = ELF_OSABI,
348	.regsets = mips_regsets,
349	.n = ARRAY_SIZE(mips_regsets),
350	};
351
352	static const struct user_regset mips64_regsets[] = {
353	[REGSET_GPR] = {
354	.core_note_type = NT_PRSTATUS,
355	.n = ELF_NGREG,
356	.size = sizeof(unsigned long),
357	.align = sizeof(unsigned long),
358	.get = gpr_get,
359	.set = gpr_set,
360	},
361	[REGSET_FPR] = {
362	.core_note_type = NT_PRFPREG,
363	.n = ELF_NFPREG,
364	.size = sizeof(elf_fpreg_t),
365	.align = sizeof(elf_fpreg_t),
366	.get = fpr_get,
367	.set = fpr_set,
368	},
369	};
370
371	static const struct user_regset_view user_mips64_view = {
372	.name = "mips",
373	.e_machine = ELF_ARCH,
374	.ei_osabi = ELF_OSABI,
375	.regsets = mips64_regsets,
376	.n = ARRAY_SIZE(mips_regsets),
377	};
378
379	const struct user_regset_view task_user_regset_view(struct task_struct task)
380	{
381	#ifdef CONFIG_32BIT
382	return &user_mips_view;
383	#endif
384
385	#ifdef CONFIG_MIPS32_O32
386	if (test_thread_flag(TIF_32BIT_REGS))
387	return &user_mips_view;
388	#endif
389
390	return &user_mips64_view;
391	}
392
9b05a69e NK	393	long arch_ptrace(struct task_struct *child, long request,
9b05a69e NK	394	unsigned long addr, unsigned long data)
1da177e4	395	{
1da177e4	396	int ret;
fb671139 NK	397	void __user addrp = (void __user ) addr;
	398	void __user datavp = (void __user ) data;
	399	unsigned long __user datalp = (void __user ) data;
1da177e4	400
1da177e4 LT	401	switch (request) {
	402	/* when I and D space are separate, these will need to be fixed. */
	403	case PTRACE_PEEKTEXT: /* read word at location addr. */
76647323 AD	404	case PTRACE_PEEKDATA:
76647323 AD	405	ret = generic_ptrace_peekdata(child, addr, data);
1da177e4	406	break;
1da177e4 LT	407
	408	/* Read the word at location addr in the USER area. */
	409	case PTRACE_PEEKUSR: {
	410	struct pt_regs *regs;
597ce172	411	fpureg_t *fregs;
1da177e4 LT	412	unsigned long tmp = 0;
1da177e4 LT	413
40bc9c67	414	regs = task_pt_regs(child);
1da177e4 LT	415	ret = 0; /* Default return value. */
	416
	417	switch (addr) {
	418	case 0 ... 31:
	419	tmp = regs->regs[addr];
	420	break;
	421	case FPR_BASE ... FPR_BASE + 31:
597ce172 PB	422	if (!tsk_used_math(child)) {
	423	/* FP not yet used */
	424	tmp = -1;
	425	break;
	426	}
	427	fregs = get_fpu_regs(child);
1da177e4	428
875d43e7	429	#ifdef CONFIG_32BIT
597ce172	430	if (test_thread_flag(TIF_32BIT_FPREGS)) {
1da177e4 LT	431	/*
	432	* The odd registers are actually the high
	433	* order bits of the values stored in the even
	434	* registers - unless we're using r2k_switch.S.
	435	*/
	436	if (addr & 1)
597ce172	437	tmp = fregs[(addr & ~1) - 32] >> 32;
1da177e4	438	else
597ce172 PB	439	tmp = fregs[addr - 32];
597ce172 PB	440	break;
1da177e4	441	}
597ce172 PB	442	#endif
597ce172 PB	443	tmp = fregs[addr - FPR_BASE];
1da177e4 LT	444	break;
	445	case PC:
	446	tmp = regs->cp0_epc;
	447	break;
	448	case CAUSE:
	449	tmp = regs->cp0_cause;
	450	break;
	451	case BADVADDR:
	452	tmp = regs->cp0_badvaddr;
	453	break;
	454	case MMHI:
	455	tmp = regs->hi;
	456	break;
	457	case MMLO:
	458	tmp = regs->lo;
	459	break;
9693a853 FBH	460	#ifdef CONFIG_CPU_HAS_SMARTMIPS
	461	case ACX:
	462	tmp = regs->acx;
	463	break;
	464	#endif
1da177e4	465	case FPC_CSR:
eae89076	466	tmp = child->thread.fpu.fcr31;
1da177e4	467	break;
70342287	468	case FPC_EIR: { /* implementation / version register */
1da177e4	469	unsigned int flags;
41c594ab	470	#ifdef CONFIG_MIPS_MT_SMTC
b7e4226e	471	unsigned long irqflags;
41c594ab RB	472	unsigned int mtflags;
41c594ab RB	473	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4	474
e04582b7 AN	475	preempt_disable();
	476	if (!cpu_has_fpu) {
	477	preempt_enable();
1da177e4	478	break;
e04582b7	479	}
1da177e4	480
41c594ab RB	481	#ifdef CONFIG_MIPS_MT_SMTC
	482	/* Read-modify-write of Status must be atomic */
	483	local_irq_save(irqflags);
	484	mtflags = dmt();
	485	#endif /* CONFIG_MIPS_MT_SMTC */
101b3531 RB	486	if (cpu_has_mipsmt) {
	487	unsigned int vpflags = dvpe();
	488	flags = read_c0_status();
597ce172	489	__enable_fpu(FPU_AS_IS);
101b3531 RB	490	__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
	491	write_c0_status(flags);
	492	evpe(vpflags);
	493	} else {
	494	flags = read_c0_status();
597ce172	495	__enable_fpu(FPU_AS_IS);
101b3531 RB	496	__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
	497	write_c0_status(flags);
	498	}
41c594ab RB	499	#ifdef CONFIG_MIPS_MT_SMTC
	500	emt(mtflags);
	501	local_irq_restore(irqflags);
	502	#endif /* CONFIG_MIPS_MT_SMTC */
101b3531	503	preempt_enable();
1da177e4 LT	504	break;
1da177e4 LT	505	}
c134a5ec RB	506	case DSP_BASE ... DSP_BASE + 5: {
	507	dspreg_t *dregs;
	508
e50c0a8f RB	509	if (!cpu_has_dsp) {
	510	tmp = 0;
	511	ret = -EIO;
481bed45	512	goto out;
e50c0a8f	513	}
6c355852 RB	514	dregs = __get_dsp_regs(child);
6c355852 RB	515	tmp = (unsigned long) (dregs[addr - DSP_BASE]);
e50c0a8f	516	break;
c134a5ec	517	}
e50c0a8f RB	518	case DSP_CONTROL:
	519	if (!cpu_has_dsp) {
	520	tmp = 0;
	521	ret = -EIO;
481bed45	522	goto out;
e50c0a8f RB	523	}
	524	tmp = child->thread.dsp.dspcontrol;
	525	break;
1da177e4 LT	526	default:
	527	tmp = 0;
	528	ret = -EIO;
481bed45	529	goto out;
1da177e4	530	}
fb671139	531	ret = put_user(tmp, datalp);
1da177e4 LT	532	break;
	533	}
	534
	535	/* when I and D space are separate, this will have to be fixed. */
	536	case PTRACE_POKETEXT: /* write the word at location addr. */
	537	case PTRACE_POKEDATA:
f284ce72	538	ret = generic_ptrace_pokedata(child, addr, data);
1da177e4 LT	539	break;
	540
	541	case PTRACE_POKEUSR: {
	542	struct pt_regs *regs;
	543	ret = 0;
40bc9c67	544	regs = task_pt_regs(child);
1da177e4 LT	545
	546	switch (addr) {
	547	case 0 ... 31:
	548	regs->regs[addr] = data;
	549	break;
	550	case FPR_BASE ... FPR_BASE + 31: {
	551	fpureg_t *fregs = get_fpu_regs(child);
	552
	553	if (!tsk_used_math(child)) {
	554	/* FP not yet used */
eae89076 AN	555	memset(&child->thread.fpu, ~0,
	556	sizeof(child->thread.fpu));
	557	child->thread.fpu.fcr31 = 0;
1da177e4	558	}
875d43e7	559	#ifdef CONFIG_32BIT
597ce172 PB	560	if (test_thread_flag(TIF_32BIT_FPREGS)) {
	561	/*
	562	* The odd registers are actually the high
	563	* order bits of the values stored in the even
	564	* registers - unless we're using r2k_switch.S.
	565	*/
	566	if (addr & 1) {
	567	fregs[(addr & ~1) - FPR_BASE] &=
	568	0xffffffff;
	569	fregs[(addr & ~1) - FPR_BASE] \|=
	570	((u64)data) << 32;
	571	} else {
	572	fregs[addr - FPR_BASE] &= ~0xffffffffLL;
	573	fregs[addr - FPR_BASE] \|= data;
	574	}
	575	break;
1da177e4 LT	576	}
1da177e4 LT	577	#endif
1da177e4	578	fregs[addr - FPR_BASE] = data;
1da177e4 LT	579	break;
	580	}
	581	case PC:
	582	regs->cp0_epc = data;
	583	break;
	584	case MMHI:
	585	regs->hi = data;
	586	break;
	587	case MMLO:
	588	regs->lo = data;
	589	break;
9693a853 FBH	590	#ifdef CONFIG_CPU_HAS_SMARTMIPS
	591	case ACX:
	592	regs->acx = data;
	593	break;
	594	#endif
1da177e4	595	case FPC_CSR:
eae89076	596	child->thread.fpu.fcr31 = data;
1da177e4	597	break;
c134a5ec RB	598	case DSP_BASE ... DSP_BASE + 5: {
	599	dspreg_t *dregs;
	600
e50c0a8f RB	601	if (!cpu_has_dsp) {
	602	ret = -EIO;
	603	break;
	604	}
	605
c134a5ec	606	dregs = __get_dsp_regs(child);
e50c0a8f RB	607	dregs[addr - DSP_BASE] = data;
e50c0a8f RB	608	break;
c134a5ec	609	}
e50c0a8f RB	610	case DSP_CONTROL:
	611	if (!cpu_has_dsp) {
	612	ret = -EIO;
	613	break;
	614	}
	615	child->thread.dsp.dspcontrol = data;
	616	break;
1da177e4 LT	617	default:
	618	/* The rest are not allowed. */
	619	ret = -EIO;
	620	break;
	621	}
	622	break;
	623	}
	624
ea3d710f	625	case PTRACE_GETREGS:
fb671139	626	ret = ptrace_getregs(child, datavp);
ea3d710f DJ	627	break;
	628
	629	case PTRACE_SETREGS:
fb671139	630	ret = ptrace_setregs(child, datavp);
ea3d710f DJ	631	break;
	632
	633	case PTRACE_GETFPREGS:
fb671139	634	ret = ptrace_getfpregs(child, datavp);
ea3d710f DJ	635	break;
	636
	637	case PTRACE_SETFPREGS:
fb671139	638	ret = ptrace_setfpregs(child, datavp);
ea3d710f DJ	639	break;
ea3d710f DJ	640
3c37026d	641	case PTRACE_GET_THREAD_AREA:
fb671139	642	ret = put_user(task_thread_info(child)->tp_value, datalp);
3c37026d RB	643	break;
3c37026d RB	644
0926bf95	645	case PTRACE_GET_WATCH_REGS:
fb671139	646	ret = ptrace_get_watch_regs(child, addrp);
0926bf95 DD	647	break;
	648
	649	case PTRACE_SET_WATCH_REGS:
fb671139	650	ret = ptrace_set_watch_regs(child, addrp);
0926bf95 DD	651	break;
0926bf95 DD	652
1da177e4 LT	653	default:
	654	ret = ptrace_request(child, request, addr, data);
	655	break;
	656	}
481bed45	657	out:
1da177e4 LT	658	return ret;
	659	}
	660
	661	/*
	662	* Notification of system call entry/exit
	663	* - triggered by current->work.syscall_trace
	664	*/
4c21b8fd	665	asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
1da177e4	666	{
0dfa95aa	667	long ret = 0;
c3fc5cd5 RB	668	user_exit();
c3fc5cd5 RB	669
1225eb82 MC	670	if (secure_computing(syscall) == -1)
1225eb82 MC	671	return -1;
1da177e4	672
0dfa95aa RB	673	if (test_thread_flag(TIF_SYSCALL_TRACE) &&
	674	tracehook_report_syscall_entry(regs))
	675	ret = -1;
293c5bd1	676
1d7bf993 RB	677	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
	678	trace_sys_enter(regs, regs->regs[2]);
	679
6e345746	680	audit_syscall_entry(syscall_get_arch(current, regs),
1225eb82	681	syscall,
b05d8447 EP	682	regs->regs[4], regs->regs[5],
b05d8447 EP	683	regs->regs[6], regs->regs[7]);
1225eb82	684	return syscall;
1da177e4	685	}
8b659a39 RB	686
	687	/*
	688	* Notification of system call entry/exit
	689	* - triggered by current->work.syscall_trace
	690	*/
	691	asmlinkage void syscall_trace_leave(struct pt_regs *regs)
	692	{
c3fc5cd5 RB	693	/*
	694	* We may come here right after calling schedule_user()
	695	* or do_notify_resume(), in which case we can be in RCU
	696	* user mode.
	697	*/
	698	user_exit();
	699
d7e7528b	700	audit_syscall_exit(regs);
8b659a39	701
1d7bf993 RB	702	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
	703	trace_sys_exit(regs, regs->regs[2]);
	704
bc3d22c1 RB	705	if (test_thread_flag(TIF_SYSCALL_TRACE))
bc3d22c1 RB	706	tracehook_report_syscall_exit(regs, 0);
c3fc5cd5 RB	707
c3fc5cd5 RB	708	user_enter();
8b659a39	709	}