Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1992 Ross Biro | |
7 | * Copyright (C) Linus Torvalds | |
8 | * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle | |
9 | * Copyright (C) 1996 David S. Miller | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 1999 MIPS Technologies, Inc. | |
12 | * Copyright (C) 2000 Ulf Carlsson | |
13 | * | |
14 | * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit | |
15 | * binaries. | |
16 | */ | |
1da177e4 | 17 | #include <linux/compiler.h> |
c3fc5cd5 | 18 | #include <linux/context_tracking.h> |
7aeb753b | 19 | #include <linux/elf.h> |
1da177e4 LT |
20 | #include <linux/kernel.h> |
21 | #include <linux/sched.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/ptrace.h> | |
7aeb753b | 25 | #include <linux/regset.h> |
1da177e4 | 26 | #include <linux/smp.h> |
1da177e4 LT |
27 | #include <linux/user.h> |
28 | #include <linux/security.h> | |
bc3d22c1 | 29 | #include <linux/tracehook.h> |
293c5bd1 RB |
30 | #include <linux/audit.h> |
31 | #include <linux/seccomp.h> | |
1d7bf993 | 32 | #include <linux/ftrace.h> |
1da177e4 | 33 | |
f8280c8d | 34 | #include <asm/byteorder.h> |
1da177e4 | 35 | #include <asm/cpu.h> |
e50c0a8f | 36 | #include <asm/dsp.h> |
1da177e4 LT |
37 | #include <asm/fpu.h> |
38 | #include <asm/mipsregs.h> | |
101b3531 | 39 | #include <asm/mipsmtregs.h> |
1da177e4 LT |
40 | #include <asm/pgtable.h> |
41 | #include <asm/page.h> | |
bec9b2b2 | 42 | #include <asm/syscall.h> |
1da177e4 LT |
43 | #include <asm/uaccess.h> |
44 | #include <asm/bootinfo.h> | |
ea3d710f | 45 | #include <asm/reg.h> |
1da177e4 | 46 | |
1d7bf993 RB |
47 | #define CREATE_TRACE_POINTS |
48 | #include <trace/events/syscalls.h> | |
49 | ||
1da177e4 LT |
50 | /* |
51 | * Called by kernel/ptrace.c when detaching.. | |
52 | * | |
53 | * Make sure single step bits etc are not set. | |
54 | */ | |
55 | void ptrace_disable(struct task_struct *child) | |
56 | { | |
0926bf95 DD |
57 | /* Don't load the watchpoint registers for the ex-child. */ |
58 | clear_tsk_thread_flag(child, TIF_LOAD_WATCH); | |
1da177e4 LT |
59 | } |
60 | ||
ea3d710f | 61 | /* |
70342287 | 62 | * Read a general register set. We always use the 64-bit format, even |
ea3d710f DJ |
63 | * for 32-bit kernels and for 32-bit processes on a 64-bit kernel. |
64 | * Registers are sign extended to fill the available space. | |
65 | */ | |
49a89efb | 66 | int ptrace_getregs(struct task_struct *child, __s64 __user *data) |
ea3d710f DJ |
67 | { |
68 | struct pt_regs *regs; | |
69 | int i; | |
70 | ||
71 | if (!access_ok(VERIFY_WRITE, data, 38 * 8)) | |
72 | return -EIO; | |
73 | ||
40bc9c67 | 74 | regs = task_pt_regs(child); |
ea3d710f DJ |
75 | |
76 | for (i = 0; i < 32; i++) | |
62b14c24 AN |
77 | __put_user((long)regs->regs[i], data + i); |
78 | __put_user((long)regs->lo, data + EF_LO - EF_R0); | |
79 | __put_user((long)regs->hi, data + EF_HI - EF_R0); | |
80 | __put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0); | |
81 | __put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0); | |
82 | __put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0); | |
83 | __put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0); | |
ea3d710f DJ |
84 | |
85 | return 0; | |
86 | } | |
87 | ||
88 | /* | |
89 | * Write a general register set. As for PTRACE_GETREGS, we always use | |
90 | * the 64-bit format. On a 32-bit kernel only the lower order half | |
91 | * (according to endianness) will be used. | |
92 | */ | |
49a89efb | 93 | int ptrace_setregs(struct task_struct *child, __s64 __user *data) |
ea3d710f DJ |
94 | { |
95 | struct pt_regs *regs; | |
96 | int i; | |
97 | ||
98 | if (!access_ok(VERIFY_READ, data, 38 * 8)) | |
99 | return -EIO; | |
100 | ||
40bc9c67 | 101 | regs = task_pt_regs(child); |
ea3d710f DJ |
102 | |
103 | for (i = 0; i < 32; i++) | |
49a89efb RB |
104 | __get_user(regs->regs[i], data + i); |
105 | __get_user(regs->lo, data + EF_LO - EF_R0); | |
106 | __get_user(regs->hi, data + EF_HI - EF_R0); | |
107 | __get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0); | |
ea3d710f DJ |
108 | |
109 | /* badvaddr, status, and cause may not be written. */ | |
110 | ||
111 | return 0; | |
112 | } | |
113 | ||
49a89efb | 114 | int ptrace_getfpregs(struct task_struct *child, __u32 __user *data) |
ea3d710f DJ |
115 | { |
116 | int i; | |
e04582b7 | 117 | unsigned int tmp; |
ea3d710f DJ |
118 | |
119 | if (!access_ok(VERIFY_WRITE, data, 33 * 8)) | |
120 | return -EIO; | |
121 | ||
122 | if (tsk_used_math(child)) { | |
123 | fpureg_t *fregs = get_fpu_regs(child); | |
124 | for (i = 0; i < 32; i++) | |
49a89efb | 125 | __put_user(fregs[i], i + (__u64 __user *) data); |
ea3d710f DJ |
126 | } else { |
127 | for (i = 0; i < 32; i++) | |
49a89efb | 128 | __put_user((__u64) -1, i + (__u64 __user *) data); |
ea3d710f DJ |
129 | } |
130 | ||
49a89efb | 131 | __put_user(child->thread.fpu.fcr31, data + 64); |
eae89076 | 132 | |
e04582b7 | 133 | preempt_disable(); |
ea3d710f | 134 | if (cpu_has_fpu) { |
e04582b7 | 135 | unsigned int flags; |
ea3d710f | 136 | |
101b3531 RB |
137 | if (cpu_has_mipsmt) { |
138 | unsigned int vpflags = dvpe(); | |
139 | flags = read_c0_status(); | |
597ce172 | 140 | __enable_fpu(FPU_AS_IS); |
101b3531 RB |
141 | __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); |
142 | write_c0_status(flags); | |
143 | evpe(vpflags); | |
144 | } else { | |
145 | flags = read_c0_status(); | |
597ce172 | 146 | __enable_fpu(FPU_AS_IS); |
101b3531 RB |
147 | __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); |
148 | write_c0_status(flags); | |
149 | } | |
ea3d710f | 150 | } else { |
e04582b7 | 151 | tmp = 0; |
ea3d710f | 152 | } |
e04582b7 | 153 | preempt_enable(); |
49a89efb | 154 | __put_user(tmp, data + 65); |
ea3d710f DJ |
155 | |
156 | return 0; | |
157 | } | |
158 | ||
49a89efb | 159 | int ptrace_setfpregs(struct task_struct *child, __u32 __user *data) |
ea3d710f DJ |
160 | { |
161 | fpureg_t *fregs; | |
162 | int i; | |
163 | ||
164 | if (!access_ok(VERIFY_READ, data, 33 * 8)) | |
165 | return -EIO; | |
166 | ||
167 | fregs = get_fpu_regs(child); | |
168 | ||
169 | for (i = 0; i < 32; i++) | |
49a89efb | 170 | __get_user(fregs[i], i + (__u64 __user *) data); |
ea3d710f | 171 | |
49a89efb | 172 | __get_user(child->thread.fpu.fcr31, data + 64); |
ea3d710f DJ |
173 | |
174 | /* FIR may not be written. */ | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
0926bf95 DD |
179 | int ptrace_get_watch_regs(struct task_struct *child, |
180 | struct pt_watch_regs __user *addr) | |
181 | { | |
182 | enum pt_watch_style style; | |
183 | int i; | |
184 | ||
185 | if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0) | |
186 | return -EIO; | |
187 | if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs))) | |
188 | return -EIO; | |
189 | ||
190 | #ifdef CONFIG_32BIT | |
191 | style = pt_watch_style_mips32; | |
192 | #define WATCH_STYLE mips32 | |
193 | #else | |
194 | style = pt_watch_style_mips64; | |
195 | #define WATCH_STYLE mips64 | |
196 | #endif | |
197 | ||
198 | __put_user(style, &addr->style); | |
199 | __put_user(current_cpu_data.watch_reg_use_cnt, | |
200 | &addr->WATCH_STYLE.num_valid); | |
201 | for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) { | |
202 | __put_user(child->thread.watch.mips3264.watchlo[i], | |
203 | &addr->WATCH_STYLE.watchlo[i]); | |
204 | __put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff, | |
205 | &addr->WATCH_STYLE.watchhi[i]); | |
206 | __put_user(current_cpu_data.watch_reg_masks[i], | |
207 | &addr->WATCH_STYLE.watch_masks[i]); | |
208 | } | |
209 | for (; i < 8; i++) { | |
210 | __put_user(0, &addr->WATCH_STYLE.watchlo[i]); | |
211 | __put_user(0, &addr->WATCH_STYLE.watchhi[i]); | |
212 | __put_user(0, &addr->WATCH_STYLE.watch_masks[i]); | |
213 | } | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
218 | int ptrace_set_watch_regs(struct task_struct *child, | |
219 | struct pt_watch_regs __user *addr) | |
220 | { | |
221 | int i; | |
222 | int watch_active = 0; | |
223 | unsigned long lt[NUM_WATCH_REGS]; | |
224 | u16 ht[NUM_WATCH_REGS]; | |
225 | ||
226 | if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0) | |
227 | return -EIO; | |
228 | if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs))) | |
229 | return -EIO; | |
230 | /* Check the values. */ | |
231 | for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) { | |
232 | __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]); | |
233 | #ifdef CONFIG_32BIT | |
234 | if (lt[i] & __UA_LIMIT) | |
235 | return -EINVAL; | |
236 | #else | |
237 | if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) { | |
238 | if (lt[i] & 0xffffffff80000000UL) | |
239 | return -EINVAL; | |
240 | } else { | |
241 | if (lt[i] & __UA_LIMIT) | |
242 | return -EINVAL; | |
243 | } | |
244 | #endif | |
245 | __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]); | |
246 | if (ht[i] & ~0xff8) | |
247 | return -EINVAL; | |
248 | } | |
249 | /* Install them. */ | |
250 | for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) { | |
251 | if (lt[i] & 7) | |
252 | watch_active = 1; | |
253 | child->thread.watch.mips3264.watchlo[i] = lt[i]; | |
254 | /* Set the G bit. */ | |
255 | child->thread.watch.mips3264.watchhi[i] = ht[i]; | |
256 | } | |
257 | ||
258 | if (watch_active) | |
259 | set_tsk_thread_flag(child, TIF_LOAD_WATCH); | |
260 | else | |
261 | clear_tsk_thread_flag(child, TIF_LOAD_WATCH); | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
7aeb753b RB |
266 | /* regset get/set implementations */ |
267 | ||
268 | static int gpr_get(struct task_struct *target, | |
269 | const struct user_regset *regset, | |
270 | unsigned int pos, unsigned int count, | |
271 | void *kbuf, void __user *ubuf) | |
272 | { | |
273 | struct pt_regs *regs = task_pt_regs(target); | |
274 | ||
275 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
276 | regs, 0, sizeof(*regs)); | |
277 | } | |
278 | ||
279 | static int gpr_set(struct task_struct *target, | |
280 | const struct user_regset *regset, | |
281 | unsigned int pos, unsigned int count, | |
282 | const void *kbuf, const void __user *ubuf) | |
283 | { | |
284 | struct pt_regs newregs; | |
285 | int ret; | |
286 | ||
287 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
288 | &newregs, | |
289 | 0, sizeof(newregs)); | |
290 | if (ret) | |
291 | return ret; | |
292 | ||
293 | *task_pt_regs(target) = newregs; | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | static int fpr_get(struct task_struct *target, | |
299 | const struct user_regset *regset, | |
300 | unsigned int pos, unsigned int count, | |
301 | void *kbuf, void __user *ubuf) | |
302 | { | |
303 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
304 | &target->thread.fpu, | |
305 | 0, sizeof(elf_fpregset_t)); | |
306 | /* XXX fcr31 */ | |
307 | } | |
308 | ||
309 | static int fpr_set(struct task_struct *target, | |
310 | const struct user_regset *regset, | |
311 | unsigned int pos, unsigned int count, | |
312 | const void *kbuf, const void __user *ubuf) | |
313 | { | |
314 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
315 | &target->thread.fpu, | |
316 | 0, sizeof(elf_fpregset_t)); | |
317 | /* XXX fcr31 */ | |
318 | } | |
319 | ||
320 | enum mips_regset { | |
321 | REGSET_GPR, | |
322 | REGSET_FPR, | |
323 | }; | |
324 | ||
325 | static const struct user_regset mips_regsets[] = { | |
326 | [REGSET_GPR] = { | |
327 | .core_note_type = NT_PRSTATUS, | |
328 | .n = ELF_NGREG, | |
329 | .size = sizeof(unsigned int), | |
330 | .align = sizeof(unsigned int), | |
331 | .get = gpr_get, | |
332 | .set = gpr_set, | |
333 | }, | |
334 | [REGSET_FPR] = { | |
335 | .core_note_type = NT_PRFPREG, | |
336 | .n = ELF_NFPREG, | |
337 | .size = sizeof(elf_fpreg_t), | |
338 | .align = sizeof(elf_fpreg_t), | |
339 | .get = fpr_get, | |
340 | .set = fpr_set, | |
341 | }, | |
342 | }; | |
343 | ||
344 | static const struct user_regset_view user_mips_view = { | |
345 | .name = "mips", | |
346 | .e_machine = ELF_ARCH, | |
347 | .ei_osabi = ELF_OSABI, | |
348 | .regsets = mips_regsets, | |
349 | .n = ARRAY_SIZE(mips_regsets), | |
350 | }; | |
351 | ||
352 | static const struct user_regset mips64_regsets[] = { | |
353 | [REGSET_GPR] = { | |
354 | .core_note_type = NT_PRSTATUS, | |
355 | .n = ELF_NGREG, | |
356 | .size = sizeof(unsigned long), | |
357 | .align = sizeof(unsigned long), | |
358 | .get = gpr_get, | |
359 | .set = gpr_set, | |
360 | }, | |
361 | [REGSET_FPR] = { | |
362 | .core_note_type = NT_PRFPREG, | |
363 | .n = ELF_NFPREG, | |
364 | .size = sizeof(elf_fpreg_t), | |
365 | .align = sizeof(elf_fpreg_t), | |
366 | .get = fpr_get, | |
367 | .set = fpr_set, | |
368 | }, | |
369 | }; | |
370 | ||
371 | static const struct user_regset_view user_mips64_view = { | |
372 | .name = "mips", | |
373 | .e_machine = ELF_ARCH, | |
374 | .ei_osabi = ELF_OSABI, | |
375 | .regsets = mips64_regsets, | |
376 | .n = ARRAY_SIZE(mips_regsets), | |
377 | }; | |
378 | ||
379 | const struct user_regset_view *task_user_regset_view(struct task_struct *task) | |
380 | { | |
381 | #ifdef CONFIG_32BIT | |
382 | return &user_mips_view; | |
383 | #endif | |
384 | ||
385 | #ifdef CONFIG_MIPS32_O32 | |
386 | if (test_thread_flag(TIF_32BIT_REGS)) | |
387 | return &user_mips_view; | |
388 | #endif | |
389 | ||
390 | return &user_mips64_view; | |
391 | } | |
392 | ||
9b05a69e NK |
393 | long arch_ptrace(struct task_struct *child, long request, |
394 | unsigned long addr, unsigned long data) | |
1da177e4 | 395 | { |
1da177e4 | 396 | int ret; |
fb671139 NK |
397 | void __user *addrp = (void __user *) addr; |
398 | void __user *datavp = (void __user *) data; | |
399 | unsigned long __user *datalp = (void __user *) data; | |
1da177e4 | 400 | |
1da177e4 LT |
401 | switch (request) { |
402 | /* when I and D space are separate, these will need to be fixed. */ | |
403 | case PTRACE_PEEKTEXT: /* read word at location addr. */ | |
76647323 AD |
404 | case PTRACE_PEEKDATA: |
405 | ret = generic_ptrace_peekdata(child, addr, data); | |
1da177e4 | 406 | break; |
1da177e4 LT |
407 | |
408 | /* Read the word at location addr in the USER area. */ | |
409 | case PTRACE_PEEKUSR: { | |
410 | struct pt_regs *regs; | |
597ce172 | 411 | fpureg_t *fregs; |
1da177e4 LT |
412 | unsigned long tmp = 0; |
413 | ||
40bc9c67 | 414 | regs = task_pt_regs(child); |
1da177e4 LT |
415 | ret = 0; /* Default return value. */ |
416 | ||
417 | switch (addr) { | |
418 | case 0 ... 31: | |
419 | tmp = regs->regs[addr]; | |
420 | break; | |
421 | case FPR_BASE ... FPR_BASE + 31: | |
597ce172 PB |
422 | if (!tsk_used_math(child)) { |
423 | /* FP not yet used */ | |
424 | tmp = -1; | |
425 | break; | |
426 | } | |
427 | fregs = get_fpu_regs(child); | |
1da177e4 | 428 | |
875d43e7 | 429 | #ifdef CONFIG_32BIT |
597ce172 | 430 | if (test_thread_flag(TIF_32BIT_FPREGS)) { |
1da177e4 LT |
431 | /* |
432 | * The odd registers are actually the high | |
433 | * order bits of the values stored in the even | |
434 | * registers - unless we're using r2k_switch.S. | |
435 | */ | |
436 | if (addr & 1) | |
597ce172 | 437 | tmp = fregs[(addr & ~1) - 32] >> 32; |
1da177e4 | 438 | else |
597ce172 PB |
439 | tmp = fregs[addr - 32]; |
440 | break; | |
1da177e4 | 441 | } |
597ce172 PB |
442 | #endif |
443 | tmp = fregs[addr - FPR_BASE]; | |
1da177e4 LT |
444 | break; |
445 | case PC: | |
446 | tmp = regs->cp0_epc; | |
447 | break; | |
448 | case CAUSE: | |
449 | tmp = regs->cp0_cause; | |
450 | break; | |
451 | case BADVADDR: | |
452 | tmp = regs->cp0_badvaddr; | |
453 | break; | |
454 | case MMHI: | |
455 | tmp = regs->hi; | |
456 | break; | |
457 | case MMLO: | |
458 | tmp = regs->lo; | |
459 | break; | |
9693a853 FBH |
460 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
461 | case ACX: | |
462 | tmp = regs->acx; | |
463 | break; | |
464 | #endif | |
1da177e4 | 465 | case FPC_CSR: |
eae89076 | 466 | tmp = child->thread.fpu.fcr31; |
1da177e4 | 467 | break; |
70342287 | 468 | case FPC_EIR: { /* implementation / version register */ |
1da177e4 | 469 | unsigned int flags; |
41c594ab | 470 | #ifdef CONFIG_MIPS_MT_SMTC |
b7e4226e | 471 | unsigned long irqflags; |
41c594ab RB |
472 | unsigned int mtflags; |
473 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 | 474 | |
e04582b7 AN |
475 | preempt_disable(); |
476 | if (!cpu_has_fpu) { | |
477 | preempt_enable(); | |
1da177e4 | 478 | break; |
e04582b7 | 479 | } |
1da177e4 | 480 | |
41c594ab RB |
481 | #ifdef CONFIG_MIPS_MT_SMTC |
482 | /* Read-modify-write of Status must be atomic */ | |
483 | local_irq_save(irqflags); | |
484 | mtflags = dmt(); | |
485 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
101b3531 RB |
486 | if (cpu_has_mipsmt) { |
487 | unsigned int vpflags = dvpe(); | |
488 | flags = read_c0_status(); | |
597ce172 | 489 | __enable_fpu(FPU_AS_IS); |
101b3531 RB |
490 | __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); |
491 | write_c0_status(flags); | |
492 | evpe(vpflags); | |
493 | } else { | |
494 | flags = read_c0_status(); | |
597ce172 | 495 | __enable_fpu(FPU_AS_IS); |
101b3531 RB |
496 | __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); |
497 | write_c0_status(flags); | |
498 | } | |
41c594ab RB |
499 | #ifdef CONFIG_MIPS_MT_SMTC |
500 | emt(mtflags); | |
501 | local_irq_restore(irqflags); | |
502 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
101b3531 | 503 | preempt_enable(); |
1da177e4 LT |
504 | break; |
505 | } | |
c134a5ec RB |
506 | case DSP_BASE ... DSP_BASE + 5: { |
507 | dspreg_t *dregs; | |
508 | ||
e50c0a8f RB |
509 | if (!cpu_has_dsp) { |
510 | tmp = 0; | |
511 | ret = -EIO; | |
481bed45 | 512 | goto out; |
e50c0a8f | 513 | } |
6c355852 RB |
514 | dregs = __get_dsp_regs(child); |
515 | tmp = (unsigned long) (dregs[addr - DSP_BASE]); | |
e50c0a8f | 516 | break; |
c134a5ec | 517 | } |
e50c0a8f RB |
518 | case DSP_CONTROL: |
519 | if (!cpu_has_dsp) { | |
520 | tmp = 0; | |
521 | ret = -EIO; | |
481bed45 | 522 | goto out; |
e50c0a8f RB |
523 | } |
524 | tmp = child->thread.dsp.dspcontrol; | |
525 | break; | |
1da177e4 LT |
526 | default: |
527 | tmp = 0; | |
528 | ret = -EIO; | |
481bed45 | 529 | goto out; |
1da177e4 | 530 | } |
fb671139 | 531 | ret = put_user(tmp, datalp); |
1da177e4 LT |
532 | break; |
533 | } | |
534 | ||
535 | /* when I and D space are separate, this will have to be fixed. */ | |
536 | case PTRACE_POKETEXT: /* write the word at location addr. */ | |
537 | case PTRACE_POKEDATA: | |
f284ce72 | 538 | ret = generic_ptrace_pokedata(child, addr, data); |
1da177e4 LT |
539 | break; |
540 | ||
541 | case PTRACE_POKEUSR: { | |
542 | struct pt_regs *regs; | |
543 | ret = 0; | |
40bc9c67 | 544 | regs = task_pt_regs(child); |
1da177e4 LT |
545 | |
546 | switch (addr) { | |
547 | case 0 ... 31: | |
548 | regs->regs[addr] = data; | |
549 | break; | |
550 | case FPR_BASE ... FPR_BASE + 31: { | |
551 | fpureg_t *fregs = get_fpu_regs(child); | |
552 | ||
553 | if (!tsk_used_math(child)) { | |
554 | /* FP not yet used */ | |
eae89076 AN |
555 | memset(&child->thread.fpu, ~0, |
556 | sizeof(child->thread.fpu)); | |
557 | child->thread.fpu.fcr31 = 0; | |
1da177e4 | 558 | } |
875d43e7 | 559 | #ifdef CONFIG_32BIT |
597ce172 PB |
560 | if (test_thread_flag(TIF_32BIT_FPREGS)) { |
561 | /* | |
562 | * The odd registers are actually the high | |
563 | * order bits of the values stored in the even | |
564 | * registers - unless we're using r2k_switch.S. | |
565 | */ | |
566 | if (addr & 1) { | |
567 | fregs[(addr & ~1) - FPR_BASE] &= | |
568 | 0xffffffff; | |
569 | fregs[(addr & ~1) - FPR_BASE] |= | |
570 | ((u64)data) << 32; | |
571 | } else { | |
572 | fregs[addr - FPR_BASE] &= ~0xffffffffLL; | |
573 | fregs[addr - FPR_BASE] |= data; | |
574 | } | |
575 | break; | |
1da177e4 LT |
576 | } |
577 | #endif | |
1da177e4 | 578 | fregs[addr - FPR_BASE] = data; |
1da177e4 LT |
579 | break; |
580 | } | |
581 | case PC: | |
582 | regs->cp0_epc = data; | |
583 | break; | |
584 | case MMHI: | |
585 | regs->hi = data; | |
586 | break; | |
587 | case MMLO: | |
588 | regs->lo = data; | |
589 | break; | |
9693a853 FBH |
590 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
591 | case ACX: | |
592 | regs->acx = data; | |
593 | break; | |
594 | #endif | |
1da177e4 | 595 | case FPC_CSR: |
eae89076 | 596 | child->thread.fpu.fcr31 = data; |
1da177e4 | 597 | break; |
c134a5ec RB |
598 | case DSP_BASE ... DSP_BASE + 5: { |
599 | dspreg_t *dregs; | |
600 | ||
e50c0a8f RB |
601 | if (!cpu_has_dsp) { |
602 | ret = -EIO; | |
603 | break; | |
604 | } | |
605 | ||
c134a5ec | 606 | dregs = __get_dsp_regs(child); |
e50c0a8f RB |
607 | dregs[addr - DSP_BASE] = data; |
608 | break; | |
c134a5ec | 609 | } |
e50c0a8f RB |
610 | case DSP_CONTROL: |
611 | if (!cpu_has_dsp) { | |
612 | ret = -EIO; | |
613 | break; | |
614 | } | |
615 | child->thread.dsp.dspcontrol = data; | |
616 | break; | |
1da177e4 LT |
617 | default: |
618 | /* The rest are not allowed. */ | |
619 | ret = -EIO; | |
620 | break; | |
621 | } | |
622 | break; | |
623 | } | |
624 | ||
ea3d710f | 625 | case PTRACE_GETREGS: |
fb671139 | 626 | ret = ptrace_getregs(child, datavp); |
ea3d710f DJ |
627 | break; |
628 | ||
629 | case PTRACE_SETREGS: | |
fb671139 | 630 | ret = ptrace_setregs(child, datavp); |
ea3d710f DJ |
631 | break; |
632 | ||
633 | case PTRACE_GETFPREGS: | |
fb671139 | 634 | ret = ptrace_getfpregs(child, datavp); |
ea3d710f DJ |
635 | break; |
636 | ||
637 | case PTRACE_SETFPREGS: | |
fb671139 | 638 | ret = ptrace_setfpregs(child, datavp); |
ea3d710f DJ |
639 | break; |
640 | ||
3c37026d | 641 | case PTRACE_GET_THREAD_AREA: |
fb671139 | 642 | ret = put_user(task_thread_info(child)->tp_value, datalp); |
3c37026d RB |
643 | break; |
644 | ||
0926bf95 | 645 | case PTRACE_GET_WATCH_REGS: |
fb671139 | 646 | ret = ptrace_get_watch_regs(child, addrp); |
0926bf95 DD |
647 | break; |
648 | ||
649 | case PTRACE_SET_WATCH_REGS: | |
fb671139 | 650 | ret = ptrace_set_watch_regs(child, addrp); |
0926bf95 DD |
651 | break; |
652 | ||
1da177e4 LT |
653 | default: |
654 | ret = ptrace_request(child, request, addr, data); | |
655 | break; | |
656 | } | |
481bed45 | 657 | out: |
1da177e4 LT |
658 | return ret; |
659 | } | |
660 | ||
661 | /* | |
662 | * Notification of system call entry/exit | |
663 | * - triggered by current->work.syscall_trace | |
664 | */ | |
1225eb82 | 665 | asmlinkage long syscall_trace_enter(struct pt_regs *regs) |
1da177e4 | 666 | { |
1225eb82 | 667 | long syscall = regs->regs[2]; |
0dfa95aa | 668 | long ret = 0; |
c3fc5cd5 RB |
669 | user_exit(); |
670 | ||
1225eb82 MC |
671 | if (secure_computing(syscall) == -1) |
672 | return -1; | |
1da177e4 | 673 | |
0dfa95aa RB |
674 | if (test_thread_flag(TIF_SYSCALL_TRACE) && |
675 | tracehook_report_syscall_entry(regs)) | |
676 | ret = -1; | |
293c5bd1 | 677 | |
1d7bf993 RB |
678 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
679 | trace_sys_enter(regs, regs->regs[2]); | |
680 | ||
6e345746 | 681 | audit_syscall_entry(syscall_get_arch(current, regs), |
1225eb82 | 682 | syscall, |
b05d8447 EP |
683 | regs->regs[4], regs->regs[5], |
684 | regs->regs[6], regs->regs[7]); | |
1225eb82 | 685 | return syscall; |
1da177e4 | 686 | } |
8b659a39 RB |
687 | |
688 | /* | |
689 | * Notification of system call entry/exit | |
690 | * - triggered by current->work.syscall_trace | |
691 | */ | |
692 | asmlinkage void syscall_trace_leave(struct pt_regs *regs) | |
693 | { | |
c3fc5cd5 RB |
694 | /* |
695 | * We may come here right after calling schedule_user() | |
696 | * or do_notify_resume(), in which case we can be in RCU | |
697 | * user mode. | |
698 | */ | |
699 | user_exit(); | |
700 | ||
d7e7528b | 701 | audit_syscall_exit(regs); |
8b659a39 | 702 | |
1d7bf993 RB |
703 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
704 | trace_sys_exit(regs, regs->regs[2]); | |
705 | ||
bc3d22c1 RB |
706 | if (test_thread_flag(TIF_SYSCALL_TRACE)) |
707 | tracehook_report_syscall_exit(regs, 0); | |
c3fc5cd5 RB |
708 | |
709 | user_enter(); | |
8b659a39 | 710 | } |