[deliverable/linux.git] / arch / mips / kernel / ptrace.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 Ross Biro
 * Copyright (C) Linus Torvalds
 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
 * Copyright (C) 1996 David S. Miller
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 1999 MIPS Technologies, Inc.
 * Copyright (C) 2000 Ulf Carlsson
 *
 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
 * binaries.
 */
#include <linux/compiler.h>
#include <linux/context_tracking.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
#include <linux/smp.h>
#include <linux/user.h>
#include <linux/security.h>
#include <linux/tracehook.h>
#include <linux/audit.h>
#include <linux/seccomp.h>

#include <asm/byteorder.h>
#include <asm/cpu.h>
#include <asm/dsp.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/uaccess.h>
#include <asm/bootinfo.h>
#include <asm/reg.h>

/*
 * Called by kernel/ptrace.c when detaching..
 *
 * Make sure single step bits etc are not set.
 */
void ptrace_disable(struct task_struct *child)
{
	/* Don't load the watchpoint registers for the ex-child. */
	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
}

/*
 * Read a general register set.	 We always use the 64-bit format, even
 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
 * Registers are sign extended to fill the available space.
 */
int ptrace_getregs(struct task_struct *child, __s64 __user *data)
{
	struct pt_regs *regs;
	int i;

	if (!access_ok(VERIFY_WRITE, data, 38 * 8))
		return -EIO;

	regs = task_pt_regs(child);

	for (i = 0; i < 32; i++)
		__put_user((long)regs->regs[i], data + i);
	__put_user((long)regs->lo, data + EF_LO - EF_R0);
	__put_user((long)regs->hi, data + EF_HI - EF_R0);
	__put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
	__put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
	__put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
	__put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);

	return 0;
}

/*
 * Write a general register set.  As for PTRACE_GETREGS, we always use
 * the 64-bit format.  On a 32-bit kernel only the lower order half
 * (according to endianness) will be used.
 */
int ptrace_setregs(struct task_struct *child, __s64 __user *data)
{
	struct pt_regs *regs;
	int i;

	if (!access_ok(VERIFY_READ, data, 38 * 8))
		return -EIO;

	regs = task_pt_regs(child);

	for (i = 0; i < 32; i++)
		__get_user(regs->regs[i], data + i);
	__get_user(regs->lo, data + EF_LO - EF_R0);
	__get_user(regs->hi, data + EF_HI - EF_R0);
	__get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);

	/* badvaddr, status, and cause may not be written.  */

	return 0;
}

int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
{
	int i;
	unsigned int tmp;

	if (!access_ok(VERIFY_WRITE, data, 33 * 8))
		return -EIO;

	if (tsk_used_math(child)) {
		fpureg_t *fregs = get_fpu_regs(child);
		for (i = 0; i < 32; i++)
			__put_user(fregs[i], i + (__u64 __user *) data);
	} else {
		for (i = 0; i < 32; i++)
			__put_user((__u64) -1, i + (__u64 __user *) data);
	}

	__put_user(child->thread.fpu.fcr31, data + 64);

	preempt_disable();
	if (cpu_has_fpu) {
		unsigned int flags;

		if (cpu_has_mipsmt) {
			unsigned int vpflags = dvpe();
			flags = read_c0_status();
			__enable_fpu();
			__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
			write_c0_status(flags);
			evpe(vpflags);
		} else {
			flags = read_c0_status();
			__enable_fpu();
			__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
			write_c0_status(flags);
		}
	} else {
		tmp = 0;
	}
	preempt_enable();
	__put_user(tmp, data + 65);

	return 0;
}

int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
{
	fpureg_t *fregs;
	int i;

	if (!access_ok(VERIFY_READ, data, 33 * 8))
		return -EIO;

	fregs = get_fpu_regs(child);

	for (i = 0; i < 32; i++)
		__get_user(fregs[i], i + (__u64 __user *) data);

	__get_user(child->thread.fpu.fcr31, data + 64);

	/* FIR may not be written.  */

	return 0;
}

int ptrace_get_watch_regs(struct task_struct *child,
			  struct pt_watch_regs __user *addr)
{
	enum pt_watch_style style;
	int i;

	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
		return -EIO;
	if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
		return -EIO;

#ifdef CONFIG_32BIT
	style = pt_watch_style_mips32;
#define WATCH_STYLE mips32
#else
	style = pt_watch_style_mips64;
#define WATCH_STYLE mips64
#endif

	__put_user(style, &addr->style);
	__put_user(current_cpu_data.watch_reg_use_cnt,
		   &addr->WATCH_STYLE.num_valid);
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		__put_user(child->thread.watch.mips3264.watchlo[i],
			   &addr->WATCH_STYLE.watchlo[i]);
		__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
			   &addr->WATCH_STYLE.watchhi[i]);
		__put_user(current_cpu_data.watch_reg_masks[i],
			   &addr->WATCH_STYLE.watch_masks[i]);
	}
	for (; i < 8; i++) {
		__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
		__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
		__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
	}

	return 0;
}

int ptrace_set_watch_regs(struct task_struct *child,
			  struct pt_watch_regs __user *addr)
{
	int i;
	int watch_active = 0;
	unsigned long lt[NUM_WATCH_REGS];
	u16 ht[NUM_WATCH_REGS];

	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
		return -EIO;
	if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
		return -EIO;
	/* Check the values. */
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
#ifdef CONFIG_32BIT
		if (lt[i] & __UA_LIMIT)
			return -EINVAL;
#else
		if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
			if (lt[i] & 0xffffffff80000000UL)
				return -EINVAL;
		} else {
			if (lt[i] & __UA_LIMIT)
				return -EINVAL;
		}
#endif
		__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
		if (ht[i] & ~0xff8)
			return -EINVAL;
	}
	/* Install them. */
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		if (lt[i] & 7)
			watch_active = 1;
		child->thread.watch.mips3264.watchlo[i] = lt[i];
		/* Set the G bit. */
		child->thread.watch.mips3264.watchhi[i] = ht[i];
	}

	if (watch_active)
		set_tsk_thread_flag(child, TIF_LOAD_WATCH);
	else
		clear_tsk_thread_flag(child, TIF_LOAD_WATCH);

	return 0;
}

long arch_ptrace(struct task_struct *child, long request,
		 unsigned long addr, unsigned long data)
{
	int ret;
	void __user *addrp = (void __user *) addr;
	void __user *datavp = (void __user *) data;
	unsigned long __user *datalp = (void __user *) data;

	switch (request) {
	/* when I and D space are separate, these will need to be fixed. */
	case PTRACE_PEEKTEXT: /* read word at location addr. */
	case PTRACE_PEEKDATA:
		ret = generic_ptrace_peekdata(child, addr, data);
		break;

	/* Read the word at location addr in the USER area. */
	case PTRACE_PEEKUSR: {
		struct pt_regs *regs;
		unsigned long tmp = 0;

		regs = task_pt_regs(child);
		ret = 0;  /* Default return value. */

		switch (addr) {
		case 0 ... 31:
			tmp = regs->regs[addr];
			break;
		case FPR_BASE ... FPR_BASE + 31:
			if (tsk_used_math(child)) {
				fpureg_t *fregs = get_fpu_regs(child);

#ifdef CONFIG_32BIT
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				if (addr & 1)
					tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32);
				else
					tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
#endif
#ifdef CONFIG_64BIT
				tmp = fregs[addr - FPR_BASE];
#endif
			} else {
				tmp = -1;	/* FP not yet used  */
			}
			break;
		case PC:
			tmp = regs->cp0_epc;
			break;
		case CAUSE:
			tmp = regs->cp0_cause;
			break;
		case BADVADDR:
			tmp = regs->cp0_badvaddr;
			break;
		case MMHI:
			tmp = regs->hi;
			break;
		case MMLO:
			tmp = regs->lo;
			break;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
		case ACX:
			tmp = regs->acx;
			break;
#endif
		case FPC_CSR:
			tmp = child->thread.fpu.fcr31;
			break;
		case FPC_EIR: { /* implementation / version register */
			unsigned int flags;
#ifdef CONFIG_MIPS_MT_SMTC
			unsigned long irqflags;
			unsigned int mtflags;
#endif /* CONFIG_MIPS_MT_SMTC */

			preempt_disable();
			if (!cpu_has_fpu) {
				preempt_enable();
				break;
			}

#ifdef CONFIG_MIPS_MT_SMTC
			/* Read-modify-write of Status must be atomic */
			local_irq_save(irqflags);
			mtflags = dmt();
#endif /* CONFIG_MIPS_MT_SMTC */
			if (cpu_has_mipsmt) {
				unsigned int vpflags = dvpe();
				flags = read_c0_status();
				__enable_fpu();
				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
				write_c0_status(flags);
				evpe(vpflags);
			} else {
				flags = read_c0_status();
				__enable_fpu();
				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
				write_c0_status(flags);
			}
#ifdef CONFIG_MIPS_MT_SMTC
			emt(mtflags);
			local_irq_restore(irqflags);
#endif /* CONFIG_MIPS_MT_SMTC */
			preempt_enable();
			break;
		}
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			dregs = __get_dsp_regs(child);
			tmp = (unsigned long) (dregs[addr - DSP_BASE]);
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			tmp = child->thread.dsp.dspcontrol;
			break;
		default:
			tmp = 0;
			ret = -EIO;
			goto out;
		}
		ret = put_user(tmp, datalp);
		break;
	}

	/* when I and D space are separate, this will have to be fixed. */
	case PTRACE_POKETEXT: /* write the word at location addr. */
	case PTRACE_POKEDATA:
		ret = generic_ptrace_pokedata(child, addr, data);
		break;

	case PTRACE_POKEUSR: {
		struct pt_regs *regs;
		ret = 0;
		regs = task_pt_regs(child);

		switch (addr) {
		case 0 ... 31:
			regs->regs[addr] = data;
			break;
		case FPR_BASE ... FPR_BASE + 31: {
			fpureg_t *fregs = get_fpu_regs(child);

			if (!tsk_used_math(child)) {
				/* FP not yet used  */
				memset(&child->thread.fpu, ~0,
				       sizeof(child->thread.fpu));
				child->thread.fpu.fcr31 = 0;
			}
#ifdef CONFIG_32BIT
			/*
			 * The odd registers are actually the high order bits
			 * of the values stored in the even registers - unless
			 * we're using r2k_switch.S.
			 */
			if (addr & 1) {
				fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff;
				fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32;
			} else {
				fregs[addr - FPR_BASE] &= ~0xffffffffLL;
				fregs[addr - FPR_BASE] |= data;
			}
#endif
#ifdef CONFIG_64BIT
			fregs[addr - FPR_BASE] = data;
#endif
			break;
		}
		case PC:
			regs->cp0_epc = data;
			break;
		case MMHI:
			regs->hi = data;
			break;
		case MMLO:
			regs->lo = data;
			break;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
		case ACX:
			regs->acx = data;
			break;
#endif
		case FPC_CSR:
			child->thread.fpu.fcr31 = data;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}

			dregs = __get_dsp_regs(child);
			dregs[addr - DSP_BASE] = data;
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}
			child->thread.dsp.dspcontrol = data;
			break;
		default:
			/* The rest are not allowed. */
			ret = -EIO;
			break;
		}
		break;
		}

	case PTRACE_GETREGS:
		ret = ptrace_getregs(child, datavp);
		break;

	case PTRACE_SETREGS:
		ret = ptrace_setregs(child, datavp);
		break;

	case PTRACE_GETFPREGS:
		ret = ptrace_getfpregs(child, datavp);
		break;

	case PTRACE_SETFPREGS:
		ret = ptrace_setfpregs(child, datavp);
		break;

	case PTRACE_GET_THREAD_AREA:
		ret = put_user(task_thread_info(child)->tp_value, datalp);
		break;

	case PTRACE_GET_WATCH_REGS:
		ret = ptrace_get_watch_regs(child, addrp);
		break;

	case PTRACE_SET_WATCH_REGS:
		ret = ptrace_set_watch_regs(child, addrp);
		break;

	default:
		ret = ptrace_request(child, request, addr, data);
		break;
	}
 out:
	return ret;
}

static inline int audit_arch(void)
{
	int arch = EM_MIPS;
#ifdef CONFIG_64BIT
	arch |=	 __AUDIT_ARCH_64BIT;
#endif
#if defined(__LITTLE_ENDIAN)
	arch |=	 __AUDIT_ARCH_LE;
#endif
	return arch;
}

/*
 * Notification of system call entry/exit
 * - triggered by current->work.syscall_trace
 */
asmlinkage void syscall_trace_enter(struct pt_regs *regs)
{
	user_exit();

	/* do the secure computing check first */
	secure_computing_strict(regs->regs[2]);

	if (test_thread_flag(TIF_SYSCALL_TRACE))
		ptrace_report_syscall(regs);

	audit_syscall_entry(audit_arch(), regs->regs[2],
			    regs->regs[4], regs->regs[5],
			    regs->regs[6], regs->regs[7]);
}

/*
 * Notification of system call entry/exit
 * - triggered by current->work.syscall_trace
 */
asmlinkage void syscall_trace_leave(struct pt_regs *regs)
{
        /*
	 * We may come here right after calling schedule_user()
	 * or do_notify_resume(), in which case we can be in RCU
	 * user mode.
	 */
	user_exit();

	audit_syscall_exit(regs);

	if (test_thread_flag(TIF_SYSCALL_TRACE))
		tracehook_report_syscall_exit(regs, 0);

	user_enter();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1992 Ross Biro
	7	* Copyright (C) Linus Torvalds
	8	* Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
	9	* Copyright (C) 1996 David S. Miller
	10	* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	11	* Copyright (C) 1999 MIPS Technologies, Inc.
	12	* Copyright (C) 2000 Ulf Carlsson
	13	*
	14	* At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
	15	* binaries.
	16	*/
1da177e4	17	#include <linux/compiler.h>
c3fc5cd5	18	#include <linux/context_tracking.h>
1da177e4 LT	19	#include <linux/kernel.h>
	20	#include <linux/sched.h>
	21	#include <linux/mm.h>
	22	#include <linux/errno.h>
	23	#include <linux/ptrace.h>
1da177e4	24	#include <linux/smp.h>
1da177e4 LT	25	#include <linux/user.h>
1da177e4 LT	26	#include <linux/security.h>
bc3d22c1	27	#include <linux/tracehook.h>
293c5bd1 RB	28	#include <linux/audit.h>
293c5bd1 RB	29	#include <linux/seccomp.h>
1da177e4	30
f8280c8d	31	#include <asm/byteorder.h>
1da177e4	32	#include <asm/cpu.h>
e50c0a8f	33	#include <asm/dsp.h>
1da177e4 LT	34	#include <asm/fpu.h>
1da177e4 LT	35	#include <asm/mipsregs.h>
101b3531	36	#include <asm/mipsmtregs.h>
1da177e4 LT	37	#include <asm/pgtable.h>
1da177e4 LT	38	#include <asm/page.h>
1da177e4 LT	39	#include <asm/uaccess.h>
1da177e4 LT	40	#include <asm/bootinfo.h>
ea3d710f	41	#include <asm/reg.h>
1da177e4 LT	42
	43	/*
	44	* Called by kernel/ptrace.c when detaching..
	45	*
	46	* Make sure single step bits etc are not set.
	47	*/
	48	void ptrace_disable(struct task_struct *child)
	49	{
0926bf95 DD	50	/* Don't load the watchpoint registers for the ex-child. */
0926bf95 DD	51	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
1da177e4 LT	52	}
1da177e4 LT	53
ea3d710f	54	/*
70342287	55	* Read a general register set. We always use the 64-bit format, even
ea3d710f DJ	56	* for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
	57	* Registers are sign extended to fill the available space.
	58	*/
49a89efb	59	int ptrace_getregs(struct task_struct child, __s64 __user data)
ea3d710f DJ	60	{
	61	struct pt_regs *regs;
	62	int i;
	63
	64	if (!access_ok(VERIFY_WRITE, data, 38 * 8))
	65	return -EIO;
	66
40bc9c67	67	regs = task_pt_regs(child);
ea3d710f DJ	68
ea3d710f DJ	69	for (i = 0; i < 32; i++)
62b14c24 AN	70	__put_user((long)regs->regs[i], data + i);
	71	__put_user((long)regs->lo, data + EF_LO - EF_R0);
	72	__put_user((long)regs->hi, data + EF_HI - EF_R0);
	73	__put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
	74	__put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
	75	__put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
	76	__put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
ea3d710f DJ	77
	78	return 0;
	79	}
	80
	81	/*
	82	* Write a general register set. As for PTRACE_GETREGS, we always use
	83	* the 64-bit format. On a 32-bit kernel only the lower order half
	84	* (according to endianness) will be used.
	85	*/
49a89efb	86	int ptrace_setregs(struct task_struct child, __s64 __user data)
ea3d710f DJ	87	{
	88	struct pt_regs *regs;
	89	int i;
	90
	91	if (!access_ok(VERIFY_READ, data, 38 * 8))
	92	return -EIO;
	93
40bc9c67	94	regs = task_pt_regs(child);
ea3d710f DJ	95
ea3d710f DJ	96	for (i = 0; i < 32; i++)
49a89efb RB	97	__get_user(regs->regs[i], data + i);
	98	__get_user(regs->lo, data + EF_LO - EF_R0);
	99	__get_user(regs->hi, data + EF_HI - EF_R0);
	100	__get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
ea3d710f DJ	101
	102	/* badvaddr, status, and cause may not be written. */
	103
	104	return 0;
	105	}
	106
49a89efb	107	int ptrace_getfpregs(struct task_struct child, __u32 __user data)
ea3d710f DJ	108	{
ea3d710f DJ	109	int i;
e04582b7	110	unsigned int tmp;
ea3d710f DJ	111
	112	if (!access_ok(VERIFY_WRITE, data, 33 * 8))
	113	return -EIO;
	114
	115	if (tsk_used_math(child)) {
	116	fpureg_t *fregs = get_fpu_regs(child);
	117	for (i = 0; i < 32; i++)
49a89efb	118	__put_user(fregs[i], i + (__u64 __user *) data);
ea3d710f DJ	119	} else {
ea3d710f DJ	120	for (i = 0; i < 32; i++)
49a89efb	121	__put_user((__u64) -1, i + (__u64 __user *) data);
ea3d710f DJ	122	}
ea3d710f DJ	123
49a89efb	124	__put_user(child->thread.fpu.fcr31, data + 64);
eae89076	125
e04582b7	126	preempt_disable();
ea3d710f	127	if (cpu_has_fpu) {
e04582b7	128	unsigned int flags;
ea3d710f	129
101b3531 RB	130	if (cpu_has_mipsmt) {
	131	unsigned int vpflags = dvpe();
	132	flags = read_c0_status();
	133	__enable_fpu();
	134	__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
	135	write_c0_status(flags);
	136	evpe(vpflags);
	137	} else {
	138	flags = read_c0_status();
	139	__enable_fpu();
	140	__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
	141	write_c0_status(flags);
	142	}
ea3d710f	143	} else {
e04582b7	144	tmp = 0;
ea3d710f	145	}
e04582b7	146	preempt_enable();
49a89efb	147	__put_user(tmp, data + 65);
ea3d710f DJ	148
	149	return 0;
	150	}
	151
49a89efb	152	int ptrace_setfpregs(struct task_struct child, __u32 __user data)
ea3d710f DJ	153	{
	154	fpureg_t *fregs;
	155	int i;
	156
	157	if (!access_ok(VERIFY_READ, data, 33 * 8))
	158	return -EIO;
	159
	160	fregs = get_fpu_regs(child);
	161
	162	for (i = 0; i < 32; i++)
49a89efb	163	__get_user(fregs[i], i + (__u64 __user *) data);
ea3d710f	164
49a89efb	165	__get_user(child->thread.fpu.fcr31, data + 64);
ea3d710f DJ	166
	167	/* FIR may not be written. */
	168
	169	return 0;
	170	}
	171
0926bf95 DD	172	int ptrace_get_watch_regs(struct task_struct *child,
	173	struct pt_watch_regs __user *addr)
	174	{
	175	enum pt_watch_style style;
	176	int i;
	177
	178	if (!cpu_has_watch \|\| current_cpu_data.watch_reg_use_cnt == 0)
	179	return -EIO;
	180	if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
	181	return -EIO;
	182
	183	#ifdef CONFIG_32BIT
	184	style = pt_watch_style_mips32;
	185	#define WATCH_STYLE mips32
	186	#else
	187	style = pt_watch_style_mips64;
	188	#define WATCH_STYLE mips64
	189	#endif
	190
	191	__put_user(style, &addr->style);
	192	__put_user(current_cpu_data.watch_reg_use_cnt,
	193	&addr->WATCH_STYLE.num_valid);
	194	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
	195	__put_user(child->thread.watch.mips3264.watchlo[i],
	196	&addr->WATCH_STYLE.watchlo[i]);
	197	__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
	198	&addr->WATCH_STYLE.watchhi[i]);
	199	__put_user(current_cpu_data.watch_reg_masks[i],
	200	&addr->WATCH_STYLE.watch_masks[i]);
	201	}
	202	for (; i < 8; i++) {
	203	__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
	204	__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
	205	__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
	206	}
	207
	208	return 0;
	209	}
	210
	211	int ptrace_set_watch_regs(struct task_struct *child,
	212	struct pt_watch_regs __user *addr)
	213	{
	214	int i;
	215	int watch_active = 0;
	216	unsigned long lt[NUM_WATCH_REGS];
	217	u16 ht[NUM_WATCH_REGS];
	218
	219	if (!cpu_has_watch \|\| current_cpu_data.watch_reg_use_cnt == 0)
	220	return -EIO;
	221	if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
	222	return -EIO;
	223	/* Check the values. */
	224	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
	225	__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
	226	#ifdef CONFIG_32BIT
	227	if (lt[i] & __UA_LIMIT)
	228	return -EINVAL;
	229	#else
	230	if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
	231	if (lt[i] & 0xffffffff80000000UL)
	232	return -EINVAL;
	233	} else {
	234	if (lt[i] & __UA_LIMIT)
	235	return -EINVAL;
236	}
237	#endif
238	__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
239	if (ht[i] & ~0xff8)
240	return -EINVAL;
241	}
242	/* Install them. */
243	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
244	if (lt[i] & 7)
245	watch_active = 1;
246	child->thread.watch.mips3264.watchlo[i] = lt[i];
247	/* Set the G bit. */
248	child->thread.watch.mips3264.watchhi[i] = ht[i];
249	}
250
251	if (watch_active)
252	set_tsk_thread_flag(child, TIF_LOAD_WATCH);
253	else
254	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
255
256	return 0;
257	}
258
9b05a69e NK	259	long arch_ptrace(struct task_struct *child, long request,
9b05a69e NK	260	unsigned long addr, unsigned long data)
1da177e4	261	{
1da177e4	262	int ret;
fb671139 NK	263	void __user addrp = (void __user ) addr;
	264	void __user datavp = (void __user ) data;
	265	unsigned long __user datalp = (void __user ) data;
1da177e4	266
1da177e4 LT	267	switch (request) {
	268	/* when I and D space are separate, these will need to be fixed. */
	269	case PTRACE_PEEKTEXT: /* read word at location addr. */
76647323 AD	270	case PTRACE_PEEKDATA:
76647323 AD	271	ret = generic_ptrace_peekdata(child, addr, data);
1da177e4	272	break;
1da177e4 LT	273
	274	/* Read the word at location addr in the USER area. */
	275	case PTRACE_PEEKUSR: {
	276	struct pt_regs *regs;
	277	unsigned long tmp = 0;
	278
40bc9c67	279	regs = task_pt_regs(child);
1da177e4 LT	280	ret = 0; /* Default return value. */
	281
	282	switch (addr) {
	283	case 0 ... 31:
	284	tmp = regs->regs[addr];
	285	break;
	286	case FPR_BASE ... FPR_BASE + 31:
	287	if (tsk_used_math(child)) {
	288	fpureg_t *fregs = get_fpu_regs(child);
	289
875d43e7	290	#ifdef CONFIG_32BIT
1da177e4 LT	291	/*
	292	* The odd registers are actually the high
	293	* order bits of the values stored in the even
	294	* registers - unless we're using r2k_switch.S.
	295	*/
	296	if (addr & 1)
	297	tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32);
	298	else
	299	tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
	300	#endif
875d43e7	301	#ifdef CONFIG_64BIT
1da177e4 LT	302	tmp = fregs[addr - FPR_BASE];
	303	#endif
	304	} else {
	305	tmp = -1; /* FP not yet used */
	306	}
	307	break;
	308	case PC:
	309	tmp = regs->cp0_epc;
	310	break;
	311	case CAUSE:
	312	tmp = regs->cp0_cause;
	313	break;
	314	case BADVADDR:
	315	tmp = regs->cp0_badvaddr;
	316	break;
	317	case MMHI:
	318	tmp = regs->hi;
	319	break;
	320	case MMLO:
	321	tmp = regs->lo;
	322	break;
9693a853 FBH	323	#ifdef CONFIG_CPU_HAS_SMARTMIPS
	324	case ACX:
	325	tmp = regs->acx;
	326	break;
	327	#endif
1da177e4	328	case FPC_CSR:
eae89076	329	tmp = child->thread.fpu.fcr31;
1da177e4	330	break;
70342287	331	case FPC_EIR: { /* implementation / version register */
1da177e4	332	unsigned int flags;
41c594ab	333	#ifdef CONFIG_MIPS_MT_SMTC
b7e4226e	334	unsigned long irqflags;
41c594ab RB	335	unsigned int mtflags;
41c594ab RB	336	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4	337
e04582b7 AN	338	preempt_disable();
	339	if (!cpu_has_fpu) {
	340	preempt_enable();
1da177e4	341	break;
e04582b7	342	}
1da177e4	343
41c594ab RB	344	#ifdef CONFIG_MIPS_MT_SMTC
	345	/* Read-modify-write of Status must be atomic */
	346	local_irq_save(irqflags);
	347	mtflags = dmt();
	348	#endif /* CONFIG_MIPS_MT_SMTC */
101b3531 RB	349	if (cpu_has_mipsmt) {
	350	unsigned int vpflags = dvpe();
	351	flags = read_c0_status();
	352	__enable_fpu();
	353	__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
	354	write_c0_status(flags);
	355	evpe(vpflags);
	356	} else {
	357	flags = read_c0_status();
	358	__enable_fpu();
	359	__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
	360	write_c0_status(flags);
	361	}
41c594ab RB	362	#ifdef CONFIG_MIPS_MT_SMTC
	363	emt(mtflags);
	364	local_irq_restore(irqflags);
	365	#endif /* CONFIG_MIPS_MT_SMTC */
101b3531	366	preempt_enable();
1da177e4 LT	367	break;
1da177e4 LT	368	}
c134a5ec RB	369	case DSP_BASE ... DSP_BASE + 5: {
	370	dspreg_t *dregs;
	371
e50c0a8f RB	372	if (!cpu_has_dsp) {
	373	tmp = 0;
	374	ret = -EIO;
481bed45	375	goto out;
e50c0a8f	376	}
6c355852 RB	377	dregs = __get_dsp_regs(child);
6c355852 RB	378	tmp = (unsigned long) (dregs[addr - DSP_BASE]);
e50c0a8f	379	break;
c134a5ec	380	}
e50c0a8f RB	381	case DSP_CONTROL:
	382	if (!cpu_has_dsp) {
	383	tmp = 0;
	384	ret = -EIO;
481bed45	385	goto out;
e50c0a8f RB	386	}
	387	tmp = child->thread.dsp.dspcontrol;
	388	break;
1da177e4 LT	389	default:
	390	tmp = 0;
	391	ret = -EIO;
481bed45	392	goto out;
1da177e4	393	}
fb671139	394	ret = put_user(tmp, datalp);
1da177e4 LT	395	break;
	396	}
	397
	398	/* when I and D space are separate, this will have to be fixed. */
	399	case PTRACE_POKETEXT: /* write the word at location addr. */
	400	case PTRACE_POKEDATA:
f284ce72	401	ret = generic_ptrace_pokedata(child, addr, data);
1da177e4 LT	402	break;
	403
	404	case PTRACE_POKEUSR: {
	405	struct pt_regs *regs;
	406	ret = 0;
40bc9c67	407	regs = task_pt_regs(child);
1da177e4 LT	408
	409	switch (addr) {
	410	case 0 ... 31:
	411	regs->regs[addr] = data;
	412	break;
	413	case FPR_BASE ... FPR_BASE + 31: {
	414	fpureg_t *fregs = get_fpu_regs(child);
	415
	416	if (!tsk_used_math(child)) {
	417	/* FP not yet used */
eae89076 AN	418	memset(&child->thread.fpu, ~0,
	419	sizeof(child->thread.fpu));
	420	child->thread.fpu.fcr31 = 0;
1da177e4	421	}
875d43e7	422	#ifdef CONFIG_32BIT
1da177e4 LT	423	/*
	424	* The odd registers are actually the high order bits
	425	* of the values stored in the even registers - unless
	426	* we're using r2k_switch.S.
	427	*/
	428	if (addr & 1) {
	429	fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff;
	430	fregs[(addr & ~1) - FPR_BASE] \|= ((unsigned long long) data) << 32;
	431	} else {
	432	fregs[addr - FPR_BASE] &= ~0xffffffffLL;
	433	fregs[addr - FPR_BASE] \|= data;
	434	}
	435	#endif
875d43e7	436	#ifdef CONFIG_64BIT
1da177e4 LT	437	fregs[addr - FPR_BASE] = data;
	438	#endif
	439	break;
	440	}
	441	case PC:
	442	regs->cp0_epc = data;
	443	break;
	444	case MMHI:
	445	regs->hi = data;
	446	break;
	447	case MMLO:
	448	regs->lo = data;
	449	break;
9693a853 FBH	450	#ifdef CONFIG_CPU_HAS_SMARTMIPS
	451	case ACX:
	452	regs->acx = data;
	453	break;
	454	#endif
1da177e4	455	case FPC_CSR:
eae89076	456	child->thread.fpu.fcr31 = data;
1da177e4	457	break;
c134a5ec RB	458	case DSP_BASE ... DSP_BASE + 5: {
	459	dspreg_t *dregs;
	460
e50c0a8f RB	461	if (!cpu_has_dsp) {
	462	ret = -EIO;
	463	break;
	464	}
	465
c134a5ec	466	dregs = __get_dsp_regs(child);
e50c0a8f RB	467	dregs[addr - DSP_BASE] = data;
e50c0a8f RB	468	break;
c134a5ec	469	}
e50c0a8f RB	470	case DSP_CONTROL:
	471	if (!cpu_has_dsp) {
	472	ret = -EIO;
	473	break;
	474	}
	475	child->thread.dsp.dspcontrol = data;
	476	break;
1da177e4 LT	477	default:
	478	/* The rest are not allowed. */
	479	ret = -EIO;
	480	break;
	481	}
	482	break;
	483	}
	484
ea3d710f	485	case PTRACE_GETREGS:
fb671139	486	ret = ptrace_getregs(child, datavp);
ea3d710f DJ	487	break;
	488
	489	case PTRACE_SETREGS:
fb671139	490	ret = ptrace_setregs(child, datavp);
ea3d710f DJ	491	break;
	492
	493	case PTRACE_GETFPREGS:
fb671139	494	ret = ptrace_getfpregs(child, datavp);
ea3d710f DJ	495	break;
	496
	497	case PTRACE_SETFPREGS:
fb671139	498	ret = ptrace_setfpregs(child, datavp);
ea3d710f DJ	499	break;
ea3d710f DJ	500
3c37026d	501	case PTRACE_GET_THREAD_AREA:
fb671139	502	ret = put_user(task_thread_info(child)->tp_value, datalp);
3c37026d RB	503	break;
3c37026d RB	504
0926bf95	505	case PTRACE_GET_WATCH_REGS:
fb671139	506	ret = ptrace_get_watch_regs(child, addrp);
0926bf95 DD	507	break;
	508
	509	case PTRACE_SET_WATCH_REGS:
fb671139	510	ret = ptrace_set_watch_regs(child, addrp);
0926bf95 DD	511	break;
0926bf95 DD	512
1da177e4 LT	513	default:
	514	ret = ptrace_request(child, request, addr, data);
	515	break;
	516	}
481bed45	517	out:
1da177e4 LT	518	return ret;
	519	}
	520
67eb81e1	521	static inline int audit_arch(void)
2fd6f58b	522	{
f8280c8d	523	int arch = EM_MIPS;
875d43e7	524	#ifdef CONFIG_64BIT
70342287	525	arch \|= __AUDIT_ARCH_64BIT;
f8280c8d RB	526	#endif
f8280c8d RB	527	#if defined(__LITTLE_ENDIAN)
70342287	528	arch \|= __AUDIT_ARCH_LE;
f8280c8d RB	529	#endif
f8280c8d RB	530	return arch;
2fd6f58b	531	}
2fd6f58b	532
1da177e4 LT	533	/*
	534	* Notification of system call entry/exit
	535	* - triggered by current->work.syscall_trace
	536	*/
8b659a39	537	asmlinkage void syscall_trace_enter(struct pt_regs *regs)
1da177e4	538	{
c3fc5cd5 RB	539	user_exit();
c3fc5cd5 RB	540
293c5bd1	541	/* do the secure computing check first */
e4da89d0	542	secure_computing_strict(regs->regs[2]);
1da177e4	543
bc3d22c1 RB	544	if (test_thread_flag(TIF_SYSCALL_TRACE))
bc3d22c1 RB	545	ptrace_report_syscall(regs);
293c5bd1	546
b05d8447 EP	547	audit_syscall_entry(audit_arch(), regs->regs[2],
	548	regs->regs[4], regs->regs[5],
	549	regs->regs[6], regs->regs[7]);
1da177e4	550	}
8b659a39 RB	551
	552	/*
	553	* Notification of system call entry/exit
	554	* - triggered by current->work.syscall_trace
	555	*/
	556	asmlinkage void syscall_trace_leave(struct pt_regs *regs)
	557	{
c3fc5cd5 RB	558	/*
	559	* We may come here right after calling schedule_user()
	560	* or do_notify_resume(), in which case we can be in RCU
	561	* user mode.
	562	*/
	563	user_exit();
	564
d7e7528b	565	audit_syscall_exit(regs);
8b659a39	566
bc3d22c1 RB	567	if (test_thread_flag(TIF_SYSCALL_TRACE))
bc3d22c1 RB	568	tracehook_report_syscall_exit(regs, 0);
c3fc5cd5 RB	569
c3fc5cd5 RB	570	user_enter();
8b659a39	571	}