[deliverable/linux.git] / arch / mips / kernel / ptrace.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 Ross Biro
 * Copyright (C) Linus Torvalds
 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
 * Copyright (C) 1996 David S. Miller
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 1999 MIPS Technologies, Inc.
 * Copyright (C) 2000 Ulf Carlsson
 *
 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
 * binaries.
 */
#include <linux/compiler.h>
#include <linux/context_tracking.h>
#include <linux/elf.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
#include <linux/regset.h>
#include <linux/smp.h>
#include <linux/user.h>
#include <linux/security.h>
#include <linux/tracehook.h>
#include <linux/audit.h>
#include <linux/seccomp.h>
#include <linux/ftrace.h>

#include <asm/byteorder.h>
#include <asm/cpu.h>
#include <asm/dsp.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/syscall.h>
#include <asm/uaccess.h>
#include <asm/bootinfo.h>
#include <asm/reg.h>

#define CREATE_TRACE_POINTS
#include <trace/events/syscalls.h>

/*
 * Called by kernel/ptrace.c when detaching..
 *
 * Make sure single step bits etc are not set.
 */
void ptrace_disable(struct task_struct *child)
{
	/* Don't load the watchpoint registers for the ex-child. */
	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
}

/*
 * Read a general register set.	 We always use the 64-bit format, even
 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
 * Registers are sign extended to fill the available space.
 */
int ptrace_getregs(struct task_struct *child, __s64 __user *data)
{
	struct pt_regs *regs;
	int i;

	if (!access_ok(VERIFY_WRITE, data, 38 * 8))
		return -EIO;

	regs = task_pt_regs(child);

	for (i = 0; i < 32; i++)
		__put_user((long)regs->regs[i], data + i);
	__put_user((long)regs->lo, data + EF_LO - EF_R0);
	__put_user((long)regs->hi, data + EF_HI - EF_R0);
	__put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
	__put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
	__put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
	__put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);

	return 0;
}

/*
 * Write a general register set.  As for PTRACE_GETREGS, we always use
 * the 64-bit format.  On a 32-bit kernel only the lower order half
 * (according to endianness) will be used.
 */
int ptrace_setregs(struct task_struct *child, __s64 __user *data)
{
	struct pt_regs *regs;
	int i;

	if (!access_ok(VERIFY_READ, data, 38 * 8))
		return -EIO;

	regs = task_pt_regs(child);

	for (i = 0; i < 32; i++)
		__get_user(regs->regs[i], data + i);
	__get_user(regs->lo, data + EF_LO - EF_R0);
	__get_user(regs->hi, data + EF_HI - EF_R0);
	__get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);

	/* badvaddr, status, and cause may not be written.  */

	return 0;
}

int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
{
	int i;
	unsigned int tmp;

	if (!access_ok(VERIFY_WRITE, data, 33 * 8))
		return -EIO;

	if (tsk_used_math(child)) {
		union fpureg *fregs = get_fpu_regs(child);
		for (i = 0; i < 32; i++)
			__put_user(get_fpr64(&fregs[i], 0),
				   i + (__u64 __user *)data);
	} else {
		for (i = 0; i < 32; i++)
			__put_user((__u64) -1, i + (__u64 __user *) data);
	}

	__put_user(child->thread.fpu.fcr31, data + 64);

	preempt_disable();
	if (cpu_has_fpu) {
		unsigned int flags;

		if (cpu_has_mipsmt) {
			unsigned int vpflags = dvpe();
			flags = read_c0_status();
			__enable_fpu(FPU_AS_IS);
			__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
			write_c0_status(flags);
			evpe(vpflags);
		} else {
			flags = read_c0_status();
			__enable_fpu(FPU_AS_IS);
			__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
			write_c0_status(flags);
		}
	} else {
		tmp = 0;
	}
	preempt_enable();
	__put_user(tmp, data + 65);

	return 0;
}

int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
{
	union fpureg *fregs;
	u64 fpr_val;
	int i;

	if (!access_ok(VERIFY_READ, data, 33 * 8))
		return -EIO;

	fregs = get_fpu_regs(child);

	for (i = 0; i < 32; i++) {
		__get_user(fpr_val, i + (__u64 __user *)data);
		set_fpr64(&fregs[i], 0, fpr_val);
	}

	__get_user(child->thread.fpu.fcr31, data + 64);

	/* FIR may not be written.  */

	return 0;
}

int ptrace_get_watch_regs(struct task_struct *child,
			  struct pt_watch_regs __user *addr)
{
	enum pt_watch_style style;
	int i;

	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
		return -EIO;
	if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
		return -EIO;

#ifdef CONFIG_32BIT
	style = pt_watch_style_mips32;
#define WATCH_STYLE mips32
#else
	style = pt_watch_style_mips64;
#define WATCH_STYLE mips64
#endif

	__put_user(style, &addr->style);
	__put_user(current_cpu_data.watch_reg_use_cnt,
		   &addr->WATCH_STYLE.num_valid);
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		__put_user(child->thread.watch.mips3264.watchlo[i],
			   &addr->WATCH_STYLE.watchlo[i]);
		__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
			   &addr->WATCH_STYLE.watchhi[i]);
		__put_user(current_cpu_data.watch_reg_masks[i],
			   &addr->WATCH_STYLE.watch_masks[i]);
	}
	for (; i < 8; i++) {
		__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
		__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
		__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
	}

	return 0;
}

int ptrace_set_watch_regs(struct task_struct *child,
			  struct pt_watch_regs __user *addr)
{
	int i;
	int watch_active = 0;
	unsigned long lt[NUM_WATCH_REGS];
	u16 ht[NUM_WATCH_REGS];

	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
		return -EIO;
	if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
		return -EIO;
	/* Check the values. */
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
#ifdef CONFIG_32BIT
		if (lt[i] & __UA_LIMIT)
			return -EINVAL;
#else
		if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
			if (lt[i] & 0xffffffff80000000UL)
				return -EINVAL;
		} else {
			if (lt[i] & __UA_LIMIT)
				return -EINVAL;
		}
#endif
		__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
		if (ht[i] & ~0xff8)
			return -EINVAL;
	}
	/* Install them. */
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		if (lt[i] & 7)
			watch_active = 1;
		child->thread.watch.mips3264.watchlo[i] = lt[i];
		/* Set the G bit. */
		child->thread.watch.mips3264.watchhi[i] = ht[i];
	}

	if (watch_active)
		set_tsk_thread_flag(child, TIF_LOAD_WATCH);
	else
		clear_tsk_thread_flag(child, TIF_LOAD_WATCH);

	return 0;
}

/* regset get/set implementations */

static int gpr_get(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   void *kbuf, void __user *ubuf)
{
	struct pt_regs *regs = task_pt_regs(target);

	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
				   regs, 0, sizeof(*regs));
}

static int gpr_set(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   const void *kbuf, const void __user *ubuf)
{
	struct pt_regs newregs;
	int ret;

	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
				 &newregs,
				 0, sizeof(newregs));
	if (ret)
		return ret;

	*task_pt_regs(target) = newregs;

	return 0;
}

static int fpr_get(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   void *kbuf, void __user *ubuf)
{
	unsigned i;
	int err;
	u64 fpr_val;

	/* XXX fcr31  */

	if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
		return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
					   &target->thread.fpu,
					   0, sizeof(elf_fpregset_t));

	for (i = 0; i < NUM_FPU_REGS; i++) {
		fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0);
		err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
					  &fpr_val, i * sizeof(elf_fpreg_t),
					  (i + 1) * sizeof(elf_fpreg_t));
		if (err)
			return err;
	}

	return 0;
}

static int fpr_set(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   const void *kbuf, const void __user *ubuf)
{
	unsigned i;
	int err;
	u64 fpr_val;

	/* XXX fcr31  */

	if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
		return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
					  &target->thread.fpu,
					  0, sizeof(elf_fpregset_t));

	for (i = 0; i < NUM_FPU_REGS; i++) {
		err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
					 &fpr_val, i * sizeof(elf_fpreg_t),
					 (i + 1) * sizeof(elf_fpreg_t));
		if (err)
			return err;
		set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);
	}

	return 0;
}

enum mips_regset {
	REGSET_GPR,
	REGSET_FPR,
};

static const struct user_regset mips_regsets[] = {
	[REGSET_GPR] = {
		.core_note_type	= NT_PRSTATUS,
		.n		= ELF_NGREG,
		.size		= sizeof(unsigned int),
		.align		= sizeof(unsigned int),
		.get		= gpr_get,
		.set		= gpr_set,
	},
	[REGSET_FPR] = {
		.core_note_type	= NT_PRFPREG,
		.n		= ELF_NFPREG,
		.size		= sizeof(elf_fpreg_t),
		.align		= sizeof(elf_fpreg_t),
		.get		= fpr_get,
		.set		= fpr_set,
	},
};

static const struct user_regset_view user_mips_view = {
	.name		= "mips",
	.e_machine	= ELF_ARCH,
	.ei_osabi	= ELF_OSABI,
	.regsets	= mips_regsets,
	.n		= ARRAY_SIZE(mips_regsets),
};

static const struct user_regset mips64_regsets[] = {
	[REGSET_GPR] = {
		.core_note_type	= NT_PRSTATUS,
		.n		= ELF_NGREG,
		.size		= sizeof(unsigned long),
		.align		= sizeof(unsigned long),
		.get		= gpr_get,
		.set		= gpr_set,
	},
	[REGSET_FPR] = {
		.core_note_type	= NT_PRFPREG,
		.n		= ELF_NFPREG,
		.size		= sizeof(elf_fpreg_t),
		.align		= sizeof(elf_fpreg_t),
		.get		= fpr_get,
		.set		= fpr_set,
	},
};

static const struct user_regset_view user_mips64_view = {
	.name		= "mips",
	.e_machine	= ELF_ARCH,
	.ei_osabi	= ELF_OSABI,
	.regsets	= mips64_regsets,
	.n		= ARRAY_SIZE(mips_regsets),
};

const struct user_regset_view *task_user_regset_view(struct task_struct *task)
{
#ifdef CONFIG_32BIT
	return &user_mips_view;
#endif

#ifdef CONFIG_MIPS32_O32
		if (test_thread_flag(TIF_32BIT_REGS))
			return &user_mips_view;
#endif

	return &user_mips64_view;
}

long arch_ptrace(struct task_struct *child, long request,
		 unsigned long addr, unsigned long data)
{
	int ret;
	void __user *addrp = (void __user *) addr;
	void __user *datavp = (void __user *) data;
	unsigned long __user *datalp = (void __user *) data;

	switch (request) {
	/* when I and D space are separate, these will need to be fixed. */
	case PTRACE_PEEKTEXT: /* read word at location addr. */
	case PTRACE_PEEKDATA:
		ret = generic_ptrace_peekdata(child, addr, data);
		break;

	/* Read the word at location addr in the USER area. */
	case PTRACE_PEEKUSR: {
		struct pt_regs *regs;
		union fpureg *fregs;
		unsigned long tmp = 0;

		regs = task_pt_regs(child);
		ret = 0;  /* Default return value. */

		switch (addr) {
		case 0 ... 31:
			tmp = regs->regs[addr];
			break;
		case FPR_BASE ... FPR_BASE + 31:
			if (!tsk_used_math(child)) {
				/* FP not yet used */
				tmp = -1;
				break;
			}
			fregs = get_fpu_regs(child);

#ifdef CONFIG_32BIT
			if (test_thread_flag(TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
						addr & 1);
				break;
			}
#endif
			tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
			break;
		case PC:
			tmp = regs->cp0_epc;
			break;
		case CAUSE:
			tmp = regs->cp0_cause;
			break;
		case BADVADDR:
			tmp = regs->cp0_badvaddr;
			break;
		case MMHI:
			tmp = regs->hi;
			break;
		case MMLO:
			tmp = regs->lo;
			break;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
		case ACX:
			tmp = regs->acx;
			break;
#endif
		case FPC_CSR:
			tmp = child->thread.fpu.fcr31;
			break;
		case FPC_EIR: { /* implementation / version register */
			unsigned int flags;
#ifdef CONFIG_MIPS_MT_SMTC
			unsigned long irqflags;
			unsigned int mtflags;
#endif /* CONFIG_MIPS_MT_SMTC */

			preempt_disable();
			if (!cpu_has_fpu) {
				preempt_enable();
				break;
			}

#ifdef CONFIG_MIPS_MT_SMTC
			/* Read-modify-write of Status must be atomic */
			local_irq_save(irqflags);
			mtflags = dmt();
#endif /* CONFIG_MIPS_MT_SMTC */
			if (cpu_has_mipsmt) {
				unsigned int vpflags = dvpe();
				flags = read_c0_status();
				__enable_fpu(FPU_AS_IS);
				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
				write_c0_status(flags);
				evpe(vpflags);
			} else {
				flags = read_c0_status();
				__enable_fpu(FPU_AS_IS);
				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
				write_c0_status(flags);
			}
#ifdef CONFIG_MIPS_MT_SMTC
			emt(mtflags);
			local_irq_restore(irqflags);
#endif /* CONFIG_MIPS_MT_SMTC */
			preempt_enable();
			break;
		}
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			dregs = __get_dsp_regs(child);
			tmp = (unsigned long) (dregs[addr - DSP_BASE]);
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			tmp = child->thread.dsp.dspcontrol;
			break;
		default:
			tmp = 0;
			ret = -EIO;
			goto out;
		}
		ret = put_user(tmp, datalp);
		break;
	}

	/* when I and D space are separate, this will have to be fixed. */
	case PTRACE_POKETEXT: /* write the word at location addr. */
	case PTRACE_POKEDATA:
		ret = generic_ptrace_pokedata(child, addr, data);
		break;

	case PTRACE_POKEUSR: {
		struct pt_regs *regs;
		ret = 0;
		regs = task_pt_regs(child);

		switch (addr) {
		case 0 ... 31:
			regs->regs[addr] = data;
			break;
		case FPR_BASE ... FPR_BASE + 31: {
			union fpureg *fregs = get_fpu_regs(child);

			if (!tsk_used_math(child)) {
				/* FP not yet used  */
				memset(&child->thread.fpu, ~0,
				       sizeof(child->thread.fpu));
				child->thread.fpu.fcr31 = 0;
			}
#ifdef CONFIG_32BIT
			if (test_thread_flag(TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
					  addr & 1, data);
				break;
			}
#endif
			set_fpr64(&fregs[addr - FPR_BASE], 0, data);
			break;
		}
		case PC:
			regs->cp0_epc = data;
			break;
		case MMHI:
			regs->hi = data;
			break;
		case MMLO:
			regs->lo = data;
			break;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
		case ACX:
			regs->acx = data;
			break;
#endif
		case FPC_CSR:
			child->thread.fpu.fcr31 = data;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}

			dregs = __get_dsp_regs(child);
			dregs[addr - DSP_BASE] = data;
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}
			child->thread.dsp.dspcontrol = data;
			break;
		default:
			/* The rest are not allowed. */
			ret = -EIO;
			break;
		}
		break;
		}

	case PTRACE_GETREGS:
		ret = ptrace_getregs(child, datavp);
		break;

	case PTRACE_SETREGS:
		ret = ptrace_setregs(child, datavp);
		break;

	case PTRACE_GETFPREGS:
		ret = ptrace_getfpregs(child, datavp);
		break;

	case PTRACE_SETFPREGS:
		ret = ptrace_setfpregs(child, datavp);
		break;

	case PTRACE_GET_THREAD_AREA:
		ret = put_user(task_thread_info(child)->tp_value, datalp);
		break;

	case PTRACE_GET_WATCH_REGS:
		ret = ptrace_get_watch_regs(child, addrp);
		break;

	case PTRACE_SET_WATCH_REGS:
		ret = ptrace_set_watch_regs(child, addrp);
		break;

	default:
		ret = ptrace_request(child, request, addr, data);
		break;
	}
 out:
	return ret;
}

/*
 * Notification of system call entry/exit
 * - triggered by current->work.syscall_trace
 */
asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
{
	long ret = 0;
	user_exit();

	if (secure_computing(syscall) == -1)
		return -1;

	if (test_thread_flag(TIF_SYSCALL_TRACE) &&
	    tracehook_report_syscall_entry(regs))
		ret = -1;

	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
		trace_sys_enter(regs, regs->regs[2]);

	audit_syscall_entry(syscall_get_arch(current, regs),
			    syscall,
			    regs->regs[4], regs->regs[5],
			    regs->regs[6], regs->regs[7]);
	return syscall;
}

/*
 * Notification of system call entry/exit
 * - triggered by current->work.syscall_trace
 */
asmlinkage void syscall_trace_leave(struct pt_regs *regs)
{
        /*
	 * We may come here right after calling schedule_user()
	 * or do_notify_resume(), in which case we can be in RCU
	 * user mode.
	 */
	user_exit();

	audit_syscall_exit(regs);

	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
		trace_sys_exit(regs, regs->regs[2]);

	if (test_thread_flag(TIF_SYSCALL_TRACE))
		tracehook_report_syscall_exit(regs, 0);

	user_enter();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1992 Ross Biro
	7	* Copyright (C) Linus Torvalds
	8	* Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
	9	* Copyright (C) 1996 David S. Miller
	10	* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	11	* Copyright (C) 1999 MIPS Technologies, Inc.
	12	* Copyright (C) 2000 Ulf Carlsson
	13	*
	14	* At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
	15	* binaries.
	16	*/
1da177e4	17	#include <linux/compiler.h>
c3fc5cd5	18	#include <linux/context_tracking.h>
7aeb753b	19	#include <linux/elf.h>
1da177e4 LT	20	#include <linux/kernel.h>
	21	#include <linux/sched.h>
	22	#include <linux/mm.h>
	23	#include <linux/errno.h>
	24	#include <linux/ptrace.h>
7aeb753b	25	#include <linux/regset.h>
1da177e4	26	#include <linux/smp.h>
1da177e4 LT	27	#include <linux/user.h>
1da177e4 LT	28	#include <linux/security.h>
bc3d22c1	29	#include <linux/tracehook.h>
293c5bd1 RB	30	#include <linux/audit.h>
293c5bd1 RB	31	#include <linux/seccomp.h>
1d7bf993	32	#include <linux/ftrace.h>
1da177e4	33
f8280c8d	34	#include <asm/byteorder.h>
1da177e4	35	#include <asm/cpu.h>
e50c0a8f	36	#include <asm/dsp.h>
1da177e4 LT	37	#include <asm/fpu.h>
1da177e4 LT	38	#include <asm/mipsregs.h>
101b3531	39	#include <asm/mipsmtregs.h>
1da177e4 LT	40	#include <asm/pgtable.h>
1da177e4 LT	41	#include <asm/page.h>
bec9b2b2	42	#include <asm/syscall.h>
1da177e4 LT	43	#include <asm/uaccess.h>
1da177e4 LT	44	#include <asm/bootinfo.h>
ea3d710f	45	#include <asm/reg.h>
1da177e4	46
1d7bf993 RB	47	#define CREATE_TRACE_POINTS
	48	#include <trace/events/syscalls.h>
	49
1da177e4 LT	50	/*
	51	* Called by kernel/ptrace.c when detaching..
	52	*
	53	* Make sure single step bits etc are not set.
	54	*/
	55	void ptrace_disable(struct task_struct *child)
	56	{
0926bf95 DD	57	/* Don't load the watchpoint registers for the ex-child. */
0926bf95 DD	58	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
1da177e4 LT	59	}
1da177e4 LT	60
ea3d710f	61	/*
70342287	62	* Read a general register set. We always use the 64-bit format, even
ea3d710f DJ	63	* for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
	64	* Registers are sign extended to fill the available space.
	65	*/
49a89efb	66	int ptrace_getregs(struct task_struct child, __s64 __user data)
ea3d710f DJ	67	{
	68	struct pt_regs *regs;
	69	int i;
	70
	71	if (!access_ok(VERIFY_WRITE, data, 38 * 8))
	72	return -EIO;
	73
40bc9c67	74	regs = task_pt_regs(child);
ea3d710f DJ	75
ea3d710f DJ	76	for (i = 0; i < 32; i++)
62b14c24 AN	77	__put_user((long)regs->regs[i], data + i);
	78	__put_user((long)regs->lo, data + EF_LO - EF_R0);
	79	__put_user((long)regs->hi, data + EF_HI - EF_R0);
	80	__put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
	81	__put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
	82	__put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
	83	__put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
ea3d710f DJ	84
	85	return 0;
	86	}
	87
	88	/*
	89	* Write a general register set. As for PTRACE_GETREGS, we always use
	90	* the 64-bit format. On a 32-bit kernel only the lower order half
	91	* (according to endianness) will be used.
	92	*/
49a89efb	93	int ptrace_setregs(struct task_struct child, __s64 __user data)
ea3d710f DJ	94	{
	95	struct pt_regs *regs;
	96	int i;
	97
	98	if (!access_ok(VERIFY_READ, data, 38 * 8))
	99	return -EIO;
	100
40bc9c67	101	regs = task_pt_regs(child);
ea3d710f DJ	102
ea3d710f DJ	103	for (i = 0; i < 32; i++)
49a89efb RB	104	__get_user(regs->regs[i], data + i);
	105	__get_user(regs->lo, data + EF_LO - EF_R0);
	106	__get_user(regs->hi, data + EF_HI - EF_R0);
	107	__get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
ea3d710f DJ	108
	109	/* badvaddr, status, and cause may not be written. */
	110
	111	return 0;
	112	}
	113
49a89efb	114	int ptrace_getfpregs(struct task_struct child, __u32 __user data)
ea3d710f DJ	115	{
ea3d710f DJ	116	int i;
e04582b7	117	unsigned int tmp;
ea3d710f DJ	118
	119	if (!access_ok(VERIFY_WRITE, data, 33 * 8))
	120	return -EIO;
	121
	122	if (tsk_used_math(child)) {
bbd426f5	123	union fpureg *fregs = get_fpu_regs(child);
ea3d710f	124	for (i = 0; i < 32; i++)
bbd426f5 PB	125	__put_user(get_fpr64(&fregs[i], 0),
bbd426f5 PB	126	i + (__u64 __user *)data);
ea3d710f DJ	127	} else {
ea3d710f DJ	128	for (i = 0; i < 32; i++)
49a89efb	129	__put_user((__u64) -1, i + (__u64 __user *) data);
ea3d710f DJ	130	}
ea3d710f DJ	131
49a89efb	132	__put_user(child->thread.fpu.fcr31, data + 64);
eae89076	133
e04582b7	134	preempt_disable();
ea3d710f	135	if (cpu_has_fpu) {
e04582b7	136	unsigned int flags;
ea3d710f	137
101b3531 RB	138	if (cpu_has_mipsmt) {
	139	unsigned int vpflags = dvpe();
	140	flags = read_c0_status();
597ce172	141	__enable_fpu(FPU_AS_IS);
101b3531 RB	142	__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
	143	write_c0_status(flags);
	144	evpe(vpflags);
	145	} else {
	146	flags = read_c0_status();
597ce172	147	__enable_fpu(FPU_AS_IS);
101b3531 RB	148	__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
	149	write_c0_status(flags);
	150	}
ea3d710f	151	} else {
e04582b7	152	tmp = 0;
ea3d710f	153	}
e04582b7	154	preempt_enable();
49a89efb	155	__put_user(tmp, data + 65);
ea3d710f DJ	156
	157	return 0;
	158	}
	159
49a89efb	160	int ptrace_setfpregs(struct task_struct child, __u32 __user data)
ea3d710f	161	{
bbd426f5 PB	162	union fpureg *fregs;
bbd426f5 PB	163	u64 fpr_val;
ea3d710f DJ	164	int i;
	165
	166	if (!access_ok(VERIFY_READ, data, 33 * 8))
	167	return -EIO;
	168
	169	fregs = get_fpu_regs(child);
	170
bbd426f5 PB	171	for (i = 0; i < 32; i++) {
	172	__get_user(fpr_val, i + (__u64 __user *)data);
	173	set_fpr64(&fregs[i], 0, fpr_val);
	174	}
ea3d710f	175
49a89efb	176	__get_user(child->thread.fpu.fcr31, data + 64);
ea3d710f DJ	177
	178	/* FIR may not be written. */
	179
	180	return 0;
	181	}
	182
0926bf95 DD	183	int ptrace_get_watch_regs(struct task_struct *child,
	184	struct pt_watch_regs __user *addr)
	185	{
	186	enum pt_watch_style style;
	187	int i;
	188
	189	if (!cpu_has_watch \|\| current_cpu_data.watch_reg_use_cnt == 0)
	190	return -EIO;
	191	if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
	192	return -EIO;
	193
	194	#ifdef CONFIG_32BIT
	195	style = pt_watch_style_mips32;
	196	#define WATCH_STYLE mips32
	197	#else
	198	style = pt_watch_style_mips64;
	199	#define WATCH_STYLE mips64
	200	#endif
	201
	202	__put_user(style, &addr->style);
	203	__put_user(current_cpu_data.watch_reg_use_cnt,
	204	&addr->WATCH_STYLE.num_valid);
	205	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
	206	__put_user(child->thread.watch.mips3264.watchlo[i],
	207	&addr->WATCH_STYLE.watchlo[i]);
	208	__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
	209	&addr->WATCH_STYLE.watchhi[i]);
	210	__put_user(current_cpu_data.watch_reg_masks[i],
	211	&addr->WATCH_STYLE.watch_masks[i]);
	212	}
	213	for (; i < 8; i++) {
	214	__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
	215	__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
	216	__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
	217	}
	218
	219	return 0;
	220	}
	221
	222	int ptrace_set_watch_regs(struct task_struct *child,
	223	struct pt_watch_regs __user *addr)
	224	{
	225	int i;
	226	int watch_active = 0;
	227	unsigned long lt[NUM_WATCH_REGS];
	228	u16 ht[NUM_WATCH_REGS];
	229
	230	if (!cpu_has_watch \|\| current_cpu_data.watch_reg_use_cnt == 0)
	231	return -EIO;
	232	if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
	233	return -EIO;
	234	/* Check the values. */
	235	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
	236	__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
	237	#ifdef CONFIG_32BIT
	238	if (lt[i] & __UA_LIMIT)
	239	return -EINVAL;
	240	#else
	241	if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
	242	if (lt[i] & 0xffffffff80000000UL)
	243	return -EINVAL;
	244	} else {
	245	if (lt[i] & __UA_LIMIT)
	246	return -EINVAL;
247	}
248	#endif
249	__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
250	if (ht[i] & ~0xff8)
251	return -EINVAL;
252	}
253	/* Install them. */
254	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
255	if (lt[i] & 7)
256	watch_active = 1;
257	child->thread.watch.mips3264.watchlo[i] = lt[i];
258	/* Set the G bit. */
259	child->thread.watch.mips3264.watchhi[i] = ht[i];
260	}
261
262	if (watch_active)
263	set_tsk_thread_flag(child, TIF_LOAD_WATCH);
264	else
265	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
266
267	return 0;
268	}
269
7aeb753b RB	270	/* regset get/set implementations */
	271
	272	static int gpr_get(struct task_struct *target,
	273	const struct user_regset *regset,
	274	unsigned int pos, unsigned int count,
	275	void kbuf, void __user ubuf)
	276	{
	277	struct pt_regs *regs = task_pt_regs(target);
	278
	279	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
	280	regs, 0, sizeof(*regs));
	281	}
	282
	283	static int gpr_set(struct task_struct *target,
	284	const struct user_regset *regset,
	285	unsigned int pos, unsigned int count,
	286	const void kbuf, const void __user ubuf)
	287	{
	288	struct pt_regs newregs;
	289	int ret;
	290
	291	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
	292	&newregs,
	293	0, sizeof(newregs));
	294	if (ret)
	295	return ret;
	296
	297	*task_pt_regs(target) = newregs;
	298
	299	return 0;
	300	}
	301
	302	static int fpr_get(struct task_struct *target,
	303	const struct user_regset *regset,
	304	unsigned int pos, unsigned int count,
	305	void kbuf, void __user ubuf)
	306	{
72b22bba PB	307	unsigned i;
	308	int err;
	309	u64 fpr_val;
	310
7aeb753b	311	/* XXX fcr31 */
72b22bba PB	312
	313	if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
	314	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
	315	&target->thread.fpu,
	316	0, sizeof(elf_fpregset_t));
	317
	318	for (i = 0; i < NUM_FPU_REGS; i++) {
	319	fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0);
	320	err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
	321	&fpr_val, i * sizeof(elf_fpreg_t),
	322	(i + 1) * sizeof(elf_fpreg_t));
	323	if (err)
	324	return err;
	325	}
	326
	327	return 0;
7aeb753b RB	328	}
	329
	330	static int fpr_set(struct task_struct *target,
	331	const struct user_regset *regset,
	332	unsigned int pos, unsigned int count,
	333	const void kbuf, const void __user ubuf)
	334	{
72b22bba PB	335	unsigned i;
	336	int err;
	337	u64 fpr_val;
	338
7aeb753b	339	/* XXX fcr31 */
72b22bba PB	340
	341	if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
	342	return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
	343	&target->thread.fpu,
	344	0, sizeof(elf_fpregset_t));
	345
	346	for (i = 0; i < NUM_FPU_REGS; i++) {
	347	err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
	348	&fpr_val, i * sizeof(elf_fpreg_t),
	349	(i + 1) * sizeof(elf_fpreg_t));
	350	if (err)
	351	return err;
	352	set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);
	353	}
	354
	355	return 0;
7aeb753b RB	356	}
	357
	358	enum mips_regset {
	359	REGSET_GPR,
	360	REGSET_FPR,
	361	};
	362
	363	static const struct user_regset mips_regsets[] = {
	364	[REGSET_GPR] = {
	365	.core_note_type = NT_PRSTATUS,
	366	.n = ELF_NGREG,
	367	.size = sizeof(unsigned int),
	368	.align = sizeof(unsigned int),
	369	.get = gpr_get,
	370	.set = gpr_set,
	371	},
	372	[REGSET_FPR] = {
	373	.core_note_type = NT_PRFPREG,
	374	.n = ELF_NFPREG,
	375	.size = sizeof(elf_fpreg_t),
	376	.align = sizeof(elf_fpreg_t),
	377	.get = fpr_get,
	378	.set = fpr_set,
	379	},
	380	};
	381
	382	static const struct user_regset_view user_mips_view = {
	383	.name = "mips",
	384	.e_machine = ELF_ARCH,
	385	.ei_osabi = ELF_OSABI,
	386	.regsets = mips_regsets,
	387	.n = ARRAY_SIZE(mips_regsets),
	388	};
	389
	390	static const struct user_regset mips64_regsets[] = {
	391	[REGSET_GPR] = {
	392	.core_note_type = NT_PRSTATUS,
	393	.n = ELF_NGREG,
	394	.size = sizeof(unsigned long),
	395	.align = sizeof(unsigned long),
	396	.get = gpr_get,
	397	.set = gpr_set,
	398	},
	399	[REGSET_FPR] = {
	400	.core_note_type = NT_PRFPREG,
	401	.n = ELF_NFPREG,
	402	.size = sizeof(elf_fpreg_t),
	403	.align = sizeof(elf_fpreg_t),
	404	.get = fpr_get,
	405	.set = fpr_set,
	406	},
	407	};
	408
	409	static const struct user_regset_view user_mips64_view = {
	410	.name = "mips",
	411	.e_machine = ELF_ARCH,
	412	.ei_osabi = ELF_OSABI,
	413	.regsets = mips64_regsets,
	414	.n = ARRAY_SIZE(mips_regsets),
	415	};
	416
	417	const struct user_regset_view task_user_regset_view(struct task_struct task)
	418	{
	419	#ifdef CONFIG_32BIT
420	return &user_mips_view;
421	#endif
422
423	#ifdef CONFIG_MIPS32_O32
424	if (test_thread_flag(TIF_32BIT_REGS))
425	return &user_mips_view;
426	#endif
427
428	return &user_mips64_view;
429	}
430
9b05a69e NK	431	long arch_ptrace(struct task_struct *child, long request,
9b05a69e NK	432	unsigned long addr, unsigned long data)
1da177e4	433	{
1da177e4	434	int ret;
fb671139 NK	435	void __user addrp = (void __user ) addr;
	436	void __user datavp = (void __user ) data;
	437	unsigned long __user datalp = (void __user ) data;
1da177e4	438
1da177e4 LT	439	switch (request) {
	440	/* when I and D space are separate, these will need to be fixed. */
	441	case PTRACE_PEEKTEXT: /* read word at location addr. */
76647323 AD	442	case PTRACE_PEEKDATA:
76647323 AD	443	ret = generic_ptrace_peekdata(child, addr, data);
1da177e4	444	break;
1da177e4 LT	445
	446	/* Read the word at location addr in the USER area. */
	447	case PTRACE_PEEKUSR: {
	448	struct pt_regs *regs;
bbd426f5	449	union fpureg *fregs;
1da177e4 LT	450	unsigned long tmp = 0;
1da177e4 LT	451
40bc9c67	452	regs = task_pt_regs(child);
1da177e4 LT	453	ret = 0; /* Default return value. */
	454
	455	switch (addr) {
	456	case 0 ... 31:
	457	tmp = regs->regs[addr];
	458	break;
	459	case FPR_BASE ... FPR_BASE + 31:
597ce172 PB	460	if (!tsk_used_math(child)) {
	461	/* FP not yet used */
	462	tmp = -1;
	463	break;
	464	}
	465	fregs = get_fpu_regs(child);
1da177e4	466
875d43e7	467	#ifdef CONFIG_32BIT
597ce172	468	if (test_thread_flag(TIF_32BIT_FPREGS)) {
1da177e4 LT	469	/*
	470	* The odd registers are actually the high
	471	* order bits of the values stored in the even
	472	* registers - unless we're using r2k_switch.S.
	473	*/
bbd426f5 PB	474	tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
bbd426f5 PB	475	addr & 1);
597ce172	476	break;
1da177e4	477	}
597ce172	478	#endif
bbd426f5	479	tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
1da177e4 LT	480	break;
	481	case PC:
	482	tmp = regs->cp0_epc;
	483	break;
	484	case CAUSE:
	485	tmp = regs->cp0_cause;
	486	break;
	487	case BADVADDR:
	488	tmp = regs->cp0_badvaddr;
	489	break;
	490	case MMHI:
	491	tmp = regs->hi;
	492	break;
	493	case MMLO:
	494	tmp = regs->lo;
	495	break;
9693a853 FBH	496	#ifdef CONFIG_CPU_HAS_SMARTMIPS
	497	case ACX:
	498	tmp = regs->acx;
	499	break;
	500	#endif
1da177e4	501	case FPC_CSR:
eae89076	502	tmp = child->thread.fpu.fcr31;
1da177e4	503	break;
70342287	504	case FPC_EIR: { /* implementation / version register */
1da177e4	505	unsigned int flags;
41c594ab	506	#ifdef CONFIG_MIPS_MT_SMTC
b7e4226e	507	unsigned long irqflags;
41c594ab RB	508	unsigned int mtflags;
41c594ab RB	509	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4	510
e04582b7 AN	511	preempt_disable();
	512	if (!cpu_has_fpu) {
	513	preempt_enable();
1da177e4	514	break;
e04582b7	515	}
1da177e4	516
41c594ab RB	517	#ifdef CONFIG_MIPS_MT_SMTC
	518	/* Read-modify-write of Status must be atomic */
	519	local_irq_save(irqflags);
	520	mtflags = dmt();
	521	#endif /* CONFIG_MIPS_MT_SMTC */
101b3531 RB	522	if (cpu_has_mipsmt) {
	523	unsigned int vpflags = dvpe();
	524	flags = read_c0_status();
597ce172	525	__enable_fpu(FPU_AS_IS);
101b3531 RB	526	__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
	527	write_c0_status(flags);
	528	evpe(vpflags);
	529	} else {
	530	flags = read_c0_status();
597ce172	531	__enable_fpu(FPU_AS_IS);
101b3531 RB	532	__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
	533	write_c0_status(flags);
	534	}
41c594ab RB	535	#ifdef CONFIG_MIPS_MT_SMTC
	536	emt(mtflags);
	537	local_irq_restore(irqflags);
	538	#endif /* CONFIG_MIPS_MT_SMTC */
101b3531	539	preempt_enable();
1da177e4 LT	540	break;
1da177e4 LT	541	}
c134a5ec RB	542	case DSP_BASE ... DSP_BASE + 5: {
	543	dspreg_t *dregs;
	544
e50c0a8f RB	545	if (!cpu_has_dsp) {
	546	tmp = 0;
	547	ret = -EIO;
481bed45	548	goto out;
e50c0a8f	549	}
6c355852 RB	550	dregs = __get_dsp_regs(child);
6c355852 RB	551	tmp = (unsigned long) (dregs[addr - DSP_BASE]);
e50c0a8f	552	break;
c134a5ec	553	}
e50c0a8f RB	554	case DSP_CONTROL:
	555	if (!cpu_has_dsp) {
	556	tmp = 0;
	557	ret = -EIO;
481bed45	558	goto out;
e50c0a8f RB	559	}
	560	tmp = child->thread.dsp.dspcontrol;
	561	break;
1da177e4 LT	562	default:
	563	tmp = 0;
	564	ret = -EIO;
481bed45	565	goto out;
1da177e4	566	}
fb671139	567	ret = put_user(tmp, datalp);
1da177e4 LT	568	break;
	569	}
	570
	571	/* when I and D space are separate, this will have to be fixed. */
	572	case PTRACE_POKETEXT: /* write the word at location addr. */
	573	case PTRACE_POKEDATA:
f284ce72	574	ret = generic_ptrace_pokedata(child, addr, data);
1da177e4 LT	575	break;
	576
	577	case PTRACE_POKEUSR: {
	578	struct pt_regs *regs;
	579	ret = 0;
40bc9c67	580	regs = task_pt_regs(child);
1da177e4 LT	581
	582	switch (addr) {
	583	case 0 ... 31:
	584	regs->regs[addr] = data;
	585	break;
	586	case FPR_BASE ... FPR_BASE + 31: {
bbd426f5	587	union fpureg *fregs = get_fpu_regs(child);
1da177e4 LT	588
	589	if (!tsk_used_math(child)) {
	590	/* FP not yet used */
eae89076 AN	591	memset(&child->thread.fpu, ~0,
	592	sizeof(child->thread.fpu));
	593	child->thread.fpu.fcr31 = 0;
1da177e4	594	}
875d43e7	595	#ifdef CONFIG_32BIT
597ce172 PB	596	if (test_thread_flag(TIF_32BIT_FPREGS)) {
	597	/*
	598	* The odd registers are actually the high
	599	* order bits of the values stored in the even
	600	* registers - unless we're using r2k_switch.S.
	601	*/
bbd426f5 PB	602	set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
bbd426f5 PB	603	addr & 1, data);
597ce172	604	break;
1da177e4 LT	605	}
1da177e4 LT	606	#endif
bbd426f5	607	set_fpr64(&fregs[addr - FPR_BASE], 0, data);
1da177e4 LT	608	break;
	609	}
	610	case PC:
	611	regs->cp0_epc = data;
	612	break;
	613	case MMHI:
	614	regs->hi = data;
	615	break;
	616	case MMLO:
	617	regs->lo = data;
	618	break;
9693a853 FBH	619	#ifdef CONFIG_CPU_HAS_SMARTMIPS
	620	case ACX:
	621	regs->acx = data;
	622	break;
	623	#endif
1da177e4	624	case FPC_CSR:
eae89076	625	child->thread.fpu.fcr31 = data;
1da177e4	626	break;
c134a5ec RB	627	case DSP_BASE ... DSP_BASE + 5: {
	628	dspreg_t *dregs;
	629
e50c0a8f RB	630	if (!cpu_has_dsp) {
	631	ret = -EIO;
	632	break;
	633	}
	634
c134a5ec	635	dregs = __get_dsp_regs(child);
e50c0a8f RB	636	dregs[addr - DSP_BASE] = data;
e50c0a8f RB	637	break;
c134a5ec	638	}
e50c0a8f RB	639	case DSP_CONTROL:
	640	if (!cpu_has_dsp) {
	641	ret = -EIO;
	642	break;
	643	}
	644	child->thread.dsp.dspcontrol = data;
	645	break;
1da177e4 LT	646	default:
	647	/* The rest are not allowed. */
	648	ret = -EIO;
	649	break;
	650	}
	651	break;
	652	}
	653
ea3d710f	654	case PTRACE_GETREGS:
fb671139	655	ret = ptrace_getregs(child, datavp);
ea3d710f DJ	656	break;
	657
	658	case PTRACE_SETREGS:
fb671139	659	ret = ptrace_setregs(child, datavp);
ea3d710f DJ	660	break;
	661
	662	case PTRACE_GETFPREGS:
fb671139	663	ret = ptrace_getfpregs(child, datavp);
ea3d710f DJ	664	break;
	665
	666	case PTRACE_SETFPREGS:
fb671139	667	ret = ptrace_setfpregs(child, datavp);
ea3d710f DJ	668	break;
ea3d710f DJ	669
3c37026d	670	case PTRACE_GET_THREAD_AREA:
fb671139	671	ret = put_user(task_thread_info(child)->tp_value, datalp);
3c37026d RB	672	break;
3c37026d RB	673
0926bf95	674	case PTRACE_GET_WATCH_REGS:
fb671139	675	ret = ptrace_get_watch_regs(child, addrp);
0926bf95 DD	676	break;
	677
	678	case PTRACE_SET_WATCH_REGS:
fb671139	679	ret = ptrace_set_watch_regs(child, addrp);
0926bf95 DD	680	break;
0926bf95 DD	681
1da177e4 LT	682	default:
	683	ret = ptrace_request(child, request, addr, data);
	684	break;
	685	}
481bed45	686	out:
1da177e4 LT	687	return ret;
	688	}
	689
	690	/*
	691	* Notification of system call entry/exit
	692	* - triggered by current->work.syscall_trace
	693	*/
4c21b8fd	694	asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
1da177e4	695	{
0dfa95aa	696	long ret = 0;
c3fc5cd5 RB	697	user_exit();
c3fc5cd5 RB	698
1225eb82 MC	699	if (secure_computing(syscall) == -1)
1225eb82 MC	700	return -1;
1da177e4	701
0dfa95aa RB	702	if (test_thread_flag(TIF_SYSCALL_TRACE) &&
	703	tracehook_report_syscall_entry(regs))
	704	ret = -1;
293c5bd1	705
1d7bf993 RB	706	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
	707	trace_sys_enter(regs, regs->regs[2]);
	708
6e345746	709	audit_syscall_entry(syscall_get_arch(current, regs),
1225eb82	710	syscall,
b05d8447 EP	711	regs->regs[4], regs->regs[5],
b05d8447 EP	712	regs->regs[6], regs->regs[7]);
1225eb82	713	return syscall;
1da177e4	714	}
8b659a39 RB	715
	716	/*
	717	* Notification of system call entry/exit
	718	* - triggered by current->work.syscall_trace
	719	*/
	720	asmlinkage void syscall_trace_leave(struct pt_regs *regs)
	721	{
c3fc5cd5 RB	722	/*
	723	* We may come here right after calling schedule_user()
	724	* or do_notify_resume(), in which case we can be in RCU
	725	* user mode.
	726	*/
	727	user_exit();
	728
d7e7528b	729	audit_syscall_exit(regs);
8b659a39	730
1d7bf993 RB	731	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
	732	trace_sys_exit(regs, regs->regs[2]);
	733
bc3d22c1 RB	734	if (test_thread_flag(TIF_SYSCALL_TRACE))
bc3d22c1 RB	735	tracehook_report_syscall_exit(regs, 0);
c3fc5cd5 RB	736
c3fc5cd5 RB	737	user_enter();
8b659a39	738	}