[deliverable/linux.git] / arch / mips / kernel / ptrace.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 Ross Biro
 * Copyright (C) Linus Torvalds
 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
 * Copyright (C) 1996 David S. Miller
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 1999 MIPS Technologies, Inc.
 * Copyright (C) 2000 Ulf Carlsson
 *
 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
 * binaries.
 */
#include <linux/compiler.h>
#include <linux/context_tracking.h>
#include <linux/elf.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
#include <linux/regset.h>
#include <linux/smp.h>
#include <linux/user.h>
#include <linux/security.h>
#include <linux/tracehook.h>
#include <linux/audit.h>
#include <linux/seccomp.h>
#include <linux/ftrace.h>

#include <asm/byteorder.h>
#include <asm/cpu.h>
#include <asm/dsp.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/syscall.h>
#include <asm/uaccess.h>
#include <asm/bootinfo.h>
#include <asm/reg.h>

#define CREATE_TRACE_POINTS
#include <trace/events/syscalls.h>

/*
 * Called by kernel/ptrace.c when detaching..
 *
 * Make sure single step bits etc are not set.
 */
void ptrace_disable(struct task_struct *child)
{
	/* Don't load the watchpoint registers for the ex-child. */
	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
}

/*
 * Read a general register set.	 We always use the 64-bit format, even
 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
 * Registers are sign extended to fill the available space.
 */
int ptrace_getregs(struct task_struct *child, __s64 __user *data)
{
	struct pt_regs *regs;
	int i;

	if (!access_ok(VERIFY_WRITE, data, 38 * 8))
		return -EIO;

	regs = task_pt_regs(child);

	for (i = 0; i < 32; i++)
		__put_user((long)regs->regs[i], data + i);
	__put_user((long)regs->lo, data + EF_LO - EF_R0);
	__put_user((long)regs->hi, data + EF_HI - EF_R0);
	__put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
	__put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
	__put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
	__put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);

	return 0;
}

/*
 * Write a general register set.  As for PTRACE_GETREGS, we always use
 * the 64-bit format.  On a 32-bit kernel only the lower order half
 * (according to endianness) will be used.
 */
int ptrace_setregs(struct task_struct *child, __s64 __user *data)
{
	struct pt_regs *regs;
	int i;

	if (!access_ok(VERIFY_READ, data, 38 * 8))
		return -EIO;

	regs = task_pt_regs(child);

	for (i = 0; i < 32; i++)
		__get_user(regs->regs[i], data + i);
	__get_user(regs->lo, data + EF_LO - EF_R0);
	__get_user(regs->hi, data + EF_HI - EF_R0);
	__get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);

	/* badvaddr, status, and cause may not be written.  */

	return 0;
}

int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
{
	int i;

	if (!access_ok(VERIFY_WRITE, data, 33 * 8))
		return -EIO;

	if (tsk_used_math(child)) {
		union fpureg *fregs = get_fpu_regs(child);
		for (i = 0; i < 32; i++)
			__put_user(get_fpr64(&fregs[i], 0),
				   i + (__u64 __user *)data);
	} else {
		for (i = 0; i < 32; i++)
			__put_user((__u64) -1, i + (__u64 __user *) data);
	}

	__put_user(child->thread.fpu.fcr31, data + 64);
	__put_user(current_cpu_data.fpu_id, data + 65);

	return 0;
}

int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
{
	union fpureg *fregs;
	u64 fpr_val;
	int i;

	if (!access_ok(VERIFY_READ, data, 33 * 8))
		return -EIO;

	fregs = get_fpu_regs(child);

	for (i = 0; i < 32; i++) {
		__get_user(fpr_val, i + (__u64 __user *)data);
		set_fpr64(&fregs[i], 0, fpr_val);
	}

	__get_user(child->thread.fpu.fcr31, data + 64);

	/* FIR may not be written.  */

	return 0;
}

int ptrace_get_watch_regs(struct task_struct *child,
			  struct pt_watch_regs __user *addr)
{
	enum pt_watch_style style;
	int i;

	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
		return -EIO;
	if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
		return -EIO;

#ifdef CONFIG_32BIT
	style = pt_watch_style_mips32;
#define WATCH_STYLE mips32
#else
	style = pt_watch_style_mips64;
#define WATCH_STYLE mips64
#endif

	__put_user(style, &addr->style);
	__put_user(current_cpu_data.watch_reg_use_cnt,
		   &addr->WATCH_STYLE.num_valid);
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		__put_user(child->thread.watch.mips3264.watchlo[i],
			   &addr->WATCH_STYLE.watchlo[i]);
		__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
			   &addr->WATCH_STYLE.watchhi[i]);
		__put_user(current_cpu_data.watch_reg_masks[i],
			   &addr->WATCH_STYLE.watch_masks[i]);
	}
	for (; i < 8; i++) {
		__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
		__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
		__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
	}

	return 0;
}

int ptrace_set_watch_regs(struct task_struct *child,
			  struct pt_watch_regs __user *addr)
{
	int i;
	int watch_active = 0;
	unsigned long lt[NUM_WATCH_REGS];
	u16 ht[NUM_WATCH_REGS];

	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
		return -EIO;
	if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
		return -EIO;
	/* Check the values. */
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
#ifdef CONFIG_32BIT
		if (lt[i] & __UA_LIMIT)
			return -EINVAL;
#else
		if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
			if (lt[i] & 0xffffffff80000000UL)
				return -EINVAL;
		} else {
			if (lt[i] & __UA_LIMIT)
				return -EINVAL;
		}
#endif
		__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
		if (ht[i] & ~0xff8)
			return -EINVAL;
	}
	/* Install them. */
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		if (lt[i] & 7)
			watch_active = 1;
		child->thread.watch.mips3264.watchlo[i] = lt[i];
		/* Set the G bit. */
		child->thread.watch.mips3264.watchhi[i] = ht[i];
	}

	if (watch_active)
		set_tsk_thread_flag(child, TIF_LOAD_WATCH);
	else
		clear_tsk_thread_flag(child, TIF_LOAD_WATCH);

	return 0;
}

/* regset get/set implementations */

static int gpr_get(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   void *kbuf, void __user *ubuf)
{
	struct pt_regs *regs = task_pt_regs(target);

	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
				   regs, 0, sizeof(*regs));
}

static int gpr_set(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   const void *kbuf, const void __user *ubuf)
{
	struct pt_regs newregs;
	int ret;

	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
				 &newregs,
				 0, sizeof(newregs));
	if (ret)
		return ret;

	*task_pt_regs(target) = newregs;

	return 0;
}

static int fpr_get(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   void *kbuf, void __user *ubuf)
{
	unsigned i;
	int err;
	u64 fpr_val;

	/* XXX fcr31  */

	if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
		return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
					   &target->thread.fpu,
					   0, sizeof(elf_fpregset_t));

	for (i = 0; i < NUM_FPU_REGS; i++) {
		fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0);
		err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
					  &fpr_val, i * sizeof(elf_fpreg_t),
					  (i + 1) * sizeof(elf_fpreg_t));
		if (err)
			return err;
	}

	return 0;
}

static int fpr_set(struct task_struct *target,
		   const struct user_regset *regset,
		   unsigned int pos, unsigned int count,
		   const void *kbuf, const void __user *ubuf)
{
	unsigned i;
	int err;
	u64 fpr_val;

	/* XXX fcr31  */

	if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
		return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
					  &target->thread.fpu,
					  0, sizeof(elf_fpregset_t));

	for (i = 0; i < NUM_FPU_REGS; i++) {
		err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
					 &fpr_val, i * sizeof(elf_fpreg_t),
					 (i + 1) * sizeof(elf_fpreg_t));
		if (err)
			return err;
		set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);
	}

	return 0;
}

enum mips_regset {
	REGSET_GPR,
	REGSET_FPR,
};

static const struct user_regset mips_regsets[] = {
	[REGSET_GPR] = {
		.core_note_type	= NT_PRSTATUS,
		.n		= ELF_NGREG,
		.size		= sizeof(unsigned int),
		.align		= sizeof(unsigned int),
		.get		= gpr_get,
		.set		= gpr_set,
	},
	[REGSET_FPR] = {
		.core_note_type	= NT_PRFPREG,
		.n		= ELF_NFPREG,
		.size		= sizeof(elf_fpreg_t),
		.align		= sizeof(elf_fpreg_t),
		.get		= fpr_get,
		.set		= fpr_set,
	},
};

static const struct user_regset_view user_mips_view = {
	.name		= "mips",
	.e_machine	= ELF_ARCH,
	.ei_osabi	= ELF_OSABI,
	.regsets	= mips_regsets,
	.n		= ARRAY_SIZE(mips_regsets),
};

static const struct user_regset mips64_regsets[] = {
	[REGSET_GPR] = {
		.core_note_type	= NT_PRSTATUS,
		.n		= ELF_NGREG,
		.size		= sizeof(unsigned long),
		.align		= sizeof(unsigned long),
		.get		= gpr_get,
		.set		= gpr_set,
	},
	[REGSET_FPR] = {
		.core_note_type	= NT_PRFPREG,
		.n		= ELF_NFPREG,
		.size		= sizeof(elf_fpreg_t),
		.align		= sizeof(elf_fpreg_t),
		.get		= fpr_get,
		.set		= fpr_set,
	},
};

static const struct user_regset_view user_mips64_view = {
	.name		= "mips",
	.e_machine	= ELF_ARCH,
	.ei_osabi	= ELF_OSABI,
	.regsets	= mips64_regsets,
	.n		= ARRAY_SIZE(mips_regsets),
};

const struct user_regset_view *task_user_regset_view(struct task_struct *task)
{
#ifdef CONFIG_32BIT
	return &user_mips_view;
#endif

#ifdef CONFIG_MIPS32_O32
		if (test_thread_flag(TIF_32BIT_REGS))
			return &user_mips_view;
#endif

	return &user_mips64_view;
}

long arch_ptrace(struct task_struct *child, long request,
		 unsigned long addr, unsigned long data)
{
	int ret;
	void __user *addrp = (void __user *) addr;
	void __user *datavp = (void __user *) data;
	unsigned long __user *datalp = (void __user *) data;

	switch (request) {
	/* when I and D space are separate, these will need to be fixed. */
	case PTRACE_PEEKTEXT: /* read word at location addr. */
	case PTRACE_PEEKDATA:
		ret = generic_ptrace_peekdata(child, addr, data);
		break;

	/* Read the word at location addr in the USER area. */
	case PTRACE_PEEKUSR: {
		struct pt_regs *regs;
		union fpureg *fregs;
		unsigned long tmp = 0;

		regs = task_pt_regs(child);
		ret = 0;  /* Default return value. */

		switch (addr) {
		case 0 ... 31:
			tmp = regs->regs[addr];
			break;
		case FPR_BASE ... FPR_BASE + 31:
			if (!tsk_used_math(child)) {
				/* FP not yet used */
				tmp = -1;
				break;
			}
			fregs = get_fpu_regs(child);

#ifdef CONFIG_32BIT
			if (test_thread_flag(TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
						addr & 1);
				break;
			}
#endif
			tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
			break;
		case PC:
			tmp = regs->cp0_epc;
			break;
		case CAUSE:
			tmp = regs->cp0_cause;
			break;
		case BADVADDR:
			tmp = regs->cp0_badvaddr;
			break;
		case MMHI:
			tmp = regs->hi;
			break;
		case MMLO:
			tmp = regs->lo;
			break;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
		case ACX:
			tmp = regs->acx;
			break;
#endif
		case FPC_CSR:
			tmp = child->thread.fpu.fcr31;
			break;
		case FPC_EIR:
			/* implementation / version register */
			tmp = current_cpu_data.fpu_id;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			dregs = __get_dsp_regs(child);
			tmp = (unsigned long) (dregs[addr - DSP_BASE]);
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			tmp = child->thread.dsp.dspcontrol;
			break;
		default:
			tmp = 0;
			ret = -EIO;
			goto out;
		}
		ret = put_user(tmp, datalp);
		break;
	}

	/* when I and D space are separate, this will have to be fixed. */
	case PTRACE_POKETEXT: /* write the word at location addr. */
	case PTRACE_POKEDATA:
		ret = generic_ptrace_pokedata(child, addr, data);
		break;

	case PTRACE_POKEUSR: {
		struct pt_regs *regs;
		ret = 0;
		regs = task_pt_regs(child);

		switch (addr) {
		case 0 ... 31:
			regs->regs[addr] = data;
			break;
		case FPR_BASE ... FPR_BASE + 31: {
			union fpureg *fregs = get_fpu_regs(child);

			if (!tsk_used_math(child)) {
				/* FP not yet used  */
				memset(&child->thread.fpu, ~0,
				       sizeof(child->thread.fpu));
				child->thread.fpu.fcr31 = 0;
			}
#ifdef CONFIG_32BIT
			if (test_thread_flag(TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
					  addr & 1, data);
				break;
			}
#endif
			set_fpr64(&fregs[addr - FPR_BASE], 0, data);
			break;
		}
		case PC:
			regs->cp0_epc = data;
			break;
		case MMHI:
			regs->hi = data;
			break;
		case MMLO:
			regs->lo = data;
			break;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
		case ACX:
			regs->acx = data;
			break;
#endif
		case FPC_CSR:
			child->thread.fpu.fcr31 = data;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}

			dregs = __get_dsp_regs(child);
			dregs[addr - DSP_BASE] = data;
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}
			child->thread.dsp.dspcontrol = data;
			break;
		default:
			/* The rest are not allowed. */
			ret = -EIO;
			break;
		}
		break;
		}

	case PTRACE_GETREGS:
		ret = ptrace_getregs(child, datavp);
		break;

	case PTRACE_SETREGS:
		ret = ptrace_setregs(child, datavp);
		break;

	case PTRACE_GETFPREGS:
		ret = ptrace_getfpregs(child, datavp);
		break;

	case PTRACE_SETFPREGS:
		ret = ptrace_setfpregs(child, datavp);
		break;

	case PTRACE_GET_THREAD_AREA:
		ret = put_user(task_thread_info(child)->tp_value, datalp);
		break;

	case PTRACE_GET_WATCH_REGS:
		ret = ptrace_get_watch_regs(child, addrp);
		break;

	case PTRACE_SET_WATCH_REGS:
		ret = ptrace_set_watch_regs(child, addrp);
		break;

	default:
		ret = ptrace_request(child, request, addr, data);
		break;
	}
 out:
	return ret;
}

/*
 * Notification of system call entry/exit
 * - triggered by current->work.syscall_trace
 */
asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
{
	long ret = 0;
	user_exit();

	if (secure_computing(syscall) == -1)
		return -1;

	if (test_thread_flag(TIF_SYSCALL_TRACE) &&
	    tracehook_report_syscall_entry(regs))
		ret = -1;

	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
		trace_sys_enter(regs, regs->regs[2]);

	audit_syscall_entry(syscall_get_arch(),
			    syscall,
			    regs->regs[4], regs->regs[5],
			    regs->regs[6], regs->regs[7]);
	return syscall;
}

/*
 * Notification of system call entry/exit
 * - triggered by current->work.syscall_trace
 */
asmlinkage void syscall_trace_leave(struct pt_regs *regs)
{
        /*
	 * We may come here right after calling schedule_user()
	 * or do_notify_resume(), in which case we can be in RCU
	 * user mode.
	 */
	user_exit();

	audit_syscall_exit(regs);

	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
		trace_sys_exit(regs, regs->regs[2]);

	if (test_thread_flag(TIF_SYSCALL_TRACE))
		tracehook_report_syscall_exit(regs, 0);

	user_enter();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1992 Ross Biro
	7	* Copyright (C) Linus Torvalds
	8	* Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
	9	* Copyright (C) 1996 David S. Miller
	10	* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	11	* Copyright (C) 1999 MIPS Technologies, Inc.
	12	* Copyright (C) 2000 Ulf Carlsson
	13	*
	14	* At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
	15	* binaries.
	16	*/
1da177e4	17	#include <linux/compiler.h>
c3fc5cd5	18	#include <linux/context_tracking.h>
7aeb753b	19	#include <linux/elf.h>
1da177e4 LT	20	#include <linux/kernel.h>
	21	#include <linux/sched.h>
	22	#include <linux/mm.h>
	23	#include <linux/errno.h>
	24	#include <linux/ptrace.h>
7aeb753b	25	#include <linux/regset.h>
1da177e4	26	#include <linux/smp.h>
1da177e4 LT	27	#include <linux/user.h>
1da177e4 LT	28	#include <linux/security.h>
bc3d22c1	29	#include <linux/tracehook.h>
293c5bd1 RB	30	#include <linux/audit.h>
293c5bd1 RB	31	#include <linux/seccomp.h>
1d7bf993	32	#include <linux/ftrace.h>
1da177e4	33
f8280c8d	34	#include <asm/byteorder.h>
1da177e4	35	#include <asm/cpu.h>
e50c0a8f	36	#include <asm/dsp.h>
1da177e4 LT	37	#include <asm/fpu.h>
1da177e4 LT	38	#include <asm/mipsregs.h>
101b3531	39	#include <asm/mipsmtregs.h>
1da177e4 LT	40	#include <asm/pgtable.h>
1da177e4 LT	41	#include <asm/page.h>
bec9b2b2	42	#include <asm/syscall.h>
1da177e4 LT	43	#include <asm/uaccess.h>
1da177e4 LT	44	#include <asm/bootinfo.h>
ea3d710f	45	#include <asm/reg.h>
1da177e4	46
1d7bf993 RB	47	#define CREATE_TRACE_POINTS
	48	#include <trace/events/syscalls.h>
	49
1da177e4 LT	50	/*
	51	* Called by kernel/ptrace.c when detaching..
	52	*
	53	* Make sure single step bits etc are not set.
	54	*/
	55	void ptrace_disable(struct task_struct *child)
	56	{
0926bf95 DD	57	/* Don't load the watchpoint registers for the ex-child. */
0926bf95 DD	58	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
1da177e4 LT	59	}
1da177e4 LT	60
ea3d710f	61	/*
70342287	62	* Read a general register set. We always use the 64-bit format, even
ea3d710f DJ	63	* for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
	64	* Registers are sign extended to fill the available space.
	65	*/
49a89efb	66	int ptrace_getregs(struct task_struct child, __s64 __user data)
ea3d710f DJ	67	{
	68	struct pt_regs *regs;
	69	int i;
	70
	71	if (!access_ok(VERIFY_WRITE, data, 38 * 8))
	72	return -EIO;
	73
40bc9c67	74	regs = task_pt_regs(child);
ea3d710f DJ	75
ea3d710f DJ	76	for (i = 0; i < 32; i++)
62b14c24 AN	77	__put_user((long)regs->regs[i], data + i);
	78	__put_user((long)regs->lo, data + EF_LO - EF_R0);
	79	__put_user((long)regs->hi, data + EF_HI - EF_R0);
	80	__put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
	81	__put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
	82	__put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
	83	__put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
ea3d710f DJ	84
	85	return 0;
	86	}
	87
	88	/*
	89	* Write a general register set. As for PTRACE_GETREGS, we always use
	90	* the 64-bit format. On a 32-bit kernel only the lower order half
	91	* (according to endianness) will be used.
	92	*/
49a89efb	93	int ptrace_setregs(struct task_struct child, __s64 __user data)
ea3d710f DJ	94	{
	95	struct pt_regs *regs;
	96	int i;
	97
	98	if (!access_ok(VERIFY_READ, data, 38 * 8))
	99	return -EIO;
	100
40bc9c67	101	regs = task_pt_regs(child);
ea3d710f DJ	102
ea3d710f DJ	103	for (i = 0; i < 32; i++)
49a89efb RB	104	__get_user(regs->regs[i], data + i);
	105	__get_user(regs->lo, data + EF_LO - EF_R0);
	106	__get_user(regs->hi, data + EF_HI - EF_R0);
	107	__get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
ea3d710f DJ	108
	109	/* badvaddr, status, and cause may not be written. */
	110
	111	return 0;
	112	}
	113
49a89efb	114	int ptrace_getfpregs(struct task_struct child, __u32 __user data)
ea3d710f DJ	115	{
	116	int i;
	117
	118	if (!access_ok(VERIFY_WRITE, data, 33 * 8))
	119	return -EIO;
	120
	121	if (tsk_used_math(child)) {
bbd426f5	122	union fpureg *fregs = get_fpu_regs(child);
ea3d710f	123	for (i = 0; i < 32; i++)
bbd426f5 PB	124	__put_user(get_fpr64(&fregs[i], 0),
bbd426f5 PB	125	i + (__u64 __user *)data);
ea3d710f DJ	126	} else {
ea3d710f DJ	127	for (i = 0; i < 32; i++)
49a89efb	128	__put_user((__u64) -1, i + (__u64 __user *) data);
ea3d710f DJ	129	}
ea3d710f DJ	130
49a89efb	131	__put_user(child->thread.fpu.fcr31, data + 64);
dab75dd9	132	__put_user(current_cpu_data.fpu_id, data + 65);
ea3d710f DJ	133
	134	return 0;
	135	}
	136
49a89efb	137	int ptrace_setfpregs(struct task_struct child, __u32 __user data)
ea3d710f	138	{
bbd426f5 PB	139	union fpureg *fregs;
bbd426f5 PB	140	u64 fpr_val;
ea3d710f DJ	141	int i;
	142
	143	if (!access_ok(VERIFY_READ, data, 33 * 8))
	144	return -EIO;
	145
	146	fregs = get_fpu_regs(child);
	147
bbd426f5 PB	148	for (i = 0; i < 32; i++) {
	149	__get_user(fpr_val, i + (__u64 __user *)data);
	150	set_fpr64(&fregs[i], 0, fpr_val);
	151	}
ea3d710f	152
49a89efb	153	__get_user(child->thread.fpu.fcr31, data + 64);
ea3d710f DJ	154
	155	/* FIR may not be written. */
	156
	157	return 0;
	158	}
	159
0926bf95 DD	160	int ptrace_get_watch_regs(struct task_struct *child,
	161	struct pt_watch_regs __user *addr)
	162	{
	163	enum pt_watch_style style;
	164	int i;
	165
	166	if (!cpu_has_watch \|\| current_cpu_data.watch_reg_use_cnt == 0)
	167	return -EIO;
	168	if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
	169	return -EIO;
	170
	171	#ifdef CONFIG_32BIT
	172	style = pt_watch_style_mips32;
	173	#define WATCH_STYLE mips32
	174	#else
	175	style = pt_watch_style_mips64;
	176	#define WATCH_STYLE mips64
	177	#endif
	178
	179	__put_user(style, &addr->style);
	180	__put_user(current_cpu_data.watch_reg_use_cnt,
	181	&addr->WATCH_STYLE.num_valid);
	182	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
	183	__put_user(child->thread.watch.mips3264.watchlo[i],
	184	&addr->WATCH_STYLE.watchlo[i]);
	185	__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
	186	&addr->WATCH_STYLE.watchhi[i]);
	187	__put_user(current_cpu_data.watch_reg_masks[i],
	188	&addr->WATCH_STYLE.watch_masks[i]);
	189	}
	190	for (; i < 8; i++) {
	191	__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
	192	__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
	193	__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
	194	}
	195
	196	return 0;
	197	}
	198
	199	int ptrace_set_watch_regs(struct task_struct *child,
	200	struct pt_watch_regs __user *addr)
	201	{
	202	int i;
	203	int watch_active = 0;
	204	unsigned long lt[NUM_WATCH_REGS];
	205	u16 ht[NUM_WATCH_REGS];
	206
	207	if (!cpu_has_watch \|\| current_cpu_data.watch_reg_use_cnt == 0)
	208	return -EIO;
	209	if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
	210	return -EIO;
	211	/* Check the values. */
	212	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
	213	__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
	214	#ifdef CONFIG_32BIT
	215	if (lt[i] & __UA_LIMIT)
	216	return -EINVAL;
	217	#else
	218	if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
	219	if (lt[i] & 0xffffffff80000000UL)
	220	return -EINVAL;
	221	} else {
	222	if (lt[i] & __UA_LIMIT)
	223	return -EINVAL;
224	}
225	#endif
226	__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
227	if (ht[i] & ~0xff8)
228	return -EINVAL;
229	}
230	/* Install them. */
231	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
232	if (lt[i] & 7)
233	watch_active = 1;
234	child->thread.watch.mips3264.watchlo[i] = lt[i];
235	/* Set the G bit. */
236	child->thread.watch.mips3264.watchhi[i] = ht[i];
237	}
238
239	if (watch_active)
240	set_tsk_thread_flag(child, TIF_LOAD_WATCH);
241	else
242	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
243
244	return 0;
245	}
246
7aeb753b RB	247	/* regset get/set implementations */
	248
	249	static int gpr_get(struct task_struct *target,
	250	const struct user_regset *regset,
	251	unsigned int pos, unsigned int count,
	252	void kbuf, void __user ubuf)
	253	{
	254	struct pt_regs *regs = task_pt_regs(target);
	255
	256	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
	257	regs, 0, sizeof(*regs));
	258	}
	259
	260	static int gpr_set(struct task_struct *target,
	261	const struct user_regset *regset,
	262	unsigned int pos, unsigned int count,
	263	const void kbuf, const void __user ubuf)
	264	{
	265	struct pt_regs newregs;
	266	int ret;
	267
	268	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
	269	&newregs,
	270	0, sizeof(newregs));
	271	if (ret)
	272	return ret;
	273
	274	*task_pt_regs(target) = newregs;
	275
	276	return 0;
	277	}
	278
	279	static int fpr_get(struct task_struct *target,
	280	const struct user_regset *regset,
	281	unsigned int pos, unsigned int count,
	282	void kbuf, void __user ubuf)
	283	{
72b22bba PB	284	unsigned i;
	285	int err;
	286	u64 fpr_val;
	287
7aeb753b	288	/* XXX fcr31 */
72b22bba PB	289
	290	if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
	291	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
	292	&target->thread.fpu,
	293	0, sizeof(elf_fpregset_t));
	294
	295	for (i = 0; i < NUM_FPU_REGS; i++) {
	296	fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0);
	297	err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
	298	&fpr_val, i * sizeof(elf_fpreg_t),
	299	(i + 1) * sizeof(elf_fpreg_t));
	300	if (err)
	301	return err;
	302	}
	303
	304	return 0;
7aeb753b RB	305	}
	306
	307	static int fpr_set(struct task_struct *target,
	308	const struct user_regset *regset,
	309	unsigned int pos, unsigned int count,
	310	const void kbuf, const void __user ubuf)
	311	{
72b22bba PB	312	unsigned i;
	313	int err;
	314	u64 fpr_val;
	315
7aeb753b	316	/* XXX fcr31 */
72b22bba PB	317
	318	if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
	319	return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
	320	&target->thread.fpu,
	321	0, sizeof(elf_fpregset_t));
	322
	323	for (i = 0; i < NUM_FPU_REGS; i++) {
	324	err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
	325	&fpr_val, i * sizeof(elf_fpreg_t),
	326	(i + 1) * sizeof(elf_fpreg_t));
	327	if (err)
	328	return err;
	329	set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);
	330	}
	331
	332	return 0;
7aeb753b RB	333	}
	334
	335	enum mips_regset {
	336	REGSET_GPR,
	337	REGSET_FPR,
	338	};
	339
	340	static const struct user_regset mips_regsets[] = {
	341	[REGSET_GPR] = {
	342	.core_note_type = NT_PRSTATUS,
	343	.n = ELF_NGREG,
	344	.size = sizeof(unsigned int),
	345	.align = sizeof(unsigned int),
	346	.get = gpr_get,
	347	.set = gpr_set,
	348	},
	349	[REGSET_FPR] = {
	350	.core_note_type = NT_PRFPREG,
	351	.n = ELF_NFPREG,
	352	.size = sizeof(elf_fpreg_t),
	353	.align = sizeof(elf_fpreg_t),
	354	.get = fpr_get,
	355	.set = fpr_set,
	356	},
	357	};
	358
	359	static const struct user_regset_view user_mips_view = {
	360	.name = "mips",
	361	.e_machine = ELF_ARCH,
	362	.ei_osabi = ELF_OSABI,
	363	.regsets = mips_regsets,
	364	.n = ARRAY_SIZE(mips_regsets),
	365	};
	366
	367	static const struct user_regset mips64_regsets[] = {
	368	[REGSET_GPR] = {
	369	.core_note_type = NT_PRSTATUS,
	370	.n = ELF_NGREG,
	371	.size = sizeof(unsigned long),
	372	.align = sizeof(unsigned long),
	373	.get = gpr_get,
	374	.set = gpr_set,
	375	},
	376	[REGSET_FPR] = {
	377	.core_note_type = NT_PRFPREG,
	378	.n = ELF_NFPREG,
	379	.size = sizeof(elf_fpreg_t),
	380	.align = sizeof(elf_fpreg_t),
	381	.get = fpr_get,
	382	.set = fpr_set,
	383	},
	384	};
	385
	386	static const struct user_regset_view user_mips64_view = {
	387	.name = "mips",
	388	.e_machine = ELF_ARCH,
	389	.ei_osabi = ELF_OSABI,
	390	.regsets = mips64_regsets,
	391	.n = ARRAY_SIZE(mips_regsets),
	392	};
	393
	394	const struct user_regset_view task_user_regset_view(struct task_struct task)
	395	{
	396	#ifdef CONFIG_32BIT
397	return &user_mips_view;
398	#endif
399
400	#ifdef CONFIG_MIPS32_O32
401	if (test_thread_flag(TIF_32BIT_REGS))
402	return &user_mips_view;
403	#endif
404
405	return &user_mips64_view;
406	}
407
9b05a69e NK	408	long arch_ptrace(struct task_struct *child, long request,
9b05a69e NK	409	unsigned long addr, unsigned long data)
1da177e4	410	{
1da177e4	411	int ret;
fb671139 NK	412	void __user addrp = (void __user ) addr;
	413	void __user datavp = (void __user ) data;
	414	unsigned long __user datalp = (void __user ) data;
1da177e4	415
1da177e4 LT	416	switch (request) {
	417	/* when I and D space are separate, these will need to be fixed. */
	418	case PTRACE_PEEKTEXT: /* read word at location addr. */
76647323 AD	419	case PTRACE_PEEKDATA:
76647323 AD	420	ret = generic_ptrace_peekdata(child, addr, data);
1da177e4	421	break;
1da177e4 LT	422
	423	/* Read the word at location addr in the USER area. */
	424	case PTRACE_PEEKUSR: {
	425	struct pt_regs *regs;
bbd426f5	426	union fpureg *fregs;
1da177e4 LT	427	unsigned long tmp = 0;
1da177e4 LT	428
40bc9c67	429	regs = task_pt_regs(child);
1da177e4 LT	430	ret = 0; /* Default return value. */
	431
	432	switch (addr) {
	433	case 0 ... 31:
	434	tmp = regs->regs[addr];
	435	break;
	436	case FPR_BASE ... FPR_BASE + 31:
597ce172 PB	437	if (!tsk_used_math(child)) {
	438	/* FP not yet used */
	439	tmp = -1;
	440	break;
	441	}
	442	fregs = get_fpu_regs(child);
1da177e4	443
875d43e7	444	#ifdef CONFIG_32BIT
597ce172	445	if (test_thread_flag(TIF_32BIT_FPREGS)) {
1da177e4 LT	446	/*
	447	* The odd registers are actually the high
	448	* order bits of the values stored in the even
	449	* registers - unless we're using r2k_switch.S.
	450	*/
bbd426f5 PB	451	tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
bbd426f5 PB	452	addr & 1);
597ce172	453	break;
1da177e4	454	}
597ce172	455	#endif
bbd426f5	456	tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
1da177e4 LT	457	break;
	458	case PC:
	459	tmp = regs->cp0_epc;
	460	break;
	461	case CAUSE:
	462	tmp = regs->cp0_cause;
	463	break;
	464	case BADVADDR:
	465	tmp = regs->cp0_badvaddr;
	466	break;
	467	case MMHI:
	468	tmp = regs->hi;
	469	break;
	470	case MMLO:
	471	tmp = regs->lo;
	472	break;
9693a853 FBH	473	#ifdef CONFIG_CPU_HAS_SMARTMIPS
	474	case ACX:
	475	tmp = regs->acx;
	476	break;
	477	#endif
1da177e4	478	case FPC_CSR:
eae89076	479	tmp = child->thread.fpu.fcr31;
1da177e4	480	break;
3351047f PB	481	case FPC_EIR:
	482	/* implementation / version register */
	483	tmp = current_cpu_data.fpu_id;
1da177e4	484	break;
c134a5ec RB	485	case DSP_BASE ... DSP_BASE + 5: {
	486	dspreg_t *dregs;
	487
e50c0a8f RB	488	if (!cpu_has_dsp) {
	489	tmp = 0;
	490	ret = -EIO;
481bed45	491	goto out;
e50c0a8f	492	}
6c355852 RB	493	dregs = __get_dsp_regs(child);
6c355852 RB	494	tmp = (unsigned long) (dregs[addr - DSP_BASE]);
e50c0a8f	495	break;
c134a5ec	496	}
e50c0a8f RB	497	case DSP_CONTROL:
	498	if (!cpu_has_dsp) {
	499	tmp = 0;
	500	ret = -EIO;
481bed45	501	goto out;
e50c0a8f RB	502	}
	503	tmp = child->thread.dsp.dspcontrol;
	504	break;
1da177e4 LT	505	default:
	506	tmp = 0;
	507	ret = -EIO;
481bed45	508	goto out;
1da177e4	509	}
fb671139	510	ret = put_user(tmp, datalp);
1da177e4 LT	511	break;
	512	}
	513
	514	/* when I and D space are separate, this will have to be fixed. */
	515	case PTRACE_POKETEXT: /* write the word at location addr. */
	516	case PTRACE_POKEDATA:
f284ce72	517	ret = generic_ptrace_pokedata(child, addr, data);
1da177e4 LT	518	break;
	519
	520	case PTRACE_POKEUSR: {
	521	struct pt_regs *regs;
	522	ret = 0;
40bc9c67	523	regs = task_pt_regs(child);
1da177e4 LT	524
	525	switch (addr) {
	526	case 0 ... 31:
	527	regs->regs[addr] = data;
	528	break;
	529	case FPR_BASE ... FPR_BASE + 31: {
bbd426f5	530	union fpureg *fregs = get_fpu_regs(child);
1da177e4 LT	531
	532	if (!tsk_used_math(child)) {
	533	/* FP not yet used */
eae89076 AN	534	memset(&child->thread.fpu, ~0,
	535	sizeof(child->thread.fpu));
	536	child->thread.fpu.fcr31 = 0;
1da177e4	537	}
875d43e7	538	#ifdef CONFIG_32BIT
597ce172 PB	539	if (test_thread_flag(TIF_32BIT_FPREGS)) {
	540	/*
	541	* The odd registers are actually the high
	542	* order bits of the values stored in the even
	543	* registers - unless we're using r2k_switch.S.
	544	*/
bbd426f5 PB	545	set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
bbd426f5 PB	546	addr & 1, data);
597ce172	547	break;
1da177e4 LT	548	}
1da177e4 LT	549	#endif
bbd426f5	550	set_fpr64(&fregs[addr - FPR_BASE], 0, data);
1da177e4 LT	551	break;
	552	}
	553	case PC:
	554	regs->cp0_epc = data;
	555	break;
	556	case MMHI:
	557	regs->hi = data;
	558	break;
	559	case MMLO:
	560	regs->lo = data;
	561	break;
9693a853 FBH	562	#ifdef CONFIG_CPU_HAS_SMARTMIPS
	563	case ACX:
	564	regs->acx = data;
	565	break;
	566	#endif
1da177e4	567	case FPC_CSR:
eae89076	568	child->thread.fpu.fcr31 = data;
1da177e4	569	break;
c134a5ec RB	570	case DSP_BASE ... DSP_BASE + 5: {
	571	dspreg_t *dregs;
	572
e50c0a8f RB	573	if (!cpu_has_dsp) {
	574	ret = -EIO;
	575	break;
	576	}
	577
c134a5ec	578	dregs = __get_dsp_regs(child);
e50c0a8f RB	579	dregs[addr - DSP_BASE] = data;
e50c0a8f RB	580	break;
c134a5ec	581	}
e50c0a8f RB	582	case DSP_CONTROL:
	583	if (!cpu_has_dsp) {
	584	ret = -EIO;
	585	break;
	586	}
	587	child->thread.dsp.dspcontrol = data;
	588	break;
1da177e4 LT	589	default:
	590	/* The rest are not allowed. */
	591	ret = -EIO;
	592	break;
	593	}
	594	break;
	595	}
	596
ea3d710f	597	case PTRACE_GETREGS:
fb671139	598	ret = ptrace_getregs(child, datavp);
ea3d710f DJ	599	break;
	600
	601	case PTRACE_SETREGS:
fb671139	602	ret = ptrace_setregs(child, datavp);
ea3d710f DJ	603	break;
	604
	605	case PTRACE_GETFPREGS:
fb671139	606	ret = ptrace_getfpregs(child, datavp);
ea3d710f DJ	607	break;
	608
	609	case PTRACE_SETFPREGS:
fb671139	610	ret = ptrace_setfpregs(child, datavp);
ea3d710f DJ	611	break;
ea3d710f DJ	612
3c37026d	613	case PTRACE_GET_THREAD_AREA:
fb671139	614	ret = put_user(task_thread_info(child)->tp_value, datalp);
3c37026d RB	615	break;
3c37026d RB	616
0926bf95	617	case PTRACE_GET_WATCH_REGS:
fb671139	618	ret = ptrace_get_watch_regs(child, addrp);
0926bf95 DD	619	break;
	620
	621	case PTRACE_SET_WATCH_REGS:
fb671139	622	ret = ptrace_set_watch_regs(child, addrp);
0926bf95 DD	623	break;
0926bf95 DD	624
1da177e4 LT	625	default:
	626	ret = ptrace_request(child, request, addr, data);
	627	break;
	628	}
481bed45	629	out:
1da177e4 LT	630	return ret;
	631	}
	632
	633	/*
	634	* Notification of system call entry/exit
	635	* - triggered by current->work.syscall_trace
	636	*/
4c21b8fd	637	asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
1da177e4	638	{
0dfa95aa	639	long ret = 0;
c3fc5cd5 RB	640	user_exit();
c3fc5cd5 RB	641
1225eb82 MC	642	if (secure_computing(syscall) == -1)
1225eb82 MC	643	return -1;
1da177e4	644
0dfa95aa RB	645	if (test_thread_flag(TIF_SYSCALL_TRACE) &&
	646	tracehook_report_syscall_entry(regs))
	647	ret = -1;
293c5bd1	648
1d7bf993 RB	649	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
	650	trace_sys_enter(regs, regs->regs[2]);
	651
5e937a9a	652	audit_syscall_entry(syscall_get_arch(),
1225eb82	653	syscall,
b05d8447 EP	654	regs->regs[4], regs->regs[5],
b05d8447 EP	655	regs->regs[6], regs->regs[7]);
1225eb82	656	return syscall;
1da177e4	657	}
8b659a39 RB	658
	659	/*
	660	* Notification of system call entry/exit
	661	* - triggered by current->work.syscall_trace
	662	*/
	663	asmlinkage void syscall_trace_leave(struct pt_regs *regs)
	664	{
c3fc5cd5 RB	665	/*
	666	* We may come here right after calling schedule_user()
	667	* or do_notify_resume(), in which case we can be in RCU
	668	* user mode.
	669	*/
	670	user_exit();
	671
d7e7528b	672	audit_syscall_exit(regs);
8b659a39	673
1d7bf993 RB	674	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
	675	trace_sys_exit(regs, regs->regs[2]);
	676
bc3d22c1 RB	677	if (test_thread_flag(TIF_SYSCALL_TRACE))
bc3d22c1 RB	678	tracehook_report_syscall_exit(regs, 0);
c3fc5cd5 RB	679
c3fc5cd5 RB	680	user_enter();
8b659a39	681	}