[deliverable/linux.git] / arch / mips / kernel / r4k_switch.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
 * Copyright (C) 1999 Silicon Graphics, Inc.
 * Copyright (C) 2000 MIPS Technologies, Inc.
 *    written by Carsten Langgaard, carstenl@mips.com
 */
#include <asm/asm.h>
#include <asm/cachectl.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
#include <asm/asm-offsets.h>
#include <asm/pgtable-bits.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/thread_info.h>

#include <asm/asmmacro.h>

/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
#undef fp

/*
 * Offset to the current process status flags, the first 32 bytes of the
 * stack are not used.
 */
#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)

#ifndef USE_ALTERNATE_RESUME_IMPL
/*
 * task_struct *resume(task_struct *prev, task_struct *next,
 *		       struct thread_info *next_ti)
 */
	.align	5
	LEAF(resume)
	mfc0	t1, CP0_STATUS
	LONG_S	t1, THREAD_STATUS(a0)
	cpu_save_nonscratch a0
	LONG_S	ra, THREAD_REG31(a0)

#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
	PTR_LA	t8, __stack_chk_guard
	LONG_L	t9, TASK_STACK_CANARY(a1)
	LONG_S	t9, 0(t8)
#endif

	/*
	 * The order of restoring the registers takes care of the race
	 * updating $28, $29 and kernelsp without disabling ints.
	 */
	move	$28, a2
	cpu_restore_nonscratch a1

	PTR_ADDU	t0, $28, _THREAD_SIZE - 32
	set_saved_sp	t0, t1, t2
	mfc0	t1, CP0_STATUS		/* Do we really need this? */
	li	a3, 0xff01
	and	t1, a3
	LONG_L	a2, THREAD_STATUS(a1)
	nor	a3, $0, a3
	and	a2, a3
	or	a2, t1
	mtc0	a2, CP0_STATUS
	move	v0, a0
	jr	ra
	END(resume)

#endif /* USE_ALTERNATE_RESUME_IMPL */

/*
 * Save a thread's fp context.
 */
LEAF(_save_fp)
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
		defined(CONFIG_CPU_MIPS32_R6)
	mfc0	t0, CP0_STATUS
#endif
	fpu_save_double a0 t0 t1		# clobbers t1
	jr	ra
	END(_save_fp)

/*
 * Restore a thread's fp context.
 */
LEAF(_restore_fp)
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
		defined(CONFIG_CPU_MIPS32_R6)
	mfc0	t0, CP0_STATUS
#endif
	fpu_restore_double a0 t0 t1		# clobbers t1
	jr	ra
	END(_restore_fp)

#ifdef CONFIG_CPU_HAS_MSA

/*
 * Save a thread's MSA vector context.
 */
LEAF(_save_msa)
	msa_save_all	a0
	jr	ra
	END(_save_msa)

/*
 * Restore a thread's MSA vector context.
 */
LEAF(_restore_msa)
	msa_restore_all	a0
	jr	ra
	END(_restore_msa)

LEAF(_init_msa_upper)
	msa_init_all_upper
	jr	ra
	END(_init_msa_upper)

#endif

/*
 * Load the FPU with signalling NANS.  This bit pattern we're using has
 * the property that no matter whether considered as single or as double
 * precision represents signaling NANS.
 *
 * The value to initialize fcr31 to comes in $a0.
 */

	.set push
	SET_HARDFLOAT

LEAF(_init_fpu)
	mfc0	t0, CP0_STATUS
	li	t1, ST0_CU1
	or	t0, t1
	mtc0	t0, CP0_STATUS
	enable_fpu_hazard

	ctc1	a0, fcr31

	li	t1, -1				# SNaN

#ifdef CONFIG_64BIT
	sll	t0, t0, 5
	bgez	t0, 1f				# 16 / 32 register mode?

	dmtc1	t1, $f1
	dmtc1	t1, $f3
	dmtc1	t1, $f5
	dmtc1	t1, $f7
	dmtc1	t1, $f9
	dmtc1	t1, $f11
	dmtc1	t1, $f13
	dmtc1	t1, $f15
	dmtc1	t1, $f17
	dmtc1	t1, $f19
	dmtc1	t1, $f21
	dmtc1	t1, $f23
	dmtc1	t1, $f25
	dmtc1	t1, $f27
	dmtc1	t1, $f29
	dmtc1	t1, $f31
1:
#endif

#ifdef CONFIG_CPU_MIPS32
	mtc1	t1, $f0
	mtc1	t1, $f1
	mtc1	t1, $f2
	mtc1	t1, $f3
	mtc1	t1, $f4
	mtc1	t1, $f5
	mtc1	t1, $f6
	mtc1	t1, $f7
	mtc1	t1, $f8
	mtc1	t1, $f9
	mtc1	t1, $f10
	mtc1	t1, $f11
	mtc1	t1, $f12
	mtc1	t1, $f13
	mtc1	t1, $f14
	mtc1	t1, $f15
	mtc1	t1, $f16
	mtc1	t1, $f17
	mtc1	t1, $f18
	mtc1	t1, $f19
	mtc1	t1, $f20
	mtc1	t1, $f21
	mtc1	t1, $f22
	mtc1	t1, $f23
	mtc1	t1, $f24
	mtc1	t1, $f25
	mtc1	t1, $f26
	mtc1	t1, $f27
	mtc1	t1, $f28
	mtc1	t1, $f29
	mtc1	t1, $f30
	mtc1	t1, $f31

#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6)
	.set    push
	.set    MIPS_ISA_LEVEL_RAW
	.set	fp=64
	sll     t0, t0, 5			# is Status.FR set?
	bgez    t0, 1f				# no: skip setting upper 32b

	mthc1   t1, $f0
	mthc1   t1, $f1
	mthc1   t1, $f2
	mthc1   t1, $f3
	mthc1   t1, $f4
	mthc1   t1, $f5
	mthc1   t1, $f6
	mthc1   t1, $f7
	mthc1   t1, $f8
	mthc1   t1, $f9
	mthc1   t1, $f10
	mthc1   t1, $f11
	mthc1   t1, $f12
	mthc1   t1, $f13
	mthc1   t1, $f14
	mthc1   t1, $f15
	mthc1   t1, $f16
	mthc1   t1, $f17
	mthc1   t1, $f18
	mthc1   t1, $f19
	mthc1   t1, $f20
	mthc1   t1, $f21
	mthc1   t1, $f22
	mthc1   t1, $f23
	mthc1   t1, $f24
	mthc1   t1, $f25
	mthc1   t1, $f26
	mthc1   t1, $f27
	mthc1   t1, $f28
	mthc1   t1, $f29
	mthc1   t1, $f30
	mthc1   t1, $f31
1:	.set    pop
#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */
#else
	.set	MIPS_ISA_ARCH_LEVEL_RAW
	dmtc1	t1, $f0
	dmtc1	t1, $f2
	dmtc1	t1, $f4
	dmtc1	t1, $f6
	dmtc1	t1, $f8
	dmtc1	t1, $f10
	dmtc1	t1, $f12
	dmtc1	t1, $f14
	dmtc1	t1, $f16
	dmtc1	t1, $f18
	dmtc1	t1, $f20
	dmtc1	t1, $f22
	dmtc1	t1, $f24
	dmtc1	t1, $f26
	dmtc1	t1, $f28
	dmtc1	t1, $f30
#endif
	jr	ra
	END(_init_fpu)

	.set pop	/* SET_HARDFLOAT */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
79add627	7	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
1da177e4 LT	8	* Copyright (C) 1994, 1995, 1996, by Andreas Busse
	9	* Copyright (C) 1999 Silicon Graphics, Inc.
	10	* Copyright (C) 2000 MIPS Technologies, Inc.
	11	* written by Carsten Langgaard, carstenl@mips.com
	12	*/
1da177e4 LT	13	#include <asm/asm.h>
	14	#include <asm/cachectl.h>
	15	#include <asm/fpregdef.h>
	16	#include <asm/mipsregs.h>
048eb582	17	#include <asm/asm-offsets.h>
1da177e4 LT	18	#include <asm/pgtable-bits.h>
	19	#include <asm/regdef.h>
	20	#include <asm/stackframe.h>
	21	#include <asm/thread_info.h>
	22
	23	#include <asm/asmmacro.h>
	24
842dfc11 ML	25	/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
	26	#undef fp
	27
1da177e4 LT	28	/*
	29	* Offset to the current process status flags, the first 32 bytes of the
	30	* stack are not used.
	31	*/
	32	#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
	33
a36d8225	34	#ifndef USE_ALTERNATE_RESUME_IMPL
1da177e4 LT	35	/*
1da177e4 LT	36	* task_struct resume(task_struct prev, task_struct *next,
1a3d5957	37	* struct thread_info *next_ti)
1da177e4 LT	38	*/
	39	.align 5
	40	LEAF(resume)
5323180d AN	41	mfc0 t1, CP0_STATUS
5323180d AN	42	LONG_S t1, THREAD_STATUS(a0)
1da177e4 LT	43	cpu_save_nonscratch a0
	44	LONG_S ra, THREAD_REG31(a0)
	45
1400eb65	46	#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
8b3c569a	47	PTR_LA t8, __stack_chk_guard
1400eb65 GF	48	LONG_L t9, TASK_STACK_CANARY(a1)
	49	LONG_S t9, 0(t8)
	50	#endif
	51
1da177e4 LT	52	/*
	53	* The order of restoring the registers takes care of the race
	54	* updating $28, $29 and kernelsp without disabling ints.
	55	*/
	56	move $28, a2
	57	cpu_restore_nonscratch a1
	58
3bd39664	59	PTR_ADDU t0, $28, _THREAD_SIZE - 32
1da177e4	60	set_saved_sp t0, t1, t2
1da177e4 LT	61	mfc0 t1, CP0_STATUS /* Do we really need this? */
	62	li a3, 0xff01
	63	and t1, a3
	64	LONG_L a2, THREAD_STATUS(a1)
	65	nor a3, $0, a3
	66	and a2, a3
	67	or a2, t1
	68	mtc0 a2, CP0_STATUS
	69	move v0, a0
	70	jr ra
	71	END(resume)
	72
a36d8225 DD	73	#endif /* USE_ALTERNATE_RESUME_IMPL */
a36d8225 DD	74
1da177e4 LT	75	/*
	76	* Save a thread's fp context.
	77	*/
	78	LEAF(_save_fp)
207083b1 LY	79	#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
207083b1 LY	80	defined(CONFIG_CPU_MIPS32_R6)
c138e12f	81	mfc0 t0, CP0_STATUS
1da177e4	82	#endif
c138e12f	83	fpu_save_double a0 t0 t1 # clobbers t1
1da177e4 LT	84	jr ra
	85	END(_save_fp)
	86
	87	/*
	88	* Restore a thread's fp context.
	89	*/
	90	LEAF(_restore_fp)
207083b1 LY	91	#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
207083b1 LY	92	defined(CONFIG_CPU_MIPS32_R6)
c138e12f AN	93	mfc0 t0, CP0_STATUS
	94	#endif
	95	fpu_restore_double a0 t0 t1 # clobbers t1
1da177e4 LT	96	jr ra
	97	END(_restore_fp)
	98
1db1af84 PB	99	#ifdef CONFIG_CPU_HAS_MSA
	100
	101	/*
	102	* Save a thread's MSA vector context.
	103	*/
	104	LEAF(_save_msa)
	105	msa_save_all a0
	106	jr ra
	107	END(_save_msa)
	108
	109	/*
	110	* Restore a thread's MSA vector context.
	111	*/
	112	LEAF(_restore_msa)
	113	msa_restore_all a0
	114	jr ra
	115	END(_restore_msa)
	116
c9017757 PB	117	LEAF(_init_msa_upper)
	118	msa_init_all_upper
	119	jr ra
	120	END(_init_msa_upper)
	121
1db1af84 PB	122	#endif
1db1af84 PB	123
1da177e4 LT	124	/*
	125	* Load the FPU with signalling NANS. This bit pattern we're using has
	126	* the property that no matter whether considered as single or as double
	127	* precision represents signaling NANS.
	128	*
9b26616c	129	* The value to initialize fcr31 to comes in $a0.
1da177e4 LT	130	*/
1da177e4 LT	131
842dfc11 ML	132	.set push
	133	SET_HARDFLOAT
	134
1da177e4 LT	135	LEAF(_init_fpu)
	136	mfc0 t0, CP0_STATUS
	137	li t1, ST0_CU1
	138	or t0, t1
	139	mtc0 t0, CP0_STATUS
f9509c84	140	enable_fpu_hazard
1da177e4	141
9b26616c	142	ctc1 a0, fcr31
1da177e4 LT	143
	144	li t1, -1 # SNaN
	145
875d43e7	146	#ifdef CONFIG_64BIT
1da177e4 LT	147	sll t0, t0, 5
	148	bgez t0, 1f # 16 / 32 register mode?
	149
	150	dmtc1 t1, $f1
	151	dmtc1 t1, $f3
	152	dmtc1 t1, $f5
	153	dmtc1 t1, $f7
	154	dmtc1 t1, $f9
	155	dmtc1 t1, $f11
	156	dmtc1 t1, $f13
	157	dmtc1 t1, $f15
	158	dmtc1 t1, $f17
	159	dmtc1 t1, $f19
	160	dmtc1 t1, $f21
	161	dmtc1 t1, $f23
	162	dmtc1 t1, $f25
	163	dmtc1 t1, $f27
	164	dmtc1 t1, $f29
	165	dmtc1 t1, $f31
	166	1:
	167	#endif
42a3b4f2	168
1da177e4 LT	169	#ifdef CONFIG_CPU_MIPS32
	170	mtc1 t1, $f0
	171	mtc1 t1, $f1
	172	mtc1 t1, $f2
	173	mtc1 t1, $f3
	174	mtc1 t1, $f4
	175	mtc1 t1, $f5
	176	mtc1 t1, $f6
	177	mtc1 t1, $f7
	178	mtc1 t1, $f8
	179	mtc1 t1, $f9
	180	mtc1 t1, $f10
	181	mtc1 t1, $f11
	182	mtc1 t1, $f12
	183	mtc1 t1, $f13
	184	mtc1 t1, $f14
	185	mtc1 t1, $f15
	186	mtc1 t1, $f16
	187	mtc1 t1, $f17
	188	mtc1 t1, $f18
	189	mtc1 t1, $f19
	190	mtc1 t1, $f20
	191	mtc1 t1, $f21
	192	mtc1 t1, $f22
	193	mtc1 t1, $f23
	194	mtc1 t1, $f24
	195	mtc1 t1, $f25
	196	mtc1 t1, $f26
	197	mtc1 t1, $f27
	198	mtc1 t1, $f28
	199	mtc1 t1, $f29
	200	mtc1 t1, $f30
	201	mtc1 t1, $f31
597ce172	202
207083b1	203	#if defined(CONFIG_CPU_MIPS32_R2) \|\| defined(CONFIG_CPU_MIPS32_R6)
597ce172	204	.set push
207083b1	205	.set MIPS_ISA_LEVEL_RAW
842dfc11	206	.set fp=64
597ce172 PB	207	sll t0, t0, 5 # is Status.FR set?
	208	bgez t0, 1f # no: skip setting upper 32b
	209
	210	mthc1 t1, $f0
	211	mthc1 t1, $f1
	212	mthc1 t1, $f2
	213	mthc1 t1, $f3
	214	mthc1 t1, $f4
	215	mthc1 t1, $f5
	216	mthc1 t1, $f6
	217	mthc1 t1, $f7
	218	mthc1 t1, $f8
	219	mthc1 t1, $f9
	220	mthc1 t1, $f10
	221	mthc1 t1, $f11
	222	mthc1 t1, $f12
	223	mthc1 t1, $f13
	224	mthc1 t1, $f14
	225	mthc1 t1, $f15
	226	mthc1 t1, $f16
	227	mthc1 t1, $f17
	228	mthc1 t1, $f18
	229	mthc1 t1, $f19
	230	mthc1 t1, $f20
	231	mthc1 t1, $f21
	232	mthc1 t1, $f22
	233	mthc1 t1, $f23
	234	mthc1 t1, $f24
	235	mthc1 t1, $f25
	236	mthc1 t1, $f26
	237	mthc1 t1, $f27
	238	mthc1 t1, $f28
	239	mthc1 t1, $f29
	240	mthc1 t1, $f30
	241	mthc1 t1, $f31
	242	1: .set pop
207083b1	243	#endif /* CONFIG_CPU_MIPS32_R2 \|\| CONFIG_CPU_MIPS32_R6 */
1da177e4	244	#else
207083b1	245	.set MIPS_ISA_ARCH_LEVEL_RAW
1da177e4 LT	246	dmtc1 t1, $f0
	247	dmtc1 t1, $f2
	248	dmtc1 t1, $f4
	249	dmtc1 t1, $f6
	250	dmtc1 t1, $f8
	251	dmtc1 t1, $f10
	252	dmtc1 t1, $f12
	253	dmtc1 t1, $f14
	254	dmtc1 t1, $f16
	255	dmtc1 t1, $f18
	256	dmtc1 t1, $f20
	257	dmtc1 t1, $f22
	258	dmtc1 t1, $f24
	259	dmtc1 t1, $f26
	260	dmtc1 t1, $f28
	261	dmtc1 t1, $f30
	262	#endif
	263	jr ra
	264	END(_init_fpu)
842dfc11 ML	265
842dfc11 ML	266	.set pop /* SET_HARDFLOAT */