[deliverable/linux.git] / arch / mips / kernel / smp-cmp.c

/*
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Copyright (C) 2007 MIPS Technologies, Inc.
 *    Chris Dearman (chris@mips.com)
 */

#undef DEBUG

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/compiler.h>
#include <linux/irqchip/mips-gic.h>

#include <linux/atomic.h>
#include <asm/cacheflush.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/mips_mt.h>
#include <asm/amon.h>

static void cmp_init_secondary(void)
{
	struct cpuinfo_mips *c __maybe_unused = &current_cpu_data;

	/* Assume GIC is present */
	change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
				 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);

	/* Enable per-cpu interrupts: platform specific */

#ifdef CONFIG_MIPS_MT_SMP
	if (cpu_has_mipsmt)
		c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
			TCBIND_CURVPE;
#endif
}

static void cmp_smp_finish(void)
{
	pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);

	/* CDFIXME: remove this? */
	write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));

#ifdef CONFIG_MIPS_MT_FPAFF
	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	if (cpu_has_fpu)
		cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */

	local_irq_enable();
}

/*
 * Setup the PC, SP, and GP of a secondary processor and start it running
 * smp_bootstrap is the place to resume from
 * __KSTK_TOS(idle) is apparently the stack pointer
 * (unsigned long)idle->thread_info the gp
 */
static void cmp_boot_secondary(int cpu, struct task_struct *idle)
{
	struct thread_info *gp = task_thread_info(idle);
	unsigned long sp = __KSTK_TOS(idle);
	unsigned long pc = (unsigned long)&smp_bootstrap;
	unsigned long a0 = 0;

	pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(),
		__func__, cpu);

#if 0
	/* Needed? */
	flush_icache_range((unsigned long)gp,
			   (unsigned long)(gp + sizeof(struct thread_info)));
#endif

	amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
}

/*
 * Common setup before any secondaries are started
 */
void __init cmp_smp_setup(void)
{
	int i;
	int ncpu = 0;

	pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);

#ifdef CONFIG_MIPS_MT_FPAFF
	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	if (cpu_has_fpu)
		cpumask_set_cpu(0, &mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */

	for (i = 1; i < NR_CPUS; i++) {
		if (amon_cpu_avail(i)) {
			set_cpu_possible(i, true);
			__cpu_number_map[i]	= ++ncpu;
			__cpu_logical_map[ncpu] = i;
		}
	}

	if (cpu_has_mipsmt) {
		unsigned int nvpe = 1;
#ifdef CONFIG_MIPS_MT_SMP
		unsigned int mvpconf0 = read_c0_mvpconf0();

		nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
#endif
		smp_num_siblings = nvpe;
	}
	pr_info("Detected %i available secondary CPU(s)\n", ncpu);
}

void __init cmp_prepare_cpus(unsigned int max_cpus)
{
	pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
		 smp_processor_id(), __func__, max_cpus);

#ifdef CONFIG_MIPS_MT
	/*
	 * FIXME: some of these options are per-system, some per-core and
	 * some per-cpu
	 */
	mips_mt_set_cpuoptions();
#endif

}

struct plat_smp_ops cmp_smp_ops = {
	.send_ipi_single	= mips_smp_send_ipi_single,
	.send_ipi_mask		= mips_smp_send_ipi_mask,
	.init_secondary		= cmp_init_secondary,
	.smp_finish		= cmp_smp_finish,
	.boot_secondary		= cmp_boot_secondary,
	.smp_setup		= cmp_smp_setup,
	.prepare_cpus		= cmp_prepare_cpus,
};
Commit	Line	Data
39b8d525 RB	1	/*
	2	* This program is free software; you can distribute it and/or modify it
	3	* under the terms of the GNU General Public License (Version 2) as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope it will be useful, but WITHOUT
	7	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	8	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	9	* for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License along
	12	* with this program; if not, write to the Free Software Foundation, Inc.,
	13	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	14	*
	15	* Copyright (C) 2007 MIPS Technologies, Inc.
	16	* Chris Dearman (chris@mips.com)
	17	*/
	18
	19	#undef DEBUG
	20
	21	#include <linux/kernel.h>
	22	#include <linux/sched.h>
631330f5	23	#include <linux/smp.h>
39b8d525 RB	24	#include <linux/cpumask.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/compiler.h>
4060bbe9	27	#include <linux/irqchip/mips-gic.h>
39b8d525	28
60063497	29	#include <linux/atomic.h>
39b8d525 RB	30	#include <asm/cacheflush.h>
	31	#include <asm/cpu.h>
	32	#include <asm/processor.h>
39b8d525 RB	33	#include <asm/hardirq.h>
	34	#include <asm/mmu_context.h>
	35	#include <asm/smp.h>
	36	#include <asm/time.h>
	37	#include <asm/mipsregs.h>
	38	#include <asm/mipsmtregs.h>
	39	#include <asm/mips_mt.h>
0365070f	40	#include <asm/amon.h>
39b8d525	41
39b8d525 RB	42	static void cmp_init_secondary(void)
39b8d525 RB	43	{
f0cff5c8	44	struct cpuinfo_mips *c __maybe_unused = &current_cpu_data;
39b8d525 RB	45
39b8d525 RB	46	/* Assume GIC is present */
c3f134fb JH	47	change_c0_status(ST0_IM, STATUSF_IP2 \| STATUSF_IP3 \| STATUSF_IP4 \|
c3f134fb JH	48	STATUSF_IP5 \| STATUSF_IP6 \| STATUSF_IP7);
39b8d525 RB	49
	50	/* Enable per-cpu interrupts: platform specific */
	51
b633648c	52	#ifdef CONFIG_MIPS_MT_SMP
670bac3a LY	53	if (cpu_has_mipsmt)
	54	c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
	55	TCBIND_CURVPE;
39b8d525	56	#endif
39b8d525 RB	57	}
	58
	59	static void cmp_smp_finish(void)
	60	{
	61	pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
	62
	63	/* CDFIXME: remove this? */
	64	write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
	65
	66	#ifdef CONFIG_MIPS_MT_FPAFF
	67	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	68	if (cpu_has_fpu)
8dd92891	69	cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
39b8d525 RB	70	#endif /* CONFIG_MIPS_MT_FPAFF */
	71
	72	local_irq_enable();
	73	}
	74
39b8d525 RB	75	/*
	76	* Setup the PC, SP, and GP of a secondary processor and start it running
	77	* smp_bootstrap is the place to resume from
	78	* __KSTK_TOS(idle) is apparently the stack pointer
	79	* (unsigned long)idle->thread_info the gp
	80	*/
	81	static void cmp_boot_secondary(int cpu, struct task_struct *idle)
	82	{
	83	struct thread_info *gp = task_thread_info(idle);
	84	unsigned long sp = __KSTK_TOS(idle);
	85	unsigned long pc = (unsigned long)&smp_bootstrap;
	86	unsigned long a0 = 0;
	87
	88	pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(),
	89	__func__, cpu);
	90
	91	#if 0
	92	/* Needed? */
	93	flush_icache_range((unsigned long)gp,
	94	(unsigned long)(gp + sizeof(struct thread_info)));
	95	#endif
	96
0365070f	97	amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
39b8d525 RB	98	}
	99
	100	/*
	101	* Common setup before any secondaries are started
	102	*/
	103	void __init cmp_smp_setup(void)
	104	{
	105	int i;
	106	int ncpu = 0;
	107
	108	pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
	109
	110	#ifdef CONFIG_MIPS_MT_FPAFF
	111	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	112	if (cpu_has_fpu)
8dd92891	113	cpumask_set_cpu(0, &mt_fpu_cpumask);
39b8d525 RB	114	#endif /* CONFIG_MIPS_MT_FPAFF */
	115
	116	for (i = 1; i < NR_CPUS; i++) {
	117	if (amon_cpu_avail(i)) {
4037ac6e	118	set_cpu_possible(i, true);
39b8d525	119	__cpu_number_map[i] = ++ncpu;
70342287	120	__cpu_logical_map[ncpu] = i;
39b8d525 RB	121	}
	122	}
	123
	124	if (cpu_has_mipsmt) {
670bac3a LY	125	unsigned int nvpe = 1;
	126	#ifdef CONFIG_MIPS_MT_SMP
	127	unsigned int mvpconf0 = read_c0_mvpconf0();
	128
	129	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
670bac3a	130	#endif
39b8d525 RB	131	smp_num_siblings = nvpe;
	132	}
	133	pr_info("Detected %i available secondary CPU(s)\n", ncpu);
	134	}
	135
	136	void __init cmp_prepare_cpus(unsigned int max_cpus)
	137	{
	138	pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
	139	smp_processor_id(), __func__, max_cpus);
	140
40149889	141	#ifdef CONFIG_MIPS_MT
39b8d525 RB	142	/*
	143	* FIXME: some of these options are per-system, some per-core and
	144	* some per-cpu
	145	*/
	146	mips_mt_set_cpuoptions();
40149889 MC	147	#endif
40149889 MC	148
39b8d525 RB	149	}
	150
	151	struct plat_smp_ops cmp_smp_ops = {
bb11cff3 QY	152	.send_ipi_single = mips_smp_send_ipi_single,
bb11cff3 QY	153	.send_ipi_mask = mips_smp_send_ipi_mask,
39b8d525 RB	154	.init_secondary = cmp_init_secondary,
39b8d525 RB	155	.smp_finish = cmp_smp_finish,
39b8d525 RB	156	.boot_secondary = cmp_boot_secondary,
	157	.smp_setup = cmp_smp_setup,
	158	.prepare_cpus = cmp_prepare_cpus,
	159	};