[deliverable/linux.git] / arch / mips / kernel / smp-mt.c

/*
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
 *    Elizabeth Clarke (beth@mips.com)
 *    Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/compiler.h>
#include <linux/smp.h>

#include <asm/atomic.h>
#include <asm/cacheflush.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/mips_mt.h>

#define MIPS_CPU_IPI_RESCHED_IRQ 0
#define MIPS_CPU_IPI_CALL_IRQ 1

static int cpu_ipi_resched_irq, cpu_ipi_call_irq;

#if 0
static void dump_mtregisters(int vpe, int tc)
{
	printk("vpe %d tc %d\n", vpe, tc);

	settc(tc);

	printk("  c0 status  0x%lx\n", read_vpe_c0_status());
	printk("  vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol());
	printk("  vpeconf0    0x%lx\n", read_vpe_c0_vpeconf0());
	printk("  tcstatus 0x%lx\n", read_tc_c0_tcstatus());
	printk("  tcrestart 0x%lx\n", read_tc_c0_tcrestart());
	printk("  tcbind 0x%lx\n", read_tc_c0_tcbind());
	printk("  tchalt 0x%lx\n", read_tc_c0_tchalt());
}
#endif

void __init sanitize_tlb_entries(void)
{
	int i, tlbsiz;
	unsigned long mvpconf0, ncpu;

	if (!cpu_has_mipsmt)
		return;

	/* Enable VPC */
	set_c0_mvpcontrol(MVPCONTROL_VPC);

	back_to_back_c0_hazard();

	/* Disable TLB sharing */
	clear_c0_mvpcontrol(MVPCONTROL_STLB);

	mvpconf0 = read_c0_mvpconf0();

	printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0,
		   (mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT,
			   (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT);

	tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT;
	ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;

	printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu);

	if (tlbsiz > 0) {
		/* share them out across the vpe's */
		tlbsiz /= ncpu;

		printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz);

		for (i = 0; i < ncpu; i++) {
			settc(i);

			if (i == 0)
				write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25));
			else
				write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) |
						   (tlbsiz << 25));
		}
	}

	clear_c0_mvpcontrol(MVPCONTROL_VPC);
}

static void ipi_resched_dispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
}

static void ipi_call_dispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
}

static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{
	return IRQ_HANDLED;
}

static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
{
	smp_call_function_interrupt();

	return IRQ_HANDLED;
}

static struct irqaction irq_resched = {
	.handler	= ipi_resched_interrupt,
	.flags		= IRQF_DISABLED|IRQF_PERCPU,
	.name		= "IPI_resched"
};

static struct irqaction irq_call = {
	.handler	= ipi_call_interrupt,
	.flags		= IRQF_DISABLED|IRQF_PERCPU,
	.name		= "IPI_call"
};

static void __init smp_copy_vpe_config(void)
{
	write_vpe_c0_status(
		(read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);

	/* set config to be the same as vpe0, particularly kseg0 coherency alg */
	write_vpe_c0_config( read_c0_config());

	/* make sure there are no software interrupts pending */
	write_vpe_c0_cause(0);

	/* Propagate Config7 */
	write_vpe_c0_config7(read_c0_config7());

	write_vpe_c0_count(read_c0_count());
}

static unsigned int __init smp_vpe_init(unsigned int tc, unsigned int mvpconf0,
	unsigned int ncpu)
{
	if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
		return ncpu;

	/* Deactivate all but VPE 0 */
	if (tc != 0) {
		unsigned long tmp = read_vpe_c0_vpeconf0();

		tmp &= ~VPECONF0_VPA;

		/* master VPE */
		tmp |= VPECONF0_MVP;
		write_vpe_c0_vpeconf0(tmp);

		/* Record this as available CPU */
		cpu_set(tc, phys_cpu_present_map);
		__cpu_number_map[tc]	= ++ncpu;
		__cpu_logical_map[ncpu]	= tc;
	}

	/* Disable multi-threading with TC's */
	write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);

	if (tc != 0)
		smp_copy_vpe_config();

	return ncpu;
}

static void __init smp_tc_init(unsigned int tc, unsigned int mvpconf0)
{
	unsigned long tmp;

	if (!tc)
		return;

	/* bind a TC to each VPE, May as well put all excess TC's
	   on the last VPE */
	if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
		write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
	else {
		write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);

		/* and set XTC */
		write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
	}

	tmp = read_tc_c0_tcstatus();

	/* mark not allocated and not dynamically allocatable */
	tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
	tmp |= TCSTATUS_IXMT;		/* interrupt exempt */
	write_tc_c0_tcstatus(tmp);

	write_tc_c0_tchalt(TCHALT_H);
}

/*
 * Common setup before any secondaries are started
 * Make sure all CPU's are in a sensible state before we boot any of the
 * secondarys
 */
void __init plat_smp_setup(void)
{
	unsigned int mvpconf0, ntc, tc, ncpu = 0;
	unsigned int nvpe;

#ifdef CONFIG_MIPS_MT_FPAFF
	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	if (cpu_has_fpu)
		cpu_set(0, mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */
	if (!cpu_has_mipsmt)
		return;

	/* disable MT so we can configure */
	dvpe();
	dmt();

	/* Put MVPE's into 'configuration state' */
	set_c0_mvpcontrol(MVPCONTROL_VPC);

	mvpconf0 = read_c0_mvpconf0();
	ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;

	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	smp_num_siblings = nvpe;

	/* we'll always have more TC's than VPE's, so loop setting everything
	   to a sensible state */
	for (tc = 0; tc <= ntc; tc++) {
		settc(tc);

		smp_tc_init(tc, mvpconf0);
		ncpu = smp_vpe_init(tc, mvpconf0, ncpu);
	}

	/* Release config state */
	clear_c0_mvpcontrol(MVPCONTROL_VPC);

	/* We'll wait until starting the secondaries before starting MVPE */

	printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
}

void __init plat_prepare_cpus(unsigned int max_cpus)
{
	mips_mt_set_cpuoptions();

	/* set up ipi interrupts */
	if (cpu_has_vint) {
		set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
		set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
	}

	cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
	cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;

	setup_irq(cpu_ipi_resched_irq, &irq_resched);
	setup_irq(cpu_ipi_call_irq, &irq_call);

	set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
	set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
}

/*
 * Setup the PC, SP, and GP of a secondary processor and start it
 * running!
 * smp_bootstrap is the place to resume from
 * __KSTK_TOS(idle) is apparently the stack pointer
 * (unsigned long)idle->thread_info the gp
 * assumes a 1:1 mapping of TC => VPE
 */
void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
{
	struct thread_info *gp = task_thread_info(idle);
	dvpe();
	set_c0_mvpcontrol(MVPCONTROL_VPC);

	settc(cpu);

	/* restart */
	write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);

	/* enable the tc this vpe/cpu will be running */
	write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);

	write_tc_c0_tchalt(0);

	/* enable the VPE */
	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);

	/* stack pointer */
	write_tc_gpr_sp( __KSTK_TOS(idle));

	/* global pointer */
	write_tc_gpr_gp((unsigned long)gp);

	flush_icache_range((unsigned long)gp,
	                   (unsigned long)(gp + sizeof(struct thread_info)));

	/* finally out of configuration and into chaos */
	clear_c0_mvpcontrol(MVPCONTROL_VPC);

	evpe(EVPE_ENABLE);
}

void __cpuinit prom_init_secondary(void)
{
	/* Enable per-cpu interrupts */

	/* This is Malta specific: IPI,performance and timer inetrrupts */
	write_c0_status((read_c0_status() & ~ST0_IM ) |
	                (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7));
}

void __cpuinit prom_smp_finish(void)
{
	write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));

#ifdef CONFIG_MIPS_MT_FPAFF
	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	if (cpu_has_fpu)
		cpu_set(smp_processor_id(), mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */

	local_irq_enable();
}

void prom_cpus_done(void)
{
}

void core_send_ipi(int cpu, unsigned int action)
{
	int i;
	unsigned long flags;
	int vpflags;

	local_irq_save(flags);

	vpflags = dvpe();	/* cant access the other CPU's registers whilst MVPE enabled */

	switch (action) {
	case SMP_CALL_FUNCTION:
		i = C_SW1;
		break;

	case SMP_RESCHEDULE_YOURSELF:
	default:
		i = C_SW0;
		break;
	}

	/* 1:1 mapping of vpe and tc... */
	settc(cpu);
	write_vpe_c0_cause(read_vpe_c0_cause() | i);
	evpe(vpflags);

	local_irq_restore(flags);
}
Commit	Line	Data
340ee4b9	1	/*
340ee4b9 RB	2	* This program is free software; you can distribute it and/or modify it
	3	* under the terms of the GNU General Public License (Version 2) as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope it will be useful, but WITHOUT
	7	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	8	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	9	* for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License along
	12	* with this program; if not, write to the Free Software Foundation, Inc.,
	13	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	14	*
41c594ab RB	15	* Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
	16	* Elizabeth Clarke (beth@mips.com)
	17	* Ralf Baechle (ralf@linux-mips.org)
	18	* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
340ee4b9 RB	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/sched.h>
	22	#include <linux/cpumask.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/compiler.h>
0ab7aefc	25	#include <linux/smp.h>
340ee4b9 RB	26
340ee4b9 RB	27	#include <asm/atomic.h>
41c594ab	28	#include <asm/cacheflush.h>
340ee4b9 RB	29	#include <asm/cpu.h>
	30	#include <asm/processor.h>
	31	#include <asm/system.h>
	32	#include <asm/hardirq.h>
	33	#include <asm/mmu_context.h>
340ee4b9 RB	34	#include <asm/time.h>
	35	#include <asm/mipsregs.h>
	36	#include <asm/mipsmtregs.h>
41c594ab	37	#include <asm/mips_mt.h>
340ee4b9 RB	38
	39	#define MIPS_CPU_IPI_RESCHED_IRQ 0
	40	#define MIPS_CPU_IPI_CALL_IRQ 1
	41
	42	static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
	43
	44	#if 0
	45	static void dump_mtregisters(int vpe, int tc)
	46	{
	47	printk("vpe %d tc %d\n", vpe, tc);
	48
	49	settc(tc);
	50
	51	printk(" c0 status 0x%lx\n", read_vpe_c0_status());
	52	printk(" vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol());
	53	printk(" vpeconf0 0x%lx\n", read_vpe_c0_vpeconf0());
	54	printk(" tcstatus 0x%lx\n", read_tc_c0_tcstatus());
	55	printk(" tcrestart 0x%lx\n", read_tc_c0_tcrestart());
	56	printk(" tcbind 0x%lx\n", read_tc_c0_tcbind());
	57	printk(" tchalt 0x%lx\n", read_tc_c0_tchalt());
	58	}
	59	#endif
	60
	61	void __init sanitize_tlb_entries(void)
	62	{
	63	int i, tlbsiz;
	64	unsigned long mvpconf0, ncpu;
	65
	66	if (!cpu_has_mipsmt)
	67	return;
	68
41c594ab	69	/* Enable VPC */
340ee4b9 RB	70	set_c0_mvpcontrol(MVPCONTROL_VPC);
340ee4b9 RB	71
fdc9bb16 RB	72	back_to_back_c0_hazard();
fdc9bb16 RB	73
340ee4b9 RB	74	/* Disable TLB sharing */
	75	clear_c0_mvpcontrol(MVPCONTROL_STLB);
	76
	77	mvpconf0 = read_c0_mvpconf0();
	78
	79	printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0,
	80	(mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT,
	81	(mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT);
	82
	83	tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT;
	84	ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	85
	86	printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu);
	87
	88	if (tlbsiz > 0) {
	89	/* share them out across the vpe's */
	90	tlbsiz /= ncpu;
	91
	92	printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz);
	93
	94	for (i = 0; i < ncpu; i++) {
	95	settc(i);
	96
	97	if (i == 0)
	98	write_c0_config1((read_c0_config1() & ~(0x3f << 25)) \| (tlbsiz << 25));
	99	else
	100	write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) \|
	101	(tlbsiz << 25));
	102	}
	103	}
	104
	105	clear_c0_mvpcontrol(MVPCONTROL_VPC);
	106	}
	107
937a8015	108	static void ipi_resched_dispatch(void)
340ee4b9	109	{
97dcb82d	110	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
340ee4b9 RB	111	}
340ee4b9 RB	112
937a8015	113	static void ipi_call_dispatch(void)
340ee4b9	114	{
97dcb82d	115	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
340ee4b9 RB	116	}
340ee4b9 RB	117
937a8015	118	static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
340ee4b9 RB	119	{
	120	return IRQ_HANDLED;
	121	}
	122
937a8015	123	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
340ee4b9 RB	124	{
	125	smp_call_function_interrupt();
	126
	127	return IRQ_HANDLED;
	128	}
	129
	130	static struct irqaction irq_resched = {
	131	.handler = ipi_resched_interrupt,
ffe9ee47	132	.flags = IRQF_DISABLED\|IRQF_PERCPU,
340ee4b9 RB	133	.name = "IPI_resched"
	134	};
	135
	136	static struct irqaction irq_call = {
	137	.handler = ipi_call_interrupt,
ffe9ee47	138	.flags = IRQF_DISABLED\|IRQF_PERCPU,
340ee4b9 RB	139	.name = "IPI_call"
	140	};
	141
781b0f8d RB	142	static void __init smp_copy_vpe_config(void)
	143	{
	144	write_vpe_c0_status(
	145	(read_c0_status() & ~(ST0_IM \| ST0_IE \| ST0_KSU)) \| ST0_CU0);
	146
	147	/* set config to be the same as vpe0, particularly kseg0 coherency alg */
	148	write_vpe_c0_config( read_c0_config());
	149
	150	/* make sure there are no software interrupts pending */
	151	write_vpe_c0_cause(0);
	152
	153	/* Propagate Config7 */
	154	write_vpe_c0_config7(read_c0_config7());
70e46f48 RB	155
70e46f48 RB	156	write_vpe_c0_count(read_c0_count());
781b0f8d RB	157	}
	158
	159	static unsigned int __init smp_vpe_init(unsigned int tc, unsigned int mvpconf0,
	160	unsigned int ncpu)
	161	{
	162	if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
	163	return ncpu;
	164
	165	/* Deactivate all but VPE 0 */
	166	if (tc != 0) {
	167	unsigned long tmp = read_vpe_c0_vpeconf0();
	168
	169	tmp &= ~VPECONF0_VPA;
	170
	171	/* master VPE */
	172	tmp \|= VPECONF0_MVP;
	173	write_vpe_c0_vpeconf0(tmp);
	174
	175	/* Record this as available CPU */
	176	cpu_set(tc, phys_cpu_present_map);
	177	__cpu_number_map[tc] = ++ncpu;
	178	__cpu_logical_map[ncpu] = tc;
	179	}
	180
	181	/* Disable multi-threading with TC's */
	182	write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
	183
	184	if (tc != 0)
	185	smp_copy_vpe_config();
	186
	187	return ncpu;
	188	}
	189
	190	static void __init smp_tc_init(unsigned int tc, unsigned int mvpconf0)
	191	{
	192	unsigned long tmp;
	193
	194	if (!tc)
	195	return;
	196
	197	/* bind a TC to each VPE, May as well put all excess TC's
	198	on the last VPE */
	199	if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
	200	write_tc_c0_tcbind(read_tc_c0_tcbind() \| ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
	201	else {
	202	write_tc_c0_tcbind(read_tc_c0_tcbind() \| tc);
	203
	204	/* and set XTC */
	205	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() \| (tc << VPECONF0_XTC_SHIFT));
	206	}
	207
	208	tmp = read_tc_c0_tcstatus();
	209
	210	/* mark not allocated and not dynamically allocatable */
	211	tmp &= ~(TCSTATUS_A \| TCSTATUS_DA);
	212	tmp \|= TCSTATUS_IXMT; /* interrupt exempt */
	213	write_tc_c0_tcstatus(tmp);
	214
	215	write_tc_c0_tchalt(TCHALT_H);
	216	}
	217
340ee4b9 RB	218	/*
	219	* Common setup before any secondaries are started
	220	* Make sure all CPU's are in a sensible state before we boot any of the
	221	* secondarys
	222	*/
781b0f8d	223	void __init plat_smp_setup(void)
340ee4b9	224	{
781b0f8d	225	unsigned int mvpconf0, ntc, tc, ncpu = 0;
0ab7aefc	226	unsigned int nvpe;
340ee4b9	227
f088fc84 RB	228	#ifdef CONFIG_MIPS_MT_FPAFF
	229	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	230	if (cpu_has_fpu)
	231	cpu_set(0, mt_fpu_cpumask);
	232	#endif /* CONFIG_MIPS_MT_FPAFF */
340ee4b9 RB	233	if (!cpu_has_mipsmt)
	234	return;
	235
	236	/* disable MT so we can configure */
	237	dvpe();
	238	dmt();
	239
	240	/* Put MVPE's into 'configuration state' */
	241	set_c0_mvpcontrol(MVPCONTROL_VPC);
	242
781b0f8d RB	243	mvpconf0 = read_c0_mvpconf0();
781b0f8d RB	244	ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
340ee4b9	245
0ab7aefc RB	246	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	247	smp_num_siblings = nvpe;
	248
340ee4b9 RB	249	/* we'll always have more TC's than VPE's, so loop setting everything
340ee4b9 RB	250	to a sensible state */
781b0f8d RB	251	for (tc = 0; tc <= ntc; tc++) {
781b0f8d RB	252	settc(tc);
340ee4b9	253
781b0f8d RB	254	smp_tc_init(tc, mvpconf0);
781b0f8d RB	255	ncpu = smp_vpe_init(tc, mvpconf0, ncpu);
340ee4b9 RB	256	}
	257
	258	/* Release config state */
	259	clear_c0_mvpcontrol(MVPCONTROL_VPC);
	260
	261	/* We'll wait until starting the secondaries before starting MVPE */
	262
781b0f8d	263	printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
41c594ab	264	}
340ee4b9	265
41c594ab RB	266	void __init plat_prepare_cpus(unsigned int max_cpus)
41c594ab RB	267	{
8c976e34 RB	268	mips_mt_set_cpuoptions();
8c976e34 RB	269
340ee4b9 RB	270	/* set up ipi interrupts */
340ee4b9 RB	271	if (cpu_has_vint) {
937a8015 RB	272	set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
937a8015 RB	273	set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
340ee4b9 RB	274	}
340ee4b9 RB	275
97dcb82d AN	276	cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
97dcb82d AN	277	cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
340ee4b9 RB	278
	279	setup_irq(cpu_ipi_resched_irq, &irq_resched);
	280	setup_irq(cpu_ipi_call_irq, &irq_call);
	281
1417836e	282	set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
1417836e	283	set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
340ee4b9 RB	284	}
	285
	286	/*
	287	* Setup the PC, SP, and GP of a secondary processor and start it
	288	* running!
	289	* smp_bootstrap is the place to resume from
	290	* __KSTK_TOS(idle) is apparently the stack pointer
	291	* (unsigned long)idle->thread_info the gp
	292	* assumes a 1:1 mapping of TC => VPE
	293	*/
428ab280	294	void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
340ee4b9	295	{
dc8f6029	296	struct thread_info *gp = task_thread_info(idle);
340ee4b9 RB	297	dvpe();
	298	set_c0_mvpcontrol(MVPCONTROL_VPC);
	299
	300	settc(cpu);
	301
	302	/* restart */
	303	write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
	304
	305	/* enable the tc this vpe/cpu will be running */
	306	write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) \| TCSTATUS_A);
	307
	308	write_tc_c0_tchalt(0);
	309
	310	/* enable the VPE */
	311	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() \| VPECONF0_VPA);
	312
	313	/* stack pointer */
	314	write_tc_gpr_sp( __KSTK_TOS(idle));
	315
	316	/* global pointer */
dc8f6029	317	write_tc_gpr_gp((unsigned long)gp);
340ee4b9	318
41c594ab RB	319	flush_icache_range((unsigned long)gp,
41c594ab RB	320	(unsigned long)(gp + sizeof(struct thread_info)));
340ee4b9 RB	321
	322	/* finally out of configuration and into chaos */
	323	clear_c0_mvpcontrol(MVPCONTROL_VPC);
	324
	325	evpe(EVPE_ENABLE);
	326	}
	327
428ab280	328	void __cpuinit prom_init_secondary(void)
340ee4b9	329	{
ffe9ee47 CD	330	/* Enable per-cpu interrupts */
	331
	332	/* This is Malta specific: IPI,performance and timer inetrrupts */
340ee4b9	333	write_c0_status((read_c0_status() & ~ST0_IM ) \|
ffe9ee47	334	(STATUSF_IP0 \| STATUSF_IP1 \| STATUSF_IP6 \| STATUSF_IP7));
340ee4b9 RB	335	}
340ee4b9 RB	336
428ab280	337	void __cpuinit prom_smp_finish(void)
340ee4b9 RB	338	{
	339	write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
	340
f088fc84 RB	341	#ifdef CONFIG_MIPS_MT_FPAFF
	342	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	343	if (cpu_has_fpu)
	344	cpu_set(smp_processor_id(), mt_fpu_cpumask);
	345	#endif /* CONFIG_MIPS_MT_FPAFF */
	346
340ee4b9 RB	347	local_irq_enable();
	348	}
	349
	350	void prom_cpus_done(void)
	351	{
	352	}
	353
	354	void core_send_ipi(int cpu, unsigned int action)
	355	{
	356	int i;
	357	unsigned long flags;
	358	int vpflags;
	359
49a89efb	360	local_irq_save(flags);
340ee4b9 RB	361
	362	vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
	363
	364	switch (action) {
	365	case SMP_CALL_FUNCTION:
	366	i = C_SW1;
	367	break;
	368
	369	case SMP_RESCHEDULE_YOURSELF:
	370	default:
	371	i = C_SW0;
	372	break;
	373	}
	374
	375	/* 1:1 mapping of vpe and tc... */
	376	settc(cpu);
	377	write_vpe_c0_cause(read_vpe_c0_cause() \| i);
	378	evpe(vpflags);
	379
	380	local_irq_restore(flags);
	381	}